src/arch/sparc/mmu.hh

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#ifndef __ARCH_SPARC_MMU_HH__
#define __ARCH_SPARC_MMU_HH__

#include "arch/generic/mmu.hh"
#include "arch/sparc/page_size.hh"
#include "arch/sparc/tlb.hh"

#include "params/SparcMMU.hh"

namespace gem5
{

namespace SparcISA {

class MMU : public BaseMMU
{
  public:
    MMU(const SparcMMUParams &p)
      : BaseMMU(p)
    {}

    TranslationGenPtr
    translateFunctional(Addr start, Addr size, ThreadContext *tc,
            Mode mode, Request::Flags flags) override
    {
        return TranslationGenPtr(new MMUTranslationGen(
                PageBytes, start, size, tc, this, mode, flags));
    }

    void
    insertItlbEntry(Addr vpn, int partition_id, int context_id, bool real,
        const PageTableEntry& PTE, int entry=-1)
    {
        static_cast<TLB*>(itb)->insert(vpn, partition_id,
            context_id, real, PTE, entry);
    }

    void
    insertDtlbEntry(Addr vpn, int partition_id, int context_id, bool real,
        const PageTableEntry& PTE, int entry=-1)
    {
        static_cast<TLB*>(dtb)->insert(vpn, partition_id,
            context_id, real, PTE, entry);
    }
};

} // namespace SparcISA
} // namespace gem5

#endif  // __ARCH_SPARC_MMU_HH__