| # -*- mode:python -*- |
| |
| # Copyright (c) 2006 The Regents of The University of Michigan |
| # All rights reserved. |
| # |
| # Redistribution and use in source and binary forms, with or without |
| # modification, are permitted provided that the following conditions are |
| # met: redistributions of source code must retain the above copyright |
| # notice, this list of conditions and the following disclaimer; |
| # redistributions in binary form must reproduce the above copyright |
| # notice, this list of conditions and the following disclaimer in the |
| # documentation and/or other materials provided with the distribution; |
| # neither the name of the copyright holders nor the names of its |
| # contributors may be used to endorse or promote products derived from |
| # this software without specific prior written permission. |
| # |
| # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| # |
| # Authors: Nathan Binkert |
| |
| Import('*') |
| |
| SimObject('Bridge.py') |
| SimObject('Bus.py') |
| SimObject('PhysicalMemory.py') |
| SimObject('MemObject.py') |
| |
| # Workaround for bug in SCons version > 0.97d20071212 |
| # Scons bug id: 2006 M5 Bug id: 308 |
| Dir('config') |
| |
| Source('bridge.cc') |
| Source('bus.cc') |
| Source('dram.cc') |
| Source('mem_object.cc') |
| Source('packet.cc') |
| Source('physical.cc') |
| Source('port.cc') |
| Source('tport.cc') |
| |
| if env['FULL_SYSTEM']: |
| Source('vport.cc') |
| else: |
| Source('page_table.cc') |
| Source('translating_port.cc') |
| |
| TraceFlag('Bus') |
| TraceFlag('BusAddrRanges') |
| TraceFlag('BusBridge') |
| TraceFlag('LLSC') |
| TraceFlag('MMU') |
| TraceFlag('MemoryAccess') |