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/*
* Copyright (c) 2012, 2018 ARM Limited
* All rights reserved.
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "cpu/simple/noncaching.hh"
NonCachingSimpleCPU::NonCachingSimpleCPU(NonCachingSimpleCPUParams *p)
: AtomicSimpleCPU(p)
{
}
void
NonCachingSimpleCPU::verifyMemoryMode() const
{
if (!(system->isAtomicMode() && system->bypassCaches())) {
fatal("The direct CPU requires the memory system to be in the "
"'atomic_noncaching' mode.\n");
}
}
Tick
NonCachingSimpleCPU::sendPacket(MasterPort &port, const PacketPtr &pkt)
{
if (system->isMemAddr(pkt->getAddr())) {
system->getPhysMem().access(pkt);
return 0;
} else {
return port.sendAtomic(pkt);
}
}
NonCachingSimpleCPU *
NonCachingSimpleCPUParams::create()
{
numThreads = 1;
if (!FullSystem && workload.size() != 1)
fatal("only one workload allowed");
return new NonCachingSimpleCPU(this);
}