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# Copyright (c) 2014 ARM Limited
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#
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# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
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# met: redistributions of source code must retain the above copyright
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# redistributions in binary form must reproduce the above copyright
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# neither the name of the copyright holders nor the names of its
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# this software without specific prior written permission.
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from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
class MemChecker(SimObject):
type = 'MemChecker'
cxx_header = "mem/mem_checker.hh"
class MemCheckerMonitor(SimObject):
type = 'MemCheckerMonitor'
cxx_header = "mem/mem_checker_monitor.hh"
# one port in each direction
master = MasterPort("Master port")
slave = SlavePort("Slave port")
cpu_side = SlavePort("Alias for slave")
mem_side = MasterPort("Alias for master")
warn_only = Param.Bool(False, "Warn about violations only")
memchecker = Param.MemChecker("Instance shared with other monitors")