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# Copyright (c) 2012-2013 ARM Limited
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#
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# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
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# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2006-2007 The Regents of The University of Michigan
# Copyright (c) 2015 The University of Bologna
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# modification, are permitted provided that the following conditions are
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from m5.params import *
from m5.objects.ClockedObject import ClockedObject
# SerialLink is a simple variation of the Bridge class, with the ability to
# account for the latency of packet serialization.
class SerialLink(ClockedObject):
type = 'SerialLink'
cxx_header = "mem/serial_link.hh"
slave = SlavePort('Slave port')
master = MasterPort('Master port')
req_size = Param.Unsigned(16, "The number of requests to buffer")
resp_size = Param.Unsigned(16, "The number of responses to buffer")
delay = Param.Latency('0ns', "The latency of this serial_link")
ranges = VectorParam.AddrRange([AllMemory],
"Address ranges to pass through the serial_link")
# Bandwidth of the serial link is determined by the clock domain which the
# link belongs to and the number of lanes:
num_lanes = Param.Unsigned(1, "Number of parallel lanes inside the serial"
"link. (aka. lane width)")
link_speed = Param.UInt64(1, "Gb/s Speed of each parallel lane inside the"
"serial link. (aka. lane speed)")