src/arch/x86/regs/float.hh

/*
 * Copyright (c) 2007 The Hewlett-Packard Development Company
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 * met: redistributions of source code must retain the above copyright
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 * this software without specific prior written permission.
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#ifndef __ARCH_X86_FLOATREGS_HH__
#define __ARCH_X86_FLOATREGS_HH__

#include "arch/x86/x86_traits.hh"
#include "base/bitunion.hh"

namespace gem5
{

namespace X86ISA
{
    enum FloatRegIndex
    {
        // MMX/X87 registers
        FLOATREG_MMX_BASE,
        FLOATREG_FPR_BASE = FLOATREG_MMX_BASE,
        FLOATREG_MMX0 = FLOATREG_MMX_BASE,
        FLOATREG_MMX1,
        FLOATREG_MMX2,
        FLOATREG_MMX3,
        FLOATREG_MMX4,
        FLOATREG_MMX5,
        FLOATREG_MMX6,
        FLOATREG_MMX7,

        FLOATREG_FPR0 = FLOATREG_FPR_BASE,
        FLOATREG_FPR1,
        FLOATREG_FPR2,
        FLOATREG_FPR3,
        FLOATREG_FPR4,
        FLOATREG_FPR5,
        FLOATREG_FPR6,
        FLOATREG_FPR7,

        FLOATREG_XMM_BASE = FLOATREG_MMX_BASE + NumMMXRegs,
        FLOATREG_XMM0_LOW = FLOATREG_XMM_BASE,
        FLOATREG_XMM0_HIGH,
        FLOATREG_XMM1_LOW,
        FLOATREG_XMM1_HIGH,
        FLOATREG_XMM2_LOW,
        FLOATREG_XMM2_HIGH,
        FLOATREG_XMM3_LOW,
        FLOATREG_XMM3_HIGH,
        FLOATREG_XMM4_LOW,
        FLOATREG_XMM4_HIGH,
        FLOATREG_XMM5_LOW,
        FLOATREG_XMM5_HIGH,
        FLOATREG_XMM6_LOW,
        FLOATREG_XMM6_HIGH,
        FLOATREG_XMM7_LOW,
        FLOATREG_XMM7_HIGH,
        FLOATREG_XMM8_LOW,
        FLOATREG_XMM8_HIGH,
        FLOATREG_XMM9_LOW,
        FLOATREG_XMM9_HIGH,
        FLOATREG_XMM10_LOW,
        FLOATREG_XMM10_HIGH,
        FLOATREG_XMM11_LOW,
        FLOATREG_XMM11_HIGH,
        FLOATREG_XMM12_LOW,
        FLOATREG_XMM12_HIGH,
        FLOATREG_XMM13_LOW,
        FLOATREG_XMM13_HIGH,
        FLOATREG_XMM14_LOW,
        FLOATREG_XMM14_HIGH,
        FLOATREG_XMM15_LOW,
        FLOATREG_XMM15_HIGH,

        FLOATREG_MICROFP_BASE = FLOATREG_XMM_BASE + 2 * NumXMMRegs,
        FLOATREG_MICROFP0 = FLOATREG_MICROFP_BASE,
        FLOATREG_MICROFP1,
        FLOATREG_MICROFP2,
        FLOATREG_MICROFP3,
        FLOATREG_MICROFP4,
        FLOATREG_MICROFP5,
        FLOATREG_MICROFP6,
        FLOATREG_MICROFP7,

        NUM_FLOATREGS = FLOATREG_MICROFP_BASE + NumMicroFpRegs
    };

    static inline FloatRegIndex
    FLOATREG_MMX(int index)
    {
        return (FloatRegIndex)(FLOATREG_MMX_BASE + index);
    }

    static inline FloatRegIndex
    FLOATREG_FPR(int index)
    {
        return (FloatRegIndex)(FLOATREG_FPR_BASE + index);
    }

    static inline FloatRegIndex
    FLOATREG_XMM_LOW(int index)
    {
        return (FloatRegIndex)(FLOATREG_XMM_BASE + 2 * index);
    }

    static inline FloatRegIndex
    FLOATREG_XMM_HIGH(int index)
    {
        return (FloatRegIndex)(FLOATREG_XMM_BASE + 2 * index + 1);
    }

    static inline FloatRegIndex
    FLOATREG_MICROFP(int index)
    {
        return (FloatRegIndex)(FLOATREG_MICROFP_BASE + index);
    }

    static inline FloatRegIndex
    FLOATREG_STACK(int index, int top)
    {
        return FLOATREG_FPR((top + index + 8) % 8);
    }

    // Each 128 bit xmm register is broken into two effective 64 bit registers.
    // Add 8 for the indices that are mapped over the fp stack
    const int NumFloatRegs =
        NumMMXRegs + 2 * NumXMMRegs + NumMicroFpRegs + 8;

} // namespace X86ISA
} // namespace gem5

#endif // __ARCH_X86_FLOATREGS_HH__