Brad Beckmann | ab2f864 | 2010-01-29 20:29:40 -0800 | [diff] [blame^] | 1 | # Copyright (c) 2006-2007 The Regents of The University of Michigan |
| 2 | # Copyright (c) 2009 Advanced Micro Devices, Inc. |
| 3 | # All rights reserved. |
| 4 | # |
| 5 | # Redistribution and use in source and binary forms, with or without |
| 6 | # modification, are permitted provided that the following conditions are |
| 7 | # met: redistributions of source code must retain the above copyright |
| 8 | # notice, this list of conditions and the following disclaimer; |
| 9 | # redistributions in binary form must reproduce the above copyright |
| 10 | # notice, this list of conditions and the following disclaimer in the |
| 11 | # documentation and/or other materials provided with the distribution; |
| 12 | # neither the name of the copyright holders nor the names of its |
| 13 | # contributors may be used to endorse or promote products derived from |
| 14 | # this software without specific prior written permission. |
| 15 | # |
| 16 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 17 | # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 18 | # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 19 | # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 20 | # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 21 | # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 22 | # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 23 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 24 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 26 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | # |
| 28 | # Authors: Ron Dreslinski |
| 29 | # Brad Beckmann |
| 30 | |
| 31 | import m5 |
| 32 | from m5.objects import * |
| 33 | from m5.defines import buildEnv |
| 34 | from m5.util import addToPath |
| 35 | import os, optparse, sys |
| 36 | |
| 37 | if buildEnv['FULL_SYSTEM']: |
| 38 | panic("This script requires system-emulation mode (*_SE).") |
| 39 | |
| 40 | # Get paths we might need. It's expected this file is in m5/configs/example. |
| 41 | config_path = os.path.dirname(os.path.abspath(__file__)) |
| 42 | config_root = os.path.dirname(config_path) |
| 43 | m5_root = os.path.dirname(config_root) |
| 44 | addToPath(config_root+'/configs/common') |
| 45 | addToPath(config_root+'/configs/ruby') |
| 46 | |
| 47 | import Ruby |
| 48 | |
| 49 | parser = optparse.OptionParser() |
| 50 | |
| 51 | # |
| 52 | # Set the default cache size and associativity to be very small to encourage |
| 53 | # races between requests and writebacks. |
| 54 | # |
| 55 | parser.add_option("--l1d_size", type="string", default="256B") |
| 56 | parser.add_option("--l1i_size", type="string", default="256B") |
| 57 | parser.add_option("--l2_size", type="string", default="512B") |
| 58 | parser.add_option("--l1d_assoc", type="int", default=2) |
| 59 | parser.add_option("--l1i_assoc", type="int", default=2) |
| 60 | parser.add_option("--l2_assoc", type="int", default=2) |
| 61 | |
| 62 | execfile(os.path.join(config_root, "configs/common", "Options.py")) |
| 63 | |
| 64 | (options, args) = parser.parse_args() |
| 65 | |
| 66 | # |
| 67 | # create the tester and system, including ruby |
| 68 | # |
| 69 | tester = RubyTester(checks_to_complete = 100, wakeup_frequency = 10) |
| 70 | |
| 71 | system = System(physmem = PhysicalMemory()) |
| 72 | |
| 73 | system.ruby = Ruby.create_system(options, system.physmem) |
| 74 | |
| 75 | assert(options.num_cpus == len(system.ruby.cpu_ruby_ports)) |
| 76 | |
| 77 | # |
| 78 | # The tester is most effective when randomization is turned on and |
| 79 | # artifical delay is randomly inserted on messages |
| 80 | # |
| 81 | system.ruby.randomization = True |
| 82 | |
| 83 | for ruby_port in system.ruby.cpu_ruby_ports: |
| 84 | # |
| 85 | # Tie the ruby tester ports to the ruby cpu ports |
| 86 | # |
| 87 | tester.cpuPort = ruby_port.port |
| 88 | |
| 89 | # |
| 90 | # Tell the sequencer this is the ruby tester so that it |
| 91 | # copies the subblock back to the checker |
| 92 | # |
| 93 | ruby_port.using_ruby_tester = True |
| 94 | |
| 95 | # ----------------------- |
| 96 | # run simulation |
| 97 | # ----------------------- |
| 98 | |
| 99 | root = Root( system = system ) |
| 100 | root.system.mem_mode = 'timing' |
| 101 | |
| 102 | # Not much point in this being higher than the L1 latency |
| 103 | m5.ticks.setGlobalFrequency('1ns') |