- 2dd0eed cpu: Fix fast build broken due to unused variable by Giacomo Travaglini · 5 years ago
- 9e340ba systemc: Add a systemc_home directory which maps to the ext headers. by Gabe Black · 5 years ago
- 95c0aef systemc: Make an include in src/systemc/ext use a relative path. by Gabe Black · 5 years ago
- d39573a cpu: Added 8KB and 64KB TAGE-SC-L branch predictor by Javier Bueno · 5 years ago
- 224f2d5 configs: simpoint-profile usable with NonCachingCPUs only by Giacomo Travaglini · 5 years ago
- e67a3d1 python: Remove uses of tuple unpacking in function params by Andreas Sandberg · 5 years ago
- 23af972 python: Replace deprecated repr syntax by Andreas Sandberg · 5 years ago
- ac00ec1 python: Switch from using compare to key in list sort by Andreas Sandberg · 5 years ago
- c5e8e0e tests: add cpu tests to the new testing infrastructure by Ayaz Akram · 5 years ago
- 308a558 tests: Move test programs paths to related test scripts by Ayaz Akram · 5 years ago
- fe29653 sim-se: update the arm kernel version by Ayaz Akram · 5 years ago
- 9ac977d tests: Convert memtest to new framework by Jason Lowe-Power · 6 years ago
- 3086d51 tests: Convert tgen-simple-memory to new framework by Jason Lowe-Power · 6 years ago
- 5cd4248 python: Replace dict.has_key with 'key in dict' by Andreas Sandberg · 5 years ago
- 5cf312e python: Add missing defines import by Andreas Sandberg · 5 years ago
- 6e08be1 python: Replace DictMixin with Mapping / MutableMapping by Andreas Sandberg · 5 years ago
- bc42d2f python: Replace orderdict with collections.OrderedDict by Andreas Sandberg · 5 years ago
- 31dff7f python: Update use of exec to work with Python 3 by Andreas Sandberg · 5 years ago
- b3195c4 python: Switch to using open instead of file by Andreas Sandberg · 5 years ago
- 626e8fa mem-cache: Irregular Stream Buffer Prefetcher by Javier Bueno · 5 years ago
- 9d4d620 system-arm: Fix dtsi dependencies in Makefile by Kevin Brodsky · 5 years ago
- ee9293d mem-cache: Added the Delta Correlating Prediction Tables Prefetcher by Javier Bueno · 5 years ago
- 1f008aa tests: Rewrite Makefiles for pthreads test by Andreas Sandberg · 5 years ago
- ef71a98 python: Don't assume SimObjects live in the global namespace by Andreas Sandberg · 5 years ago
- 9fbfb45 arch-mips: Remove unused Python file by Andreas Sandberg · 5 years ago
- fa21127 python: Make exception handling Python 3 safe by Andreas Sandberg · 5 years ago
- 6ba4545 python: Fix native module initialisation on Python 3 by Andreas Sandberg · 5 years ago
- 15e497d mem-ruby: Fixing Topology by Pouya Fotouhi · 5 years ago
- 8d79332 mem-ruby: Fixing MESI Three Level by Pouya Fotouhi · 5 years ago
- 502af7c systemc: config: Don't inject a custom argv[0] in sc_main.py. by Gabe Black · 5 years ago
- eb5e99e systemc: configs: Add a very simple config which just runs sc_main. by Gabe Black · 5 years ago
- bdef435 systemc: Change the type of a loop counter to avoid a warning. by Gabe Black · 5 years ago
- 8174d7c scons: Change an = to a += when accumulating sources from filters. by Gabe Black · 5 years ago
- da6e8b0 systemc: scons: Specify RPATH as a list. by Gabe Black · 5 years ago
- bcf6983 cpu: Proposal for changing the indirect branch predictor interface by Jairo Balart · 5 years ago
- 4f4846c riscv: fix AMO, LR and SC instructions by Tuan Ta · 6 years ago
- 25dc765 cpu: support atomic memory request type with AtomicOpFunctor by Tuan Ta · 6 years ago
- 165a7da kern,sim: implement FUTEX_WAKE_OP by Moyang Wang · 6 years ago
- 758b62c sim, kern: support FUTEX_CMP_REQUEUE by Moyang Wang · 6 years ago
- 42b063a sim: handle the case when there're not enough HW thread contexts by Tuan Ta · 6 years ago
- 2eb57c7 riscv: fixed syscall return value by Tuan Ta · 6 years ago
- e437086 cpu: fix how branching is handled when a thread is suspended in MinorCPU by Tuan Ta · 6 years ago
- 6a6668b cpu: stop scheduling suspended threads in all stages of MinorCPU by Tuan Ta · 6 years ago
- e74921e riscv: ignore nanosleep syscall by Tuan Ta · 6 years ago
- bae0edb sim,cpu: make exit_group halt all threads in a group by Tuan Ta · 6 years ago
- 72d1d29 arch-riscv: initialize RISC-V's thread pointer register in clone syscall by Tuan Ta · 6 years ago
- cf45f22 sim,kern: support FUTEX_WAIT_BITSET and FUTEX_WAKE_BITSET ops by Tuan Ta · 6 years ago
- e541567 cpu: fixed how O3 CPU executes an exit system call by Tuan Ta · 6 years ago
- aefae9d arch-arm: Fix Virtual interrupts in AArch64 by Giacomo Travaglini · 5 years ago
- 5508866 arch-arm: Fix extra comma in b7ce897f1e9545785bde982f72d04830c19d9a30 by Giacomo Travaglini · 5 years ago
- b7ce897 arch-arm: Allow ArmPPI usage for PMU by Giacomo Travaglini · 5 years ago
- c2b6aac arch-arm: Fix initialization of PMU counters by Ruben Ayrapetyan · 5 years ago
- 34b73de configs, arch-arm: Using AddrRange for Realview mem_regions by Giacomo Travaglini · 5 years ago
- 53eadea configs: Unifiy interpretation of Realview mem_regions by Giacomo Travaglini · 5 years ago
- 9c5373c arch-riscv: Enable support for riscv 32-bit in SE mode. by Austin Harris · 5 years ago
- ea487f9 riscv: remove NonSpeculative flag from fence inst by Tuan Ta · 6 years ago
- 02dafc5 cpu: fix how a thread starts up in MinorCPU by Tuan Ta · 6 years ago
- 8efcc0f arch-riscv: Initialize interrupt mask by Tuan Ta · 5 years ago
- ff5ad43 scons: fix unused auto-generated blob variable in clang by Ciro Santilli · 5 years ago
- 9309797 sim: added missed macro definition on MacOS by Andrea Mondelli · 5 years ago
- 1989ce9 misc: added missing override specifier by Andrea Mondelli · 5 years ago
- 02d2d7b cpu: Made the Loop Predictor a SimObject by Javier Bueno · 5 years ago
- 4ba8923 cpu: Made TAGE a SimObject that can be used by other predictors by Jairo Balart · 5 years ago
- f0e2caf riscv: Get rid of ISA specific register types in Interrupts. by Austin Harris · 5 years ago
- 2775f55 mem-cache: Updated version of the Signature Path Prefetcher by Javier Bueno · 5 years ago
- 6684d61 dev, arm: Removed contextId variable by Anouk Van Laer · 5 years ago
- a119a96 cpu, arch: Replace the CCReg type with RegVal. by Gabe Black · 5 years ago
- fbdf0b6 python: Remove getCode() type workaround by Andreas Sandberg · 5 years ago
- 244a984 sim: Prepare C++ side for Python 3 by Andreas Sandberg · 5 years ago
- 2d1723a tests: Add a helper to run external scripts by Andreas Sandberg · 5 years ago
- cc59815 tests: Don't override tick rate in Ruby tests by Andreas Sandberg · 5 years ago
- b6a124d power: Get rid of some ISA specific register types. by Gabe Black · 5 years ago
- 6ba2888 null: Get rid of some register type definitions. by Gabe Black · 5 years ago
- cdfb486 mips: Stop using architecture specific register types. by Gabe Black · 5 years ago
- c8a744f alpha: Stop using architecture specific register types. by Gabe Black · 5 years ago
- b859a70 x86: Stop using/defining some ISA specific register types. by Gabe Black · 5 years ago
- ad775e0 riscv: Get rid of some ISA specific register types. by Gabe Black · 5 years ago
- 5edfb67 arch: cpu: Rename *FloatRegBits* to *FloatReg*. by Gabe Black · 5 years ago
- 2547416 arch,cpu: Add vector predicate registers by Giacomo Gabrielli · 6 years ago
- c6f5db8 configs: Enable DTB autogeneration in starter_fs.py by Giacomo Travaglini · 5 years ago
- 00ef23b arch-arm, configs: Create single instance of DTB autogeneration by Giacomo Travaglini · 5 years ago
- b2d24ff tests: fix arm regression due to kernel not found by Ciro Santilli · 5 years ago
- 9048ef0 configs: fs.py remove --generate-dtb and enable it by default by Ciro Santilli · 5 years ago
- 12eca7a configs, arch-arm: don't search for default DTB and kernel by Ciro Santilli · 5 years ago
- 9b6f0a9 arch-arm: Remove floatReg operand type by Giacomo Travaglini · 5 years ago
- 96e72d6 arch-arm: Use VecElem instead of FloatReg for FP instruction by Giacomo Travaglini · 5 years ago
- d8dd86d arch: Fix VecElem Operand generation in ISA parser by Giacomo Travaglini · 5 years ago
- 3d15150 cpu, arch, arch-arm: Wire unused VecElem code in the O3 model by Giacomo Travaglini · 5 years ago
- 204e932 cpu: O3 rename using the flatIndex instead of index by Giacomo Travaglini · 5 years ago
- 47fd797 arch-arm: Inital vector rename mode depending on A32/A64 by Giacomo Travaglini · 5 years ago
- b045de7 cpu: Fix VecElemClass bugs in cpu models by Giacomo Travaglini · 5 years ago
- e7c8154 cpu: Add VecElem entries in MinorCPU Scoreboard by Giacomo Travaglini · 5 years ago
- 4d44889 arch-arm: Remove unused float operands by Giacomo Travaglini · 5 years ago
- 3ec5afd arch: Provide traceback when parsing ISA code by Giacomo Travaglini · 5 years ago
- 48f3829 python: Always throw TypeError on slave-slave connections by Nicholas Lindsay · 6 years ago
- db190b8 hsail: Remove the MiscReg type. by Gabe Black · 5 years ago
- d65f3f9 base: arch: Get rid of the now unused FloatRegVal type. by Gabe Black · 5 years ago
- 34064c4 dev-arm: fix --generate-dtb for ARM by Ciro Santilli · 5 years ago
- 51becd2 cpu-o3: O3 LSQ Generalisation by Rekai Gonzalez-Alberquilla · 7 years ago
- 6379beb arch-arm: Implement LoadAcquire/StoreRelease in AArch32 by Giacomo Travaglini · 5 years ago
