1. fa21127 python: Make exception handling Python 3 safe by Andreas Sandberg · 5 years ago
  2. 6ba4545 python: Fix native module initialisation on Python 3 by Andreas Sandberg · 5 years ago
  3. 15e497d mem-ruby: Fixing Topology by Pouya Fotouhi · 5 years ago
  4. 8d79332 mem-ruby: Fixing MESI Three Level by Pouya Fotouhi · 5 years ago
  5. 502af7c systemc: config: Don't inject a custom argv[0] in sc_main.py. by Gabe Black · 5 years ago
  6. eb5e99e systemc: configs: Add a very simple config which just runs sc_main. by Gabe Black · 5 years ago
  7. bdef435 systemc: Change the type of a loop counter to avoid a warning. by Gabe Black · 5 years ago
  8. 8174d7c scons: Change an = to a += when accumulating sources from filters. by Gabe Black · 5 years ago
  9. da6e8b0 systemc: scons: Specify RPATH as a list. by Gabe Black · 5 years ago
  10. bcf6983 cpu: Proposal for changing the indirect branch predictor interface by Jairo Balart · 5 years ago
  11. 4f4846c riscv: fix AMO, LR and SC instructions by Tuan Ta · 6 years ago
  12. 25dc765 cpu: support atomic memory request type with AtomicOpFunctor by Tuan Ta · 6 years ago
  13. 165a7da kern,sim: implement FUTEX_WAKE_OP by Moyang Wang · 6 years ago
  14. 758b62c sim, kern: support FUTEX_CMP_REQUEUE by Moyang Wang · 6 years ago
  15. 42b063a sim: handle the case when there're not enough HW thread contexts by Tuan Ta · 6 years ago
  16. 2eb57c7 riscv: fixed syscall return value by Tuan Ta · 6 years ago
  17. e437086 cpu: fix how branching is handled when a thread is suspended in MinorCPU by Tuan Ta · 6 years ago
  18. 6a6668b cpu: stop scheduling suspended threads in all stages of MinorCPU by Tuan Ta · 6 years ago
  19. e74921e riscv: ignore nanosleep syscall by Tuan Ta · 6 years ago
  20. bae0edb sim,cpu: make exit_group halt all threads in a group by Tuan Ta · 6 years ago
  21. 72d1d29 arch-riscv: initialize RISC-V's thread pointer register in clone syscall by Tuan Ta · 6 years ago
  22. cf45f22 sim,kern: support FUTEX_WAIT_BITSET and FUTEX_WAKE_BITSET ops by Tuan Ta · 6 years ago
  23. e541567 cpu: fixed how O3 CPU executes an exit system call by Tuan Ta · 6 years ago
  24. aefae9d arch-arm: Fix Virtual interrupts in AArch64 by Giacomo Travaglini · 5 years ago
  25. 5508866 arch-arm: Fix extra comma in b7ce897f1e9545785bde982f72d04830c19d9a30 by Giacomo Travaglini · 5 years ago
  26. b7ce897 arch-arm: Allow ArmPPI usage for PMU by Giacomo Travaglini · 5 years ago
  27. c2b6aac arch-arm: Fix initialization of PMU counters by Ruben Ayrapetyan · 5 years ago
  28. 34b73de configs, arch-arm: Using AddrRange for Realview mem_regions by Giacomo Travaglini · 5 years ago
  29. 53eadea configs: Unifiy interpretation of Realview mem_regions by Giacomo Travaglini · 5 years ago
  30. 9c5373c arch-riscv: Enable support for riscv 32-bit in SE mode. by Austin Harris · 5 years ago
  31. ea487f9 riscv: remove NonSpeculative flag from fence inst by Tuan Ta · 6 years ago
  32. 02dafc5 cpu: fix how a thread starts up in MinorCPU by Tuan Ta · 6 years ago
  33. 8efcc0f arch-riscv: Initialize interrupt mask by Tuan Ta · 5 years ago
  34. ff5ad43 scons: fix unused auto-generated blob variable in clang by Ciro Santilli · 5 years ago
  35. 9309797 sim: added missed macro definition on MacOS by Andrea Mondelli · 5 years ago
  36. 1989ce9 misc: added missing override specifier by Andrea Mondelli · 5 years ago
  37. 02d2d7b cpu: Made the Loop Predictor a SimObject by Javier Bueno · 5 years ago
  38. 4ba8923 cpu: Made TAGE a SimObject that can be used by other predictors by Jairo Balart · 5 years ago
  39. f0e2caf riscv: Get rid of ISA specific register types in Interrupts. by Austin Harris · 5 years ago
  40. 2775f55 mem-cache: Updated version of the Signature Path Prefetcher by Javier Bueno · 5 years ago
  41. 6684d61 dev, arm: Removed contextId variable by Anouk Van Laer · 5 years ago
  42. a119a96 cpu, arch: Replace the CCReg type with RegVal. by Gabe Black · 5 years ago
  43. fbdf0b6 python: Remove getCode() type workaround by Andreas Sandberg · 5 years ago
  44. 244a984 sim: Prepare C++ side for Python 3 by Andreas Sandberg · 5 years ago
  45. 2d1723a tests: Add a helper to run external scripts by Andreas Sandberg · 5 years ago
  46. cc59815 tests: Don't override tick rate in Ruby tests by Andreas Sandberg · 5 years ago
  47. b6a124d power: Get rid of some ISA specific register types. by Gabe Black · 5 years ago
  48. 6ba2888 null: Get rid of some register type definitions. by Gabe Black · 5 years ago
  49. cdfb486 mips: Stop using architecture specific register types. by Gabe Black · 5 years ago
  50. c8a744f alpha: Stop using architecture specific register types. by Gabe Black · 5 years ago
  51. b859a70 x86: Stop using/defining some ISA specific register types. by Gabe Black · 5 years ago
  52. ad775e0 riscv: Get rid of some ISA specific register types. by Gabe Black · 5 years ago
  53. 5edfb67 arch: cpu: Rename *FloatRegBits* to *FloatReg*. by Gabe Black · 5 years ago
  54. 2547416 arch,cpu: Add vector predicate registers by Giacomo Gabrielli · 6 years ago
  55. c6f5db8 configs: Enable DTB autogeneration in starter_fs.py by Giacomo Travaglini · 5 years ago
  56. 00ef23b arch-arm, configs: Create single instance of DTB autogeneration by Giacomo Travaglini · 5 years ago
  57. b2d24ff tests: fix arm regression due to kernel not found by Ciro Santilli · 5 years ago
  58. 9048ef0 configs: fs.py remove --generate-dtb and enable it by default by Ciro Santilli · 5 years ago
  59. 12eca7a configs, arch-arm: don't search for default DTB and kernel by Ciro Santilli · 5 years ago
  60. 9b6f0a9 arch-arm: Remove floatReg operand type by Giacomo Travaglini · 5 years ago
  61. 96e72d6 arch-arm: Use VecElem instead of FloatReg for FP instruction by Giacomo Travaglini · 5 years ago
  62. d8dd86d arch: Fix VecElem Operand generation in ISA parser by Giacomo Travaglini · 5 years ago
  63. 3d15150 cpu, arch, arch-arm: Wire unused VecElem code in the O3 model by Giacomo Travaglini · 5 years ago
  64. 204e932 cpu: O3 rename using the flatIndex instead of index by Giacomo Travaglini · 5 years ago
  65. 47fd797 arch-arm: Inital vector rename mode depending on A32/A64 by Giacomo Travaglini · 5 years ago
  66. b045de7 cpu: Fix VecElemClass bugs in cpu models by Giacomo Travaglini · 5 years ago
  67. e7c8154 cpu: Add VecElem entries in MinorCPU Scoreboard by Giacomo Travaglini · 5 years ago
  68. 4d44889 arch-arm: Remove unused float operands by Giacomo Travaglini · 5 years ago
  69. 3ec5afd arch: Provide traceback when parsing ISA code by Giacomo Travaglini · 5 years ago
  70. 48f3829 python: Always throw TypeError on slave-slave connections by Nicholas Lindsay · 6 years ago
  71. db190b8 hsail: Remove the MiscReg type. by Gabe Black · 5 years ago
  72. d65f3f9 base: arch: Get rid of the now unused FloatRegVal type. by Gabe Black · 5 years ago
  73. 34064c4 dev-arm: fix --generate-dtb for ARM by Ciro Santilli · 5 years ago
  74. 51becd2 cpu-o3: O3 LSQ Generalisation by Rekai Gonzalez-Alberquilla · 7 years ago
  75. 6379beb arch-arm: Implement LoadAcquire/StoreRelease in AArch32 by Giacomo Travaglini · 5 years ago
  76. 163065d arch-arm: IsStoreConditional flag set depending on flavor by Giacomo Travaglini · 5 years ago
  77. 51aba75 arch-arm: Remove SWP and SWPB instructions by Giacomo Travaglini · 5 years ago
  78. e1ef027 systemc: Fix TLM related includes. by Gabe Black · 5 years ago
  79. 298e8b8 arm: Replace MiscReg with RegVal in utility.(hh|cc). by Gabe Black · 5 years ago
  80. 964e610 mem-ruby: Fix missing TBE allocation and deallocation by Zicong Wang · 5 years ago
  81. 1ab1500 sparc: Get rid of some register type definitions. by Gabe Black · 6 years ago
  82. 230b892 arch: cpu: Stop passing around misc registers by reference. by Gabe Black · 6 years ago
  83. 774770a arm: Get rid of some register type definitions. by Gabe Black · 6 years ago
  84. 2b80f58 arm: dev: Replace ArmISA::MiscReg with RegVal in the GIC v3 model. by Gabe Black · 5 years ago
  85. 0f024be arch-arm: implement the GDB XML target description for ARM by Ciro Santilli · 5 years ago
  86. 6064582 ext: import GDB XML target description files for arm by Ciro Santilli · 5 years ago
  87. 9712a63 scons: add helpers to access GDB XML description files by Ciro Santilli · 5 years ago
  88. f2bda87 scons: allow embedding arbitrary blobs into the gem5 executable by Ciro Santilli · 5 years ago
  89. af5a23a base: add support for GDB's XML architecture definition by Ciro Santilli · 5 years ago
  90. 12eac0c arch-arm: Move AArch32 IMPLEMENTATION DEFINED registers by Giacomo Travaglini · 6 years ago
  91. a0649ee mem: Add tryTiming suppport to CommMonitor by Sascha Bischoff · 5 years ago
  92. e9d9575 sim-se add readv and modifies writev by Brandon Potter · 6 years ago
  93. 7936e63 sim-se: add ability to get/set sock metadata by Brandon Potter · 6 years ago
  94. bc74c58 sim-se: add syscalls related to polling by Brandon Potter · 6 years ago
  95. c4e67f6 sim-se: add calls for network transmissions by Brandon Potter · 6 years ago
  96. a2ed7d5 sim-se: add socket-based functionality by Brandon Potter · 6 years ago
  97. 2c9f7eb base: Fix unitialized storage by Daniel R. Carvalho · 5 years ago
  98. 5dda7fb tests: Fix tests/main.py so it can be run from anywhere. by Gabe Black · 5 years ago
  99. fa0c2bd mem: Allow inserts in the begining of a packet queue by Nikos Nikoleris · 5 years ago
  100. ccc50b7 mem: Determine if a packet queue forces ordering at construction by Nikos Nikoleris · 5 years ago