| |
| ---------- Begin Simulation Statistics ---------- |
| sim_seconds 0.075963 # Number of seconds simulated |
| sim_ticks 75962996000 # Number of ticks simulated |
| final_tick 75962996000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| sim_freq 1000000000000 # Frequency of simulated ticks |
| host_inst_rate 82470 # Simulator instruction rate (inst/s) |
| host_op_rate 90296 # Simulator op (including micro ops) rate (op/s) |
| host_tick_rate 36352186 # Simulator tick rate (ticks/s) |
| host_mem_usage 236740 # Number of bytes of host memory used |
| host_seconds 2089.64 # Real time elapsed on the host |
| sim_insts 172333241 # Number of instructions simulated |
| sim_ops 188686723 # Number of ops (including micro ops) simulated |
| system.physmem.bytes_read::cpu.inst 132736 # Number of bytes read from this memory |
| system.physmem.bytes_read::cpu.data 112192 # Number of bytes read from this memory |
| system.physmem.bytes_read::total 244928 # Number of bytes read from this memory |
| system.physmem.bytes_inst_read::cpu.inst 132736 # Number of instructions bytes read from this memory |
| system.physmem.bytes_inst_read::total 132736 # Number of instructions bytes read from this memory |
| system.physmem.num_reads::cpu.inst 2074 # Number of read requests responded to by this memory |
| system.physmem.num_reads::cpu.data 1753 # Number of read requests responded to by this memory |
| system.physmem.num_reads::total 3827 # Number of read requests responded to by this memory |
| system.physmem.bw_read::cpu.inst 1747377 # Total read bandwidth from this memory (bytes/s) |
| system.physmem.bw_read::cpu.data 1476930 # Total read bandwidth from this memory (bytes/s) |
| system.physmem.bw_read::total 3224307 # Total read bandwidth from this memory (bytes/s) |
| system.physmem.bw_inst_read::cpu.inst 1747377 # Instruction read bandwidth from this memory (bytes/s) |
| system.physmem.bw_inst_read::total 1747377 # Instruction read bandwidth from this memory (bytes/s) |
| system.physmem.bw_total::cpu.inst 1747377 # Total bandwidth to/from this memory (bytes/s) |
| system.physmem.bw_total::cpu.data 1476930 # Total bandwidth to/from this memory (bytes/s) |
| system.physmem.bw_total::total 3224307 # Total bandwidth to/from this memory (bytes/s) |
| system.physmem.readReqs 3828 # Total number of read requests seen |
| system.physmem.writeReqs 0 # Total number of write requests seen |
| system.physmem.cpureqs 3829 # Reqs generatd by CPU via cache - shady |
| system.physmem.bytesRead 244928 # Total number of bytes read from memory |
| system.physmem.bytesWritten 0 # Total number of bytes written to memory |
| system.physmem.bytesConsumedRd 244928 # bytesRead derated as per pkt->getSize() |
| system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() |
| system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q |
| system.physmem.neitherReadNorWrite 1 # Reqs where no action is needed |
| system.physmem.perBankRdReqs::0 320 # Track reads on a per bank basis |
| system.physmem.perBankRdReqs::1 234 # Track reads on a per bank basis |
| system.physmem.perBankRdReqs::2 192 # Track reads on a per bank basis |
| system.physmem.perBankRdReqs::3 240 # Track reads on a per bank basis |
| system.physmem.perBankRdReqs::4 228 # Track reads on a per bank basis |
| system.physmem.perBankRdReqs::5 194 # Track reads on a per bank basis |
| system.physmem.perBankRdReqs::6 224 # Track reads on a per bank basis |
| system.physmem.perBankRdReqs::7 284 # Track reads on a per bank basis |
| system.physmem.perBankRdReqs::8 247 # Track reads on a per bank basis |
| system.physmem.perBankRdReqs::9 249 # Track reads on a per bank basis |
| system.physmem.perBankRdReqs::10 248 # Track reads on a per bank basis |
| system.physmem.perBankRdReqs::11 263 # Track reads on a per bank basis |
| system.physmem.perBankRdReqs::12 249 # Track reads on a per bank basis |
| system.physmem.perBankRdReqs::13 236 # Track reads on a per bank basis |
| system.physmem.perBankRdReqs::14 182 # Track reads on a per bank basis |
| system.physmem.perBankRdReqs::15 238 # Track reads on a per bank basis |
| system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis |
| system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis |
| system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis |
| system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis |
| system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis |
| system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis |
| system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis |
| system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis |
| system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis |
| system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis |
| system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis |
| system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis |
| system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis |
| system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis |
| system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis |
| system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis |
| system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry |
| system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| system.physmem.totGap 75962976500 # Total gap between requests |
| system.physmem.readPktSize::0 0 # Categorize read packet sizes |
| system.physmem.readPktSize::1 0 # Categorize read packet sizes |
| system.physmem.readPktSize::2 0 # Categorize read packet sizes |
| system.physmem.readPktSize::3 0 # Categorize read packet sizes |
| system.physmem.readPktSize::4 0 # Categorize read packet sizes |
| system.physmem.readPktSize::5 0 # Categorize read packet sizes |
| system.physmem.readPktSize::6 3828 # Categorize read packet sizes |
| system.physmem.readPktSize::7 0 # Categorize read packet sizes |
| system.physmem.readPktSize::8 0 # Categorize read packet sizes |
| system.physmem.writePktSize::0 0 # categorize write packet sizes |
| system.physmem.writePktSize::1 0 # categorize write packet sizes |
| system.physmem.writePktSize::2 0 # categorize write packet sizes |
| system.physmem.writePktSize::3 0 # categorize write packet sizes |
| system.physmem.writePktSize::4 0 # categorize write packet sizes |
| system.physmem.writePktSize::5 0 # categorize write packet sizes |
| system.physmem.writePktSize::6 0 # categorize write packet sizes |
| system.physmem.writePktSize::7 0 # categorize write packet sizes |
| system.physmem.writePktSize::8 0 # categorize write packet sizes |
| system.physmem.neitherpktsize::0 0 # categorize neither packet sizes |
| system.physmem.neitherpktsize::1 0 # categorize neither packet sizes |
| system.physmem.neitherpktsize::2 0 # categorize neither packet sizes |
| system.physmem.neitherpktsize::3 0 # categorize neither packet sizes |
| system.physmem.neitherpktsize::4 0 # categorize neither packet sizes |
| system.physmem.neitherpktsize::5 0 # categorize neither packet sizes |
| system.physmem.neitherpktsize::6 1 # categorize neither packet sizes |
| system.physmem.neitherpktsize::7 0 # categorize neither packet sizes |
| system.physmem.neitherpktsize::8 0 # categorize neither packet sizes |
| system.physmem.rdQLenPdf::0 2829 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::1 799 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::2 151 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::3 40 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::5 2 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see |
| system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see |
| system.physmem.totQLat 15909310 # Total cycles spent in queuing delays |
| system.physmem.totMemAccLat 90413310 # Sum of mem lat for all requests |
| system.physmem.totBusLat 15312000 # Total cycles spent in databus access |
| system.physmem.totBankLat 59192000 # Total cycles spent in bank access |
| system.physmem.avgQLat 4156.04 # Average queueing delay per request |
| system.physmem.avgBankLat 15462.90 # Average bank access latency per request |
| system.physmem.avgBusLat 4000.00 # Average bus latency per request |
| system.physmem.avgMemAccLat 23618.94 # Average memory access latency |
| system.physmem.avgRdBW 3.22 # Average achieved read bandwidth in MB/s |
| system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s |
| system.physmem.avgConsumedRdBW 3.22 # Average consumed read bandwidth in MB/s |
| system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s |
| system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s |
| system.physmem.busUtil 0.02 # Data bus utilization in percentage |
| system.physmem.avgRdQLen 0.00 # Average read queue length over time |
| system.physmem.avgWrQLen 0.00 # Average write queue length over time |
| system.physmem.readRowHits 3324 # Number of row buffer hits during reads |
| system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| system.physmem.readRowHitRate 86.83 # Row buffer hit rate for reads |
| system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| system.physmem.avgGap 19844037.75 # Average gap between requests |
| system.cpu.dtb.inst_hits 0 # ITB inst hits |
| system.cpu.dtb.inst_misses 0 # ITB inst misses |
| system.cpu.dtb.read_hits 0 # DTB read hits |
| system.cpu.dtb.read_misses 0 # DTB read misses |
| system.cpu.dtb.write_hits 0 # DTB write hits |
| system.cpu.dtb.write_misses 0 # DTB write misses |
| system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed |
| system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID |
| system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB |
| system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch |
| system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions |
| system.cpu.dtb.read_accesses 0 # DTB read accesses |
| system.cpu.dtb.write_accesses 0 # DTB write accesses |
| system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| system.cpu.dtb.hits 0 # DTB hits |
| system.cpu.dtb.misses 0 # DTB misses |
| system.cpu.dtb.accesses 0 # DTB accesses |
| system.cpu.itb.inst_hits 0 # ITB inst hits |
| system.cpu.itb.inst_misses 0 # ITB inst misses |
| system.cpu.itb.read_hits 0 # DTB read hits |
| system.cpu.itb.read_misses 0 # DTB read misses |
| system.cpu.itb.write_hits 0 # DTB write hits |
| system.cpu.itb.write_misses 0 # DTB write misses |
| system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed |
| system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID |
| system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB |
| system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch |
| system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions |
| system.cpu.itb.read_accesses 0 # DTB read accesses |
| system.cpu.itb.write_accesses 0 # DTB write accesses |
| system.cpu.itb.inst_accesses 0 # ITB inst accesses |
| system.cpu.itb.hits 0 # DTB hits |
| system.cpu.itb.misses 0 # DTB misses |
| system.cpu.itb.accesses 0 # DTB accesses |
| system.cpu.workload.num_syscalls 400 # Number of system calls |
| system.cpu.numCycles 151925993 # number of cpu cycles simulated |
| system.cpu.numWorkItemsStarted 0 # number of work items this cpu started |
| system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| system.cpu.BPredUnit.lookups 96812188 # Number of BP lookups |
| system.cpu.BPredUnit.condPredicted 76032236 # Number of conditional branches predicted |
| system.cpu.BPredUnit.condIncorrect 6553809 # Number of conditional branches incorrect |
| system.cpu.BPredUnit.BTBLookups 46446152 # Number of BTB lookups |
| system.cpu.BPredUnit.BTBHits 44209779 # Number of BTB hits |
| system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| system.cpu.BPredUnit.usedRAS 4476893 # Number of times the RAS was used to get a target. |
| system.cpu.BPredUnit.RASInCorrect 89558 # Number of incorrect RAS predictions. |
| system.cpu.fetch.icacheStallCycles 40612935 # Number of cycles fetch is stalled on an Icache miss |
| system.cpu.fetch.Insts 388214882 # Number of instructions fetch has processed |
| system.cpu.fetch.Branches 96812188 # Number of branches that fetch encountered |
| system.cpu.fetch.predictedBranches 48686672 # Number of branches that fetch has predicted taken |
| system.cpu.fetch.Cycles 82228989 # Number of cycles fetch has run and was not squashing or blocked |
| system.cpu.fetch.SquashCycles 28431080 # Number of cycles fetch has spent squashing |
| system.cpu.fetch.BlockedCycles 7111966 # Number of cycles fetch has spent blocked |
| system.cpu.fetch.MiscStallCycles 46 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs |
| system.cpu.fetch.PendingTrapStallCycles 9226 # Number of stall cycles due to pending traps |
| system.cpu.fetch.PendingQuiesceStallCycles 1 # Number of stall cycles due to pending quiesce instructions |
| system.cpu.fetch.IcacheWaitRetryStallCycles 57 # Number of stall cycles due to full MSHR |
| system.cpu.fetch.CacheLines 37654254 # Number of cache lines fetched |
| system.cpu.fetch.IcacheSquashes 1887415 # Number of outstanding Icache misses that were squashed |
| system.cpu.fetch.rateDist::samples 151824267 # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::mean 2.799061 # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::stdev 3.153208 # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::0 69765849 45.95% 45.95% # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::1 5500538 3.62% 49.57% # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::2 10700560 7.05% 56.62% # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::3 10437997 6.88% 63.50% # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::4 8786758 5.79% 69.29% # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::5 6834684 4.50% 73.79% # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::6 6296298 4.15% 77.93% # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::7 8361211 5.51% 83.44% # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::8 25140372 16.56% 100.00% # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist::total 151824267 # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.branchRate 0.637233 # Number of branch fetches per cycle |
| system.cpu.fetch.rate 2.555289 # Number of inst fetches per cycle |
| system.cpu.decode.IdleCycles 46639472 # Number of cycles decode is idle |
| system.cpu.decode.BlockedCycles 5819765 # Number of cycles decode is blocked |
| system.cpu.decode.RunCycles 76543741 # Number of cycles decode is running |
| system.cpu.decode.UnblockCycles 1113557 # Number of cycles decode is unblocking |
| system.cpu.decode.SquashCycles 21707732 # Number of cycles decode is squashing |
| system.cpu.decode.BranchResolved 14816289 # Number of times decode resolved a branch |
| system.cpu.decode.BranchMispred 162918 # Number of times decode detected a branch misprediction |
| system.cpu.decode.DecodedInsts 401266810 # Number of instructions handled by decode |
| system.cpu.decode.SquashedInsts 729123 # Number of squashed instructions handled by decode |
| system.cpu.rename.SquashCycles 21707732 # Number of cycles rename is squashing |
| system.cpu.rename.IdleCycles 52145776 # Number of cycles rename is idle |
| system.cpu.rename.BlockCycles 716376 # Number of cycles rename is blocking |
| system.cpu.rename.serializeStallCycles 699385 # count of cycles rename stalled for serializing inst |
| system.cpu.rename.RunCycles 72090483 # Number of cycles rename is running |
| system.cpu.rename.UnblockCycles 4464515 # Number of cycles rename is unblocking |
| system.cpu.rename.RenamedInsts 378976726 # Number of instructions processed by rename |
| system.cpu.rename.ROBFullEvents 19 # Number of times rename has blocked due to ROB full |
| system.cpu.rename.IQFullEvents 316631 # Number of times rename has blocked due to IQ full |
| system.cpu.rename.LSQFullEvents 3575950 # Number of times rename has blocked due to LSQ full |
| system.cpu.rename.FullRegisterEvents 15 # Number of times there has been no free registers |
| system.cpu.rename.RenamedOperands 642441440 # Number of destination operands rename has renamed |
| system.cpu.rename.RenameLookups 1614452334 # Number of register rename lookups that rename has made |
| system.cpu.rename.int_rename_lookups 1596874036 # Number of integer rename lookups |
| system.cpu.rename.fp_rename_lookups 17578298 # Number of floating rename lookups |
| system.cpu.rename.CommittedMaps 298092491 # Number of HB maps that are committed |
| system.cpu.rename.UndoneMaps 344348949 # Number of HB maps that are undone due to squashing |
| system.cpu.rename.serializingInsts 33473 # count of serializing insts renamed |
| system.cpu.rename.tempSerializingInsts 33471 # count of temporary serializing insts renamed |
| system.cpu.rename.skidInsts 12628265 # count of insts added to the skid buffer |
| system.cpu.memDep0.insertedLoads 43987484 # Number of loads inserted to the mem dependence unit. |
| system.cpu.memDep0.insertedStores 16888261 # Number of stores inserted to the mem dependence unit. |
| system.cpu.memDep0.conflictingLoads 5791013 # Number of conflicting loads. |
| system.cpu.memDep0.conflictingStores 3746055 # Number of conflicting stores. |
| system.cpu.iq.iqInstsAdded 334831031 # Number of instructions added to the IQ (excludes non-spec) |
| system.cpu.iq.iqNonSpecInstsAdded 55567 # Number of non-speculative instructions added to the IQ |
| system.cpu.iq.iqInstsIssued 252811108 # Number of instructions issued |
| system.cpu.iq.iqSquashedInstsIssued 890392 # Number of squashed instructions issued |
| system.cpu.iq.iqSquashedInstsExamined 144974552 # Number of squashed instructions iterated over during squash; mainly for profiling |
| system.cpu.iq.iqSquashedOperandsExamined 373956822 # Number of squashed operands that are examined and possibly removed from graph |
| system.cpu.iq.iqSquashedNonSpecRemoved 4307 # Number of squashed non-spec instructions that were removed |
| system.cpu.iq.issued_per_cycle::samples 151824267 # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::mean 1.665156 # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::stdev 1.759693 # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::0 58367016 38.44% 38.44% # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::1 23007793 15.15% 53.60% # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::2 25146514 16.56% 70.16% # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::3 20482198 13.49% 83.65% # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::4 12879503 8.48% 92.13% # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::5 6581643 4.34% 96.47% # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::6 4062886 2.68% 99.15% # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::7 1113562 0.73% 99.88% # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::8 183152 0.12% 100.00% # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| system.cpu.iq.issued_per_cycle::total 151824267 # Number of insts issued each cycle |
| system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| system.cpu.iq.fu_full::IntAlu 966665 37.55% 37.55% # attempts to use FU when none available |
| system.cpu.iq.fu_full::IntMult 5596 0.22% 37.77% # attempts to use FU when none available |
| system.cpu.iq.fu_full::IntDiv 0 0.00% 37.77% # attempts to use FU when none available |
| system.cpu.iq.fu_full::FloatAdd 0 0.00% 37.77% # attempts to use FU when none available |
| system.cpu.iq.fu_full::FloatCmp 0 0.00% 37.77% # attempts to use FU when none available |
| system.cpu.iq.fu_full::FloatCvt 0 0.00% 37.77% # attempts to use FU when none available |
| system.cpu.iq.fu_full::FloatMult 0 0.00% 37.77% # attempts to use FU when none available |
| system.cpu.iq.fu_full::FloatDiv 0 0.00% 37.77% # attempts to use FU when none available |
| system.cpu.iq.fu_full::FloatSqrt 0 0.00% 37.77% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdAdd 0 0.00% 37.77% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 37.77% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdAlu 0 0.00% 37.77% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdCmp 0 0.00% 37.77% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdCvt 0 0.00% 37.77% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdMisc 0 0.00% 37.77% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdMult 0 0.00% 37.77% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 37.77% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdShift 0 0.00% 37.77% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 37.77% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdSqrt 0 0.00% 37.77% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdFloatAdd 94 0.00% 37.77% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 37.77% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 37.77% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 37.77% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 37.77% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdFloatMisc 27 0.00% 37.78% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 37.78% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 37.78% # attempts to use FU when none available |
| system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 37.78% # attempts to use FU when none available |
| system.cpu.iq.fu_full::MemRead 1198357 46.55% 84.33% # attempts to use FU when none available |
| system.cpu.iq.fu_full::MemWrite 403391 15.67% 100.00% # attempts to use FU when none available |
| system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available |
| system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available |
| system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| system.cpu.iq.FU_type_0::IntAlu 197328873 78.05% 78.05% # Type of FU issued |
| system.cpu.iq.FU_type_0::IntMult 995382 0.39% 78.45% # Type of FU issued |
| system.cpu.iq.FU_type_0::IntDiv 0 0.00% 78.45% # Type of FU issued |
| system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 78.45% # Type of FU issued |
| system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 78.45% # Type of FU issued |
| system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 78.45% # Type of FU issued |
| system.cpu.iq.FU_type_0::FloatMult 0 0.00% 78.45% # Type of FU issued |
| system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 78.45% # Type of FU issued |
| system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 78.45% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 78.45% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 78.45% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 78.45% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 78.45% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 78.45% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 78.45% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdMult 0 0.00% 78.45% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 78.45% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdShift 0 0.00% 78.45% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 78.45% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 78.45% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdFloatAdd 33194 0.01% 78.46% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 78.46% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdFloatCmp 163810 0.06% 78.53% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdFloatCvt 255234 0.10% 78.63% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdFloatDiv 76440 0.03% 78.66% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdFloatMisc 467356 0.18% 78.84% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdFloatMult 206283 0.08% 78.92% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdFloatMultAcc 71857 0.03% 78.95% # Type of FU issued |
| system.cpu.iq.FU_type_0::SimdFloatSqrt 320 0.00% 78.95% # Type of FU issued |
| system.cpu.iq.FU_type_0::MemRead 39021114 15.43% 94.39% # Type of FU issued |
| system.cpu.iq.FU_type_0::MemWrite 14191245 5.61% 100.00% # Type of FU issued |
| system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued |
| system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| system.cpu.iq.FU_type_0::total 252811108 # Type of FU issued |
| system.cpu.iq.rate 1.664041 # Inst issue rate |
| system.cpu.iq.fu_busy_cnt 2574130 # FU busy when requested |
| system.cpu.iq.fu_busy_rate 0.010182 # FU busy rate (busy events/executed inst) |
| system.cpu.iq.int_inst_queue_reads 657138452 # Number of integer instruction queue reads |
| system.cpu.iq.int_inst_queue_writes 477635375 # Number of integer instruction queue writes |
| system.cpu.iq.int_inst_queue_wakeup_accesses 240576408 # Number of integer instruction queue wakeup accesses |
| system.cpu.iq.fp_inst_queue_reads 3772553 # Number of floating instruction queue reads |
| system.cpu.iq.fp_inst_queue_writes 2244745 # Number of floating instruction queue writes |
| system.cpu.iq.fp_inst_queue_wakeup_accesses 1851453 # Number of floating instruction queue wakeup accesses |
| system.cpu.iq.int_alu_accesses 253490963 # Number of integer alu accesses |
| system.cpu.iq.fp_alu_accesses 1894275 # Number of floating point alu accesses |
| system.cpu.iew.lsq.thread0.forwLoads 2028433 # Number of loads that had data forwarded from stores |
| system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| system.cpu.iew.lsq.thread0.squashedLoads 14131956 # Number of loads squashed |
| system.cpu.iew.lsq.thread0.ignoredResponses 16953 # Number of memory responses ignored because the instruction is squashed |
| system.cpu.iew.lsq.thread0.memOrderViolation 19730 # Number of memory ordering violations |
| system.cpu.iew.lsq.thread0.squashedStores 4237583 # Number of stores squashed |
| system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address |
| system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| system.cpu.iew.lsq.thread0.rescheduledLoads 4 # Number of loads that were rescheduled |
| system.cpu.iew.lsq.thread0.cacheBlocked 84 # Number of times an access to memory failed due to the cache being blocked |
| system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| system.cpu.iew.iewSquashCycles 21707732 # Number of cycles IEW is squashing |
| system.cpu.iew.iewBlockCycles 16237 # Number of cycles IEW is blocking |
| system.cpu.iew.iewUnblockCycles 835 # Number of cycles IEW is unblocking |
| system.cpu.iew.iewDispatchedInsts 334904365 # Number of instructions dispatched to IQ |
| system.cpu.iew.iewDispSquashedInsts 834808 # Number of squashed instructions skipped by dispatch |
| system.cpu.iew.iewDispLoadInsts 43987484 # Number of dispatched load instructions |
| system.cpu.iew.iewDispStoreInsts 16888261 # Number of dispatched store instructions |
| system.cpu.iew.iewDispNonSpecInsts 33011 # Number of dispatched non-speculative instructions |
| system.cpu.iew.iewIQFullEvents 182 # Number of times the IQ has become full, causing a stall |
| system.cpu.iew.iewLSQFullEvents 269 # Number of times the LSQ has become full, causing a stall |
| system.cpu.iew.memOrderViolationEvents 19730 # Number of memory order violations |
| system.cpu.iew.predictedTakenIncorrect 4101344 # Number of branches that were predicted taken incorrectly |
| system.cpu.iew.predictedNotTakenIncorrect 3925912 # Number of branches that were predicted not taken incorrectly |
| system.cpu.iew.branchMispredicts 8027256 # Number of branch mispredicts detected at execute |
| system.cpu.iew.iewExecutedInsts 245818022 # Number of executed instructions |
| system.cpu.iew.iewExecLoadInsts 37400003 # Number of load instructions executed |
| system.cpu.iew.iewExecSquashedInsts 6993086 # Number of squashed instructions skipped in execute |
| system.cpu.iew.exec_swp 0 # number of swp insts executed |
| system.cpu.iew.exec_nop 17767 # number of nop insts executed |
| system.cpu.iew.exec_refs 51208402 # number of memory reference insts executed |
| system.cpu.iew.exec_branches 54033495 # Number of branches executed |
| system.cpu.iew.exec_stores 13808399 # Number of stores executed |
| system.cpu.iew.exec_rate 1.618012 # Inst execution rate |
| system.cpu.iew.wb_sent 243559168 # cumulative count of insts sent to commit |
| system.cpu.iew.wb_count 242427861 # cumulative count of insts written-back |
| system.cpu.iew.wb_producers 150062323 # num instructions producing a value |
| system.cpu.iew.wb_consumers 269174598 # num instructions consuming a value |
| system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| system.cpu.iew.wb_rate 1.595697 # insts written-back per cycle |
| system.cpu.iew.wb_fanout 0.557491 # average fanout of values written-back |
| system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| system.cpu.commit.commitSquashedInsts 146203238 # The number of squashed insts skipped by commit |
| system.cpu.commit.commitNonSpecStalls 51260 # The number of times commit has been forced to stall to communicate backwards |
| system.cpu.commit.branchMispredicts 6400494 # The number of times a branch was mispredicted |
| system.cpu.commit.committed_per_cycle::samples 130116536 # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::mean 1.450247 # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::stdev 2.162155 # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::0 59888298 46.03% 46.03% # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::1 32076129 24.65% 70.68% # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::2 13982572 10.75% 81.42% # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::3 7654340 5.88% 87.31% # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::4 4412681 3.39% 90.70% # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::5 1335897 1.03% 91.73% # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::6 1741211 1.34% 93.06% # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::7 1283921 0.99% 94.05% # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::8 7741487 5.95% 100.00% # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| system.cpu.commit.committed_per_cycle::total 130116536 # Number of insts commited each cycle |
| system.cpu.commit.committedInsts 172347629 # Number of instructions committed |
| system.cpu.commit.committedOps 188701111 # Number of ops (including micro ops) committed |
| system.cpu.commit.swp_count 0 # Number of s/w prefetches committed |
| system.cpu.commit.refs 42506206 # Number of memory references committed |
| system.cpu.commit.loads 29855528 # Number of loads committed |
| system.cpu.commit.membars 22408 # Number of memory barriers committed |
| system.cpu.commit.branches 40306355 # Number of branches committed |
| system.cpu.commit.fp_insts 1752310 # Number of committed floating point instructions. |
| system.cpu.commit.int_insts 150130393 # Number of committed integer instructions. |
| system.cpu.commit.function_calls 1848934 # Number of function calls committed. |
| system.cpu.commit.bw_lim_events 7741487 # number cycles where commit BW limit reached |
| system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| system.cpu.rob.rob_reads 457274197 # The number of ROB reads |
| system.cpu.rob.rob_writes 691635591 # The number of ROB writes |
| system.cpu.timesIdled 2582 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| system.cpu.idleCycles 101726 # Total number of cycles that the CPU has spent unscheduled due to idling |
| system.cpu.committedInsts 172333241 # Number of Instructions Simulated |
| system.cpu.committedOps 188686723 # Number of Ops (including micro ops) Simulated |
| system.cpu.committedInsts_total 172333241 # Number of Instructions Simulated |
| system.cpu.cpi 0.881583 # CPI: Cycles Per Instruction |
| system.cpu.cpi_total 0.881583 # CPI: Total CPI of All Threads |
| system.cpu.ipc 1.134324 # IPC: Instructions Per Cycle |
| system.cpu.ipc_total 1.134324 # IPC: Total IPC of All Threads |
| system.cpu.int_regfile_reads 1091906245 # number of integer regfile reads |
| system.cpu.int_regfile_writes 388600616 # number of integer regfile writes |
| system.cpu.fp_regfile_reads 2911397 # number of floating regfile reads |
| system.cpu.fp_regfile_writes 2511024 # number of floating regfile writes |
| system.cpu.misc_regfile_reads 474438629 # number of misc regfile reads |
| system.cpu.misc_regfile_writes 832124 # number of misc regfile writes |
| system.cpu.icache.replacements 2644 # number of replacements |
| system.cpu.icache.tagsinuse 1367.286315 # Cycle average of tags in use |
| system.cpu.icache.total_refs 37648759 # Total number of references to valid blocks. |
| system.cpu.icache.sampled_refs 4386 # Sample count of references to valid blocks. |
| system.cpu.icache.avg_refs 8583.848381 # Average number of references to valid blocks. |
| system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| system.cpu.icache.occ_blocks::cpu.inst 1367.286315 # Average occupied blocks per requestor |
| system.cpu.icache.occ_percent::cpu.inst 0.667620 # Average percentage of cache occupancy |
| system.cpu.icache.occ_percent::total 0.667620 # Average percentage of cache occupancy |
| system.cpu.icache.ReadReq_hits::cpu.inst 37648759 # number of ReadReq hits |
| system.cpu.icache.ReadReq_hits::total 37648759 # number of ReadReq hits |
| system.cpu.icache.demand_hits::cpu.inst 37648759 # number of demand (read+write) hits |
| system.cpu.icache.demand_hits::total 37648759 # number of demand (read+write) hits |
| system.cpu.icache.overall_hits::cpu.inst 37648759 # number of overall hits |
| system.cpu.icache.overall_hits::total 37648759 # number of overall hits |
| system.cpu.icache.ReadReq_misses::cpu.inst 5495 # number of ReadReq misses |
| system.cpu.icache.ReadReq_misses::total 5495 # number of ReadReq misses |
| system.cpu.icache.demand_misses::cpu.inst 5495 # number of demand (read+write) misses |
| system.cpu.icache.demand_misses::total 5495 # number of demand (read+write) misses |
| system.cpu.icache.overall_misses::cpu.inst 5495 # number of overall misses |
| system.cpu.icache.overall_misses::total 5495 # number of overall misses |
| system.cpu.icache.ReadReq_miss_latency::cpu.inst 164010000 # number of ReadReq miss cycles |
| system.cpu.icache.ReadReq_miss_latency::total 164010000 # number of ReadReq miss cycles |
| system.cpu.icache.demand_miss_latency::cpu.inst 164010000 # number of demand (read+write) miss cycles |
| system.cpu.icache.demand_miss_latency::total 164010000 # number of demand (read+write) miss cycles |
| system.cpu.icache.overall_miss_latency::cpu.inst 164010000 # number of overall miss cycles |
| system.cpu.icache.overall_miss_latency::total 164010000 # number of overall miss cycles |
| system.cpu.icache.ReadReq_accesses::cpu.inst 37654254 # number of ReadReq accesses(hits+misses) |
| system.cpu.icache.ReadReq_accesses::total 37654254 # number of ReadReq accesses(hits+misses) |
| system.cpu.icache.demand_accesses::cpu.inst 37654254 # number of demand (read+write) accesses |
| system.cpu.icache.demand_accesses::total 37654254 # number of demand (read+write) accesses |
| system.cpu.icache.overall_accesses::cpu.inst 37654254 # number of overall (read+write) accesses |
| system.cpu.icache.overall_accesses::total 37654254 # number of overall (read+write) accesses |
| system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000146 # miss rate for ReadReq accesses |
| system.cpu.icache.ReadReq_miss_rate::total 0.000146 # miss rate for ReadReq accesses |
| system.cpu.icache.demand_miss_rate::cpu.inst 0.000146 # miss rate for demand accesses |
| system.cpu.icache.demand_miss_rate::total 0.000146 # miss rate for demand accesses |
| system.cpu.icache.overall_miss_rate::cpu.inst 0.000146 # miss rate for overall accesses |
| system.cpu.icache.overall_miss_rate::total 0.000146 # miss rate for overall accesses |
| system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 29847.133758 # average ReadReq miss latency |
| system.cpu.icache.ReadReq_avg_miss_latency::total 29847.133758 # average ReadReq miss latency |
| system.cpu.icache.demand_avg_miss_latency::cpu.inst 29847.133758 # average overall miss latency |
| system.cpu.icache.demand_avg_miss_latency::total 29847.133758 # average overall miss latency |
| system.cpu.icache.overall_avg_miss_latency::cpu.inst 29847.133758 # average overall miss latency |
| system.cpu.icache.overall_avg_miss_latency::total 29847.133758 # average overall miss latency |
| system.cpu.icache.blocked_cycles::no_mshrs 669 # number of cycles access was blocked |
| system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| system.cpu.icache.blocked::no_mshrs 18 # number of cycles access was blocked |
| system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| system.cpu.icache.avg_blocked_cycles::no_mshrs 37.166667 # average number of cycles each access was blocked |
| system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| system.cpu.icache.fast_writes 0 # number of fast writes performed |
| system.cpu.icache.cache_copies 0 # number of cache copies performed |
| system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1106 # number of ReadReq MSHR hits |
| system.cpu.icache.ReadReq_mshr_hits::total 1106 # number of ReadReq MSHR hits |
| system.cpu.icache.demand_mshr_hits::cpu.inst 1106 # number of demand (read+write) MSHR hits |
| system.cpu.icache.demand_mshr_hits::total 1106 # number of demand (read+write) MSHR hits |
| system.cpu.icache.overall_mshr_hits::cpu.inst 1106 # number of overall MSHR hits |
| system.cpu.icache.overall_mshr_hits::total 1106 # number of overall MSHR hits |
| system.cpu.icache.ReadReq_mshr_misses::cpu.inst 4389 # number of ReadReq MSHR misses |
| system.cpu.icache.ReadReq_mshr_misses::total 4389 # number of ReadReq MSHR misses |
| system.cpu.icache.demand_mshr_misses::cpu.inst 4389 # number of demand (read+write) MSHR misses |
| system.cpu.icache.demand_mshr_misses::total 4389 # number of demand (read+write) MSHR misses |
| system.cpu.icache.overall_mshr_misses::cpu.inst 4389 # number of overall MSHR misses |
| system.cpu.icache.overall_mshr_misses::total 4389 # number of overall MSHR misses |
| system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 126227500 # number of ReadReq MSHR miss cycles |
| system.cpu.icache.ReadReq_mshr_miss_latency::total 126227500 # number of ReadReq MSHR miss cycles |
| system.cpu.icache.demand_mshr_miss_latency::cpu.inst 126227500 # number of demand (read+write) MSHR miss cycles |
| system.cpu.icache.demand_mshr_miss_latency::total 126227500 # number of demand (read+write) MSHR miss cycles |
| system.cpu.icache.overall_mshr_miss_latency::cpu.inst 126227500 # number of overall MSHR miss cycles |
| system.cpu.icache.overall_mshr_miss_latency::total 126227500 # number of overall MSHR miss cycles |
| system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for ReadReq accesses |
| system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000117 # mshr miss rate for ReadReq accesses |
| system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for demand accesses |
| system.cpu.icache.demand_mshr_miss_rate::total 0.000117 # mshr miss rate for demand accesses |
| system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000117 # mshr miss rate for overall accesses |
| system.cpu.icache.overall_mshr_miss_rate::total 0.000117 # mshr miss rate for overall accesses |
| system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28759.968102 # average ReadReq mshr miss latency |
| system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28759.968102 # average ReadReq mshr miss latency |
| system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28759.968102 # average overall mshr miss latency |
| system.cpu.icache.demand_avg_mshr_miss_latency::total 28759.968102 # average overall mshr miss latency |
| system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28759.968102 # average overall mshr miss latency |
| system.cpu.icache.overall_avg_mshr_miss_latency::total 28759.968102 # average overall mshr miss latency |
| system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| system.cpu.dcache.replacements 57 # number of replacements |
| system.cpu.dcache.tagsinuse 1416.459985 # Cycle average of tags in use |
| system.cpu.dcache.total_refs 47307506 # Total number of references to valid blocks. |
| system.cpu.dcache.sampled_refs 1862 # Sample count of references to valid blocks. |
| system.cpu.dcache.avg_refs 25406.823845 # Average number of references to valid blocks. |
| system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| system.cpu.dcache.occ_blocks::cpu.data 1416.459985 # Average occupied blocks per requestor |
| system.cpu.dcache.occ_percent::cpu.data 0.345815 # Average percentage of cache occupancy |
| system.cpu.dcache.occ_percent::total 0.345815 # Average percentage of cache occupancy |
| system.cpu.dcache.ReadReq_hits::cpu.data 34892236 # number of ReadReq hits |
| system.cpu.dcache.ReadReq_hits::total 34892236 # number of ReadReq hits |
| system.cpu.dcache.WriteReq_hits::cpu.data 12356557 # number of WriteReq hits |
| system.cpu.dcache.WriteReq_hits::total 12356557 # number of WriteReq hits |
| system.cpu.dcache.LoadLockedReq_hits::cpu.data 30260 # number of LoadLockedReq hits |
| system.cpu.dcache.LoadLockedReq_hits::total 30260 # number of LoadLockedReq hits |
| system.cpu.dcache.StoreCondReq_hits::cpu.data 28451 # number of StoreCondReq hits |
| system.cpu.dcache.StoreCondReq_hits::total 28451 # number of StoreCondReq hits |
| system.cpu.dcache.demand_hits::cpu.data 47248793 # number of demand (read+write) hits |
| system.cpu.dcache.demand_hits::total 47248793 # number of demand (read+write) hits |
| system.cpu.dcache.overall_hits::cpu.data 47248793 # number of overall hits |
| system.cpu.dcache.overall_hits::total 47248793 # number of overall hits |
| system.cpu.dcache.ReadReq_misses::cpu.data 1972 # number of ReadReq misses |
| system.cpu.dcache.ReadReq_misses::total 1972 # number of ReadReq misses |
| system.cpu.dcache.WriteReq_misses::cpu.data 7730 # number of WriteReq misses |
| system.cpu.dcache.WriteReq_misses::total 7730 # number of WriteReq misses |
| system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 # number of LoadLockedReq misses |
| system.cpu.dcache.LoadLockedReq_misses::total 2 # number of LoadLockedReq misses |
| system.cpu.dcache.demand_misses::cpu.data 9702 # number of demand (read+write) misses |
| system.cpu.dcache.demand_misses::total 9702 # number of demand (read+write) misses |
| system.cpu.dcache.overall_misses::cpu.data 9702 # number of overall misses |
| system.cpu.dcache.overall_misses::total 9702 # number of overall misses |
| system.cpu.dcache.ReadReq_miss_latency::cpu.data 89685500 # number of ReadReq miss cycles |
| system.cpu.dcache.ReadReq_miss_latency::total 89685500 # number of ReadReq miss cycles |
| system.cpu.dcache.WriteReq_miss_latency::cpu.data 298721497 # number of WriteReq miss cycles |
| system.cpu.dcache.WriteReq_miss_latency::total 298721497 # number of WriteReq miss cycles |
| system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 102000 # number of LoadLockedReq miss cycles |
| system.cpu.dcache.LoadLockedReq_miss_latency::total 102000 # number of LoadLockedReq miss cycles |
| system.cpu.dcache.demand_miss_latency::cpu.data 388406997 # number of demand (read+write) miss cycles |
| system.cpu.dcache.demand_miss_latency::total 388406997 # number of demand (read+write) miss cycles |
| system.cpu.dcache.overall_miss_latency::cpu.data 388406997 # number of overall miss cycles |
| system.cpu.dcache.overall_miss_latency::total 388406997 # number of overall miss cycles |
| system.cpu.dcache.ReadReq_accesses::cpu.data 34894208 # number of ReadReq accesses(hits+misses) |
| system.cpu.dcache.ReadReq_accesses::total 34894208 # number of ReadReq accesses(hits+misses) |
| system.cpu.dcache.WriteReq_accesses::cpu.data 12364287 # number of WriteReq accesses(hits+misses) |
| system.cpu.dcache.WriteReq_accesses::total 12364287 # number of WriteReq accesses(hits+misses) |
| system.cpu.dcache.LoadLockedReq_accesses::cpu.data 30262 # number of LoadLockedReq accesses(hits+misses) |
| system.cpu.dcache.LoadLockedReq_accesses::total 30262 # number of LoadLockedReq accesses(hits+misses) |
| system.cpu.dcache.StoreCondReq_accesses::cpu.data 28451 # number of StoreCondReq accesses(hits+misses) |
| system.cpu.dcache.StoreCondReq_accesses::total 28451 # number of StoreCondReq accesses(hits+misses) |
| system.cpu.dcache.demand_accesses::cpu.data 47258495 # number of demand (read+write) accesses |
| system.cpu.dcache.demand_accesses::total 47258495 # number of demand (read+write) accesses |
| system.cpu.dcache.overall_accesses::cpu.data 47258495 # number of overall (read+write) accesses |
| system.cpu.dcache.overall_accesses::total 47258495 # number of overall (read+write) accesses |
| system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.000057 # miss rate for ReadReq accesses |
| system.cpu.dcache.ReadReq_miss_rate::total 0.000057 # miss rate for ReadReq accesses |
| system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.000625 # miss rate for WriteReq accesses |
| system.cpu.dcache.WriteReq_miss_rate::total 0.000625 # miss rate for WriteReq accesses |
| system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.000066 # miss rate for LoadLockedReq accesses |
| system.cpu.dcache.LoadLockedReq_miss_rate::total 0.000066 # miss rate for LoadLockedReq accesses |
| system.cpu.dcache.demand_miss_rate::cpu.data 0.000205 # miss rate for demand accesses |
| system.cpu.dcache.demand_miss_rate::total 0.000205 # miss rate for demand accesses |
| system.cpu.dcache.overall_miss_rate::cpu.data 0.000205 # miss rate for overall accesses |
| system.cpu.dcache.overall_miss_rate::total 0.000205 # miss rate for overall accesses |
| system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 45479.462475 # average ReadReq miss latency |
| system.cpu.dcache.ReadReq_avg_miss_latency::total 45479.462475 # average ReadReq miss latency |
| system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 38644.436869 # average WriteReq miss latency |
| system.cpu.dcache.WriteReq_avg_miss_latency::total 38644.436869 # average WriteReq miss latency |
| system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 51000 # average LoadLockedReq miss latency |
| system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 51000 # average LoadLockedReq miss latency |
| system.cpu.dcache.demand_avg_miss_latency::cpu.data 40033.704082 # average overall miss latency |
| system.cpu.dcache.demand_avg_miss_latency::total 40033.704082 # average overall miss latency |
| system.cpu.dcache.overall_avg_miss_latency::cpu.data 40033.704082 # average overall miss latency |
| system.cpu.dcache.overall_avg_miss_latency::total 40033.704082 # average overall miss latency |
| system.cpu.dcache.blocked_cycles::no_mshrs 433 # number of cycles access was blocked |
| system.cpu.dcache.blocked_cycles::no_targets 45 # number of cycles access was blocked |
| system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked |
| system.cpu.dcache.blocked::no_targets 2 # number of cycles access was blocked |
| system.cpu.dcache.avg_blocked_cycles::no_mshrs 39.363636 # average number of cycles each access was blocked |
| system.cpu.dcache.avg_blocked_cycles::no_targets 22.500000 # average number of cycles each access was blocked |
| system.cpu.dcache.fast_writes 0 # number of fast writes performed |
| system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| system.cpu.dcache.writebacks::writebacks 18 # number of writebacks |
| system.cpu.dcache.writebacks::total 18 # number of writebacks |
| system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1197 # number of ReadReq MSHR hits |
| system.cpu.dcache.ReadReq_mshr_hits::total 1197 # number of ReadReq MSHR hits |
| system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6641 # number of WriteReq MSHR hits |
| system.cpu.dcache.WriteReq_mshr_hits::total 6641 # number of WriteReq MSHR hits |
| system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 # number of LoadLockedReq MSHR hits |
| system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 # number of LoadLockedReq MSHR hits |
| system.cpu.dcache.demand_mshr_hits::cpu.data 7838 # number of demand (read+write) MSHR hits |
| system.cpu.dcache.demand_mshr_hits::total 7838 # number of demand (read+write) MSHR hits |
| system.cpu.dcache.overall_mshr_hits::cpu.data 7838 # number of overall MSHR hits |
| system.cpu.dcache.overall_mshr_hits::total 7838 # number of overall MSHR hits |
| system.cpu.dcache.ReadReq_mshr_misses::cpu.data 775 # number of ReadReq MSHR misses |
| system.cpu.dcache.ReadReq_mshr_misses::total 775 # number of ReadReq MSHR misses |
| system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1089 # number of WriteReq MSHR misses |
| system.cpu.dcache.WriteReq_mshr_misses::total 1089 # number of WriteReq MSHR misses |
| system.cpu.dcache.demand_mshr_misses::cpu.data 1864 # number of demand (read+write) MSHR misses |
| system.cpu.dcache.demand_mshr_misses::total 1864 # number of demand (read+write) MSHR misses |
| system.cpu.dcache.overall_mshr_misses::cpu.data 1864 # number of overall MSHR misses |
| system.cpu.dcache.overall_mshr_misses::total 1864 # number of overall MSHR misses |
| system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 38083000 # number of ReadReq MSHR miss cycles |
| system.cpu.dcache.ReadReq_mshr_miss_latency::total 38083000 # number of ReadReq MSHR miss cycles |
| system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 48635999 # number of WriteReq MSHR miss cycles |
| system.cpu.dcache.WriteReq_mshr_miss_latency::total 48635999 # number of WriteReq MSHR miss cycles |
| system.cpu.dcache.demand_mshr_miss_latency::cpu.data 86718999 # number of demand (read+write) MSHR miss cycles |
| system.cpu.dcache.demand_mshr_miss_latency::total 86718999 # number of demand (read+write) MSHR miss cycles |
| system.cpu.dcache.overall_mshr_miss_latency::cpu.data 86718999 # number of overall MSHR miss cycles |
| system.cpu.dcache.overall_mshr_miss_latency::total 86718999 # number of overall MSHR miss cycles |
| system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000022 # mshr miss rate for ReadReq accesses |
| system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000022 # mshr miss rate for ReadReq accesses |
| system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000088 # mshr miss rate for WriteReq accesses |
| system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000088 # mshr miss rate for WriteReq accesses |
| system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000039 # mshr miss rate for demand accesses |
| system.cpu.dcache.demand_mshr_miss_rate::total 0.000039 # mshr miss rate for demand accesses |
| system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000039 # mshr miss rate for overall accesses |
| system.cpu.dcache.overall_mshr_miss_rate::total 0.000039 # mshr miss rate for overall accesses |
| system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 49139.354839 # average ReadReq mshr miss latency |
| system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 49139.354839 # average ReadReq mshr miss latency |
| system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 44661.156107 # average WriteReq mshr miss latency |
| system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 44661.156107 # average WriteReq mshr miss latency |
| system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 46523.068133 # average overall mshr miss latency |
| system.cpu.dcache.demand_avg_mshr_miss_latency::total 46523.068133 # average overall mshr miss latency |
| system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 46523.068133 # average overall mshr miss latency |
| system.cpu.dcache.overall_avg_mshr_miss_latency::total 46523.068133 # average overall mshr miss latency |
| system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| system.cpu.l2cache.replacements 0 # number of replacements |
| system.cpu.l2cache.tagsinuse 1988.724621 # Cycle average of tags in use |
| system.cpu.l2cache.total_refs 2398 # Total number of references to valid blocks. |
| system.cpu.l2cache.sampled_refs 2755 # Sample count of references to valid blocks. |
| system.cpu.l2cache.avg_refs 0.870417 # Average number of references to valid blocks. |
| system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| system.cpu.l2cache.occ_blocks::writebacks 3.999610 # Average occupied blocks per requestor |
| system.cpu.l2cache.occ_blocks::cpu.inst 1449.117125 # Average occupied blocks per requestor |
| system.cpu.l2cache.occ_blocks::cpu.data 535.607885 # Average occupied blocks per requestor |
| system.cpu.l2cache.occ_percent::writebacks 0.000122 # Average percentage of cache occupancy |
| system.cpu.l2cache.occ_percent::cpu.inst 0.044224 # Average percentage of cache occupancy |
| system.cpu.l2cache.occ_percent::cpu.data 0.016345 # Average percentage of cache occupancy |
| system.cpu.l2cache.occ_percent::total 0.060691 # Average percentage of cache occupancy |
| system.cpu.l2cache.ReadReq_hits::cpu.inst 2308 # number of ReadReq hits |
| system.cpu.l2cache.ReadReq_hits::cpu.data 88 # number of ReadReq hits |
| system.cpu.l2cache.ReadReq_hits::total 2396 # number of ReadReq hits |
| system.cpu.l2cache.Writeback_hits::writebacks 18 # number of Writeback hits |
| system.cpu.l2cache.Writeback_hits::total 18 # number of Writeback hits |
| system.cpu.l2cache.UpgradeReq_hits::cpu.data 1 # number of UpgradeReq hits |
| system.cpu.l2cache.UpgradeReq_hits::total 1 # number of UpgradeReq hits |
| system.cpu.l2cache.ReadExReq_hits::cpu.data 9 # number of ReadExReq hits |
| system.cpu.l2cache.ReadExReq_hits::total 9 # number of ReadExReq hits |
| system.cpu.l2cache.demand_hits::cpu.inst 2308 # number of demand (read+write) hits |
| system.cpu.l2cache.demand_hits::cpu.data 97 # number of demand (read+write) hits |
| system.cpu.l2cache.demand_hits::total 2405 # number of demand (read+write) hits |
| system.cpu.l2cache.overall_hits::cpu.inst 2308 # number of overall hits |
| system.cpu.l2cache.overall_hits::cpu.data 97 # number of overall hits |
| system.cpu.l2cache.overall_hits::total 2405 # number of overall hits |
| system.cpu.l2cache.ReadReq_misses::cpu.inst 2079 # number of ReadReq misses |
| system.cpu.l2cache.ReadReq_misses::cpu.data 685 # number of ReadReq misses |
| system.cpu.l2cache.ReadReq_misses::total 2764 # number of ReadReq misses |
| system.cpu.l2cache.UpgradeReq_misses::cpu.data 1 # number of UpgradeReq misses |
| system.cpu.l2cache.UpgradeReq_misses::total 1 # number of UpgradeReq misses |
| system.cpu.l2cache.ReadExReq_misses::cpu.data 1080 # number of ReadExReq misses |
| system.cpu.l2cache.ReadExReq_misses::total 1080 # number of ReadExReq misses |
| system.cpu.l2cache.demand_misses::cpu.inst 2079 # number of demand (read+write) misses |
| system.cpu.l2cache.demand_misses::cpu.data 1765 # number of demand (read+write) misses |
| system.cpu.l2cache.demand_misses::total 3844 # number of demand (read+write) misses |
| system.cpu.l2cache.overall_misses::cpu.inst 2079 # number of overall misses |
| system.cpu.l2cache.overall_misses::cpu.data 1765 # number of overall misses |
| system.cpu.l2cache.overall_misses::total 3844 # number of overall misses |
| system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 98742500 # number of ReadReq miss cycles |
| system.cpu.l2cache.ReadReq_miss_latency::cpu.data 36322000 # number of ReadReq miss cycles |
| system.cpu.l2cache.ReadReq_miss_latency::total 135064500 # number of ReadReq miss cycles |
| system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 47502500 # number of ReadExReq miss cycles |
| system.cpu.l2cache.ReadExReq_miss_latency::total 47502500 # number of ReadExReq miss cycles |
| system.cpu.l2cache.demand_miss_latency::cpu.inst 98742500 # number of demand (read+write) miss cycles |
| system.cpu.l2cache.demand_miss_latency::cpu.data 83824500 # number of demand (read+write) miss cycles |
| system.cpu.l2cache.demand_miss_latency::total 182567000 # number of demand (read+write) miss cycles |
| system.cpu.l2cache.overall_miss_latency::cpu.inst 98742500 # number of overall miss cycles |
| system.cpu.l2cache.overall_miss_latency::cpu.data 83824500 # number of overall miss cycles |
| system.cpu.l2cache.overall_miss_latency::total 182567000 # number of overall miss cycles |
| system.cpu.l2cache.ReadReq_accesses::cpu.inst 4387 # number of ReadReq accesses(hits+misses) |
| system.cpu.l2cache.ReadReq_accesses::cpu.data 773 # number of ReadReq accesses(hits+misses) |
| system.cpu.l2cache.ReadReq_accesses::total 5160 # number of ReadReq accesses(hits+misses) |
| system.cpu.l2cache.Writeback_accesses::writebacks 18 # number of Writeback accesses(hits+misses) |
| system.cpu.l2cache.Writeback_accesses::total 18 # number of Writeback accesses(hits+misses) |
| system.cpu.l2cache.UpgradeReq_accesses::cpu.data 2 # number of UpgradeReq accesses(hits+misses) |
| system.cpu.l2cache.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) |
| system.cpu.l2cache.ReadExReq_accesses::cpu.data 1089 # number of ReadExReq accesses(hits+misses) |
| system.cpu.l2cache.ReadExReq_accesses::total 1089 # number of ReadExReq accesses(hits+misses) |
| system.cpu.l2cache.demand_accesses::cpu.inst 4387 # number of demand (read+write) accesses |
| system.cpu.l2cache.demand_accesses::cpu.data 1862 # number of demand (read+write) accesses |
| system.cpu.l2cache.demand_accesses::total 6249 # number of demand (read+write) accesses |
| system.cpu.l2cache.overall_accesses::cpu.inst 4387 # number of overall (read+write) accesses |
| system.cpu.l2cache.overall_accesses::cpu.data 1862 # number of overall (read+write) accesses |
| system.cpu.l2cache.overall_accesses::total 6249 # number of overall (read+write) accesses |
| system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.473900 # miss rate for ReadReq accesses |
| system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.886158 # miss rate for ReadReq accesses |
| system.cpu.l2cache.ReadReq_miss_rate::total 0.535659 # miss rate for ReadReq accesses |
| system.cpu.l2cache.UpgradeReq_miss_rate::cpu.data 0.500000 # miss rate for UpgradeReq accesses |
| system.cpu.l2cache.UpgradeReq_miss_rate::total 0.500000 # miss rate for UpgradeReq accesses |
| system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.991736 # miss rate for ReadExReq accesses |
| system.cpu.l2cache.ReadExReq_miss_rate::total 0.991736 # miss rate for ReadExReq accesses |
| system.cpu.l2cache.demand_miss_rate::cpu.inst 0.473900 # miss rate for demand accesses |
| system.cpu.l2cache.demand_miss_rate::cpu.data 0.947905 # miss rate for demand accesses |
| system.cpu.l2cache.demand_miss_rate::total 0.615138 # miss rate for demand accesses |
| system.cpu.l2cache.overall_miss_rate::cpu.inst 0.473900 # miss rate for overall accesses |
| system.cpu.l2cache.overall_miss_rate::cpu.data 0.947905 # miss rate for overall accesses |
| system.cpu.l2cache.overall_miss_rate::total 0.615138 # miss rate for overall accesses |
| system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 47495.189995 # average ReadReq miss latency |
| system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 53024.817518 # average ReadReq miss latency |
| system.cpu.l2cache.ReadReq_avg_miss_latency::total 48865.593343 # average ReadReq miss latency |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 43983.796296 # average ReadExReq miss latency |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::total 43983.796296 # average ReadExReq miss latency |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 47495.189995 # average overall miss latency |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.data 47492.634561 # average overall miss latency |
| system.cpu.l2cache.demand_avg_miss_latency::total 47494.016649 # average overall miss latency |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 47495.189995 # average overall miss latency |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.data 47492.634561 # average overall miss latency |
| system.cpu.l2cache.overall_avg_miss_latency::total 47494.016649 # average overall miss latency |
| system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| system.cpu.l2cache.fast_writes 0 # number of fast writes performed |
| system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| system.cpu.l2cache.ReadReq_mshr_hits::cpu.inst 4 # number of ReadReq MSHR hits |
| system.cpu.l2cache.ReadReq_mshr_hits::cpu.data 12 # number of ReadReq MSHR hits |
| system.cpu.l2cache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits |
| system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits |
| system.cpu.l2cache.demand_mshr_hits::cpu.data 12 # number of demand (read+write) MSHR hits |
| system.cpu.l2cache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits |
| system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits |
| system.cpu.l2cache.overall_mshr_hits::cpu.data 12 # number of overall MSHR hits |
| system.cpu.l2cache.overall_mshr_hits::total 16 # number of overall MSHR hits |
| system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 2075 # number of ReadReq MSHR misses |
| system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 673 # number of ReadReq MSHR misses |
| system.cpu.l2cache.ReadReq_mshr_misses::total 2748 # number of ReadReq MSHR misses |
| system.cpu.l2cache.UpgradeReq_mshr_misses::cpu.data 1 # number of UpgradeReq MSHR misses |
| system.cpu.l2cache.UpgradeReq_mshr_misses::total 1 # number of UpgradeReq MSHR misses |
| system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 1080 # number of ReadExReq MSHR misses |
| system.cpu.l2cache.ReadExReq_mshr_misses::total 1080 # number of ReadExReq MSHR misses |
| system.cpu.l2cache.demand_mshr_misses::cpu.inst 2075 # number of demand (read+write) MSHR misses |
| system.cpu.l2cache.demand_mshr_misses::cpu.data 1753 # number of demand (read+write) MSHR misses |
| system.cpu.l2cache.demand_mshr_misses::total 3828 # number of demand (read+write) MSHR misses |
| system.cpu.l2cache.overall_mshr_misses::cpu.inst 2075 # number of overall MSHR misses |
| system.cpu.l2cache.overall_mshr_misses::cpu.data 1753 # number of overall MSHR misses |
| system.cpu.l2cache.overall_mshr_misses::total 3828 # number of overall MSHR misses |
| system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 72306456 # number of ReadReq MSHR miss cycles |
| system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 27405972 # number of ReadReq MSHR miss cycles |
| system.cpu.l2cache.ReadReq_mshr_miss_latency::total 99712428 # number of ReadReq MSHR miss cycles |
| system.cpu.l2cache.UpgradeReq_mshr_miss_latency::cpu.data 10001 # number of UpgradeReq MSHR miss cycles |
| system.cpu.l2cache.UpgradeReq_mshr_miss_latency::total 10001 # number of UpgradeReq MSHR miss cycles |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 33965187 # number of ReadExReq MSHR miss cycles |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 33965187 # number of ReadExReq MSHR miss cycles |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 72306456 # number of demand (read+write) MSHR miss cycles |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 61371159 # number of demand (read+write) MSHR miss cycles |
| system.cpu.l2cache.demand_mshr_miss_latency::total 133677615 # number of demand (read+write) MSHR miss cycles |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 72306456 # number of overall MSHR miss cycles |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 61371159 # number of overall MSHR miss cycles |
| system.cpu.l2cache.overall_mshr_miss_latency::total 133677615 # number of overall MSHR miss cycles |
| system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.472988 # mshr miss rate for ReadReq accesses |
| system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.870634 # mshr miss rate for ReadReq accesses |
| system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.532558 # mshr miss rate for ReadReq accesses |
| system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.500000 # mshr miss rate for UpgradeReq accesses |
| system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.500000 # mshr miss rate for UpgradeReq accesses |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.991736 # mshr miss rate for ReadExReq accesses |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.991736 # mshr miss rate for ReadExReq accesses |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.472988 # mshr miss rate for demand accesses |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.941461 # mshr miss rate for demand accesses |
| system.cpu.l2cache.demand_mshr_miss_rate::total 0.612578 # mshr miss rate for demand accesses |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.472988 # mshr miss rate for overall accesses |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.941461 # mshr miss rate for overall accesses |
| system.cpu.l2cache.overall_mshr_miss_rate::total 0.612578 # mshr miss rate for overall accesses |
| system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 34846.484819 # average ReadReq mshr miss latency |
| system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40722.098068 # average ReadReq mshr miss latency |
| system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 36285.454148 # average ReadReq mshr miss latency |
| system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10001 # average UpgradeReq mshr miss latency |
| system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10001 # average UpgradeReq mshr miss latency |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31449.247222 # average ReadExReq mshr miss latency |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31449.247222 # average ReadExReq mshr miss latency |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 34846.484819 # average overall mshr miss latency |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 35009.217912 # average overall mshr miss latency |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::total 34921.007053 # average overall mshr miss latency |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 34846.484819 # average overall mshr miss latency |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 35009.217912 # average overall mshr miss latency |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::total 34921.007053 # average overall mshr miss latency |
| system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| |
| ---------- End Simulation Statistics ---------- |
