sparc: Get rid of some register type definitions.
These are IntReg, FloatReg, FloatRegBits, and MiscReg. These have been
supplanted by the global types RegVal and FloatRegVal.
Change-Id: I956abfc7b439b083403e1a0d01e0bb35020bde44
Reviewed-on: https://gem5-review.googlesource.com/c/13627
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
diff --git a/src/arch/sparc/decoder.hh b/src/arch/sparc/decoder.hh
index 897d112..6fa506f 100644
--- a/src/arch/sparc/decoder.hh
+++ b/src/arch/sparc/decoder.hh
@@ -46,7 +46,7 @@
// The extended machine instruction being generated
ExtMachInst emi;
bool instDone;
- MiscReg asi;
+ RegVal asi;
public:
Decoder(ISA* isa = nullptr) : instDone(false), asi(0)
@@ -93,7 +93,7 @@
}
void
- setContext(MiscReg _asi)
+ setContext(RegVal _asi)
{
asi = _asi;
}
diff --git a/src/arch/sparc/faults.cc b/src/arch/sparc/faults.cc
index 6375fa5..3859b30 100644
--- a/src/arch/sparc/faults.cc
+++ b/src/arch/sparc/faults.cc
@@ -302,15 +302,15 @@
void
doREDFault(ThreadContext *tc, TrapType tt)
{
- MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL);
- MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
+ RegVal TL = tc->readMiscRegNoEffect(MISCREG_TL);
+ RegVal TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
- MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
- MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
- MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
- MiscReg CANSAVE = tc->readMiscRegNoEffect(NumIntArchRegs + 3);
- MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL);
+ RegVal CCR = tc->readIntReg(NumIntArchRegs + 2);
+ RegVal ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
+ RegVal CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
+ RegVal CANSAVE = tc->readMiscRegNoEffect(NumIntArchRegs + 3);
+ RegVal GL = tc->readMiscRegNoEffect(MISCREG_GL);
PCState pc = tc->pcState();
TL++;
@@ -381,15 +381,15 @@
void
doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv)
{
- MiscReg TL = tc->readMiscRegNoEffect(MISCREG_TL);
- MiscReg TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
+ RegVal TL = tc->readMiscRegNoEffect(MISCREG_TL);
+ RegVal TSTATE = tc->readMiscRegNoEffect(MISCREG_TSTATE);
PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
- MiscReg CCR = tc->readIntReg(NumIntArchRegs + 2);
- MiscReg ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
- MiscReg CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
- MiscReg CANSAVE = tc->readIntReg(NumIntArchRegs + 3);
- MiscReg GL = tc->readMiscRegNoEffect(MISCREG_GL);
+ RegVal CCR = tc->readIntReg(NumIntArchRegs + 2);
+ RegVal ASI = tc->readMiscRegNoEffect(MISCREG_ASI);
+ RegVal CWP = tc->readMiscRegNoEffect(MISCREG_CWP);
+ RegVal CANSAVE = tc->readIntReg(NumIntArchRegs + 3);
+ RegVal GL = tc->readMiscRegNoEffect(MISCREG_GL);
PCState pc = tc->pcState();
// Increment the trap level
@@ -470,7 +470,7 @@
}
void
-getREDVector(MiscReg TT, Addr &PC, Addr &NPC)
+getREDVector(RegVal TT, Addr &PC, Addr &NPC)
{
//XXX The following constant might belong in a header file.
const Addr RSTVAddr = 0xFFF0000000ULL;
@@ -479,7 +479,7 @@
}
void
-getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, MiscReg TT)
+getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, RegVal TT)
{
Addr HTBA = tc->readMiscRegNoEffect(MISCREG_HTBA);
PC = (HTBA & ~mask(14)) | ((TT << 5) & mask(14));
@@ -487,7 +487,7 @@
}
void
-getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, MiscReg TT, MiscReg TL)
+getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, RegVal TT, RegVal TL)
{
Addr TBA = tc->readMiscRegNoEffect(MISCREG_TBA);
PC = (TBA & ~mask(15)) |
@@ -507,8 +507,8 @@
// We can refer to this to see what the trap level -was-, but something
// in the middle could change it in the regfile out from under us.
- MiscReg tl = tc->readMiscRegNoEffect(MISCREG_TL);
- MiscReg tt = tc->readMiscRegNoEffect(MISCREG_TT);
+ RegVal tl = tc->readMiscRegNoEffect(MISCREG_TL);
+ RegVal tt = tc->readMiscRegNoEffect(MISCREG_TT);
PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
@@ -731,7 +731,7 @@
// but does not directly affect the ASI register value in the
// architectural state. The ASI values and the context field in the
// request packet seem to have completely different uses.
- MiscReg reg_asi = tc->readMiscRegNoEffect(MISCREG_ASI);
+ RegVal reg_asi = tc->readMiscRegNoEffect(MISCREG_ASI);
ASI asi = static_cast<ASI>(reg_asi);
// The SPARC DTLB code assumes that traps are executed in context
diff --git a/src/arch/sparc/faults.hh b/src/arch/sparc/faults.hh
index 88826bf..2c44d51 100644
--- a/src/arch/sparc/faults.hh
+++ b/src/arch/sparc/faults.hh
@@ -354,12 +354,12 @@
void doNormalFault(ThreadContext *tc, TrapType tt, bool gotoHpriv);
-void getREDVector(MiscReg TT, Addr &PC, Addr &NPC);
+void getREDVector(RegVal TT, Addr &PC, Addr &NPC);
-void getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, MiscReg TT);
+void getHyperVector(ThreadContext * tc, Addr &PC, Addr &NPC, RegVal TT);
-void getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, MiscReg TT,
- MiscReg TL);
+void getPrivVector(ThreadContext *tc, Addr &PC, Addr &NPC, RegVal TT,
+ RegVal TL);
} // namespace SparcISA
diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc
index 3456029..f75d006 100644
--- a/src/arch/sparc/isa.cc
+++ b/src/arch/sparc/isa.cc
@@ -173,7 +173,7 @@
panic("Tick comparison event active when clearing the ISA object.\n");
}
-MiscReg
+RegVal
ISA::readMiscRegNoEffect(int miscReg) const
{
@@ -248,7 +248,7 @@
case MISCREG_TBA:
return tba;
case MISCREG_PSTATE:
- return (MiscReg)pstate;
+ return (RegVal)pstate;
case MISCREG_TL:
return tl;
case MISCREG_PIL:
@@ -271,7 +271,7 @@
/** Hyper privileged registers */
case MISCREG_HPSTATE:
- return (MiscReg)hpstate;
+ return (RegVal)hpstate;
case MISCREG_HTSTATE:
return htstate[tl-1];
case MISCREG_HINTP:
@@ -334,7 +334,7 @@
}
}
-MiscReg
+RegVal
ISA::readMiscReg(int miscReg, ThreadContext * tc)
{
switch (miscReg) {
@@ -383,7 +383,7 @@
}
void
-ISA::setMiscRegNoEffect(int miscReg, MiscReg val)
+ISA::setMiscRegNoEffect(int miscReg, RegVal val)
{
switch (miscReg) {
// case MISCREG_Y:
@@ -564,9 +564,9 @@
}
void
-ISA::setMiscReg(int miscReg, MiscReg val, ThreadContext * tc)
+ISA::setMiscReg(int miscReg, RegVal val, ThreadContext * tc)
{
- MiscReg new_val = val;
+ RegVal new_val = val;
switch (miscReg) {
case MISCREG_ASI:
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 9209ba3..8ad7298 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -116,8 +116,8 @@
// These need to check the int_dis field and if 0 then
// set appropriate bit in softint and checkinterrutps on the cpu
- void setFSReg(int miscReg, MiscReg val, ThreadContext *tc);
- MiscReg readFSReg(int miscReg, ThreadContext * tc);
+ void setFSReg(int miscReg, RegVal val, ThreadContext *tc);
+ RegVal readFSReg(int miscReg, ThreadContext * tc);
// Update interrupt state on softint or pil change
void checkSoftInt(ThreadContext *tc);
@@ -183,11 +183,11 @@
public:
- MiscReg readMiscRegNoEffect(int miscReg) const;
- MiscReg readMiscReg(int miscReg, ThreadContext *tc);
+ RegVal readMiscRegNoEffect(int miscReg) const;
+ RegVal readMiscReg(int miscReg, ThreadContext *tc);
- void setMiscRegNoEffect(int miscReg, MiscReg val);
- void setMiscReg(int miscReg, MiscReg val, ThreadContext *tc);
+ void setMiscRegNoEffect(int miscReg, RegVal val);
+ void setMiscReg(int miscReg, RegVal val, ThreadContext *tc);
RegId
flattenRegId(const RegId& regId) const
diff --git a/src/arch/sparc/isa/decoder.isa b/src/arch/sparc/isa/decoder.isa
index 6ca52c4..9586833 100644
--- a/src/arch/sparc/isa/decoder.isa
+++ b/src/arch/sparc/isa/decoder.isa
@@ -138,7 +138,7 @@
}
}
0x1: BranchN::call(30, {{
- IntReg midVal;
+ RegVal midVal;
R15 = midVal = (Pstate.am ? (PC)<31:0> : PC);
NNPC = midVal + disp;
}},None, None, IsIndirectControl, IsCall);
diff --git a/src/arch/sparc/linux/syscalls.cc b/src/arch/sparc/linux/syscalls.cc
index ee8c60c..773982a 100644
--- a/src/arch/sparc/linux/syscalls.cc
+++ b/src/arch/sparc/linux/syscalls.cc
@@ -60,7 +60,7 @@
SyscallReturn
getresuidFunc(SyscallDesc *desc, int num, Process *p, ThreadContext *tc)
{
- const IntReg id = htog(100);
+ const uint64_t id = htog(100);
int index = 0;
Addr ruid = p->getSyscallArg(tc, index);
Addr euid = p->getSyscallArg(tc, index);
@@ -68,20 +68,20 @@
// Handle the EFAULT case
// Set the ruid
if (ruid) {
- BufferArg ruidBuff(ruid, sizeof(IntReg));
- memcpy(ruidBuff.bufferPtr(), &id, sizeof(IntReg));
+ BufferArg ruidBuff(ruid, sizeof(uint64_t));
+ memcpy(ruidBuff.bufferPtr(), &id, sizeof(uint64_t));
ruidBuff.copyOut(tc->getMemProxy());
}
// Set the euid
if (euid) {
- BufferArg euidBuff(euid, sizeof(IntReg));
- memcpy(euidBuff.bufferPtr(), &id, sizeof(IntReg));
+ BufferArg euidBuff(euid, sizeof(uint64_t));
+ memcpy(euidBuff.bufferPtr(), &id, sizeof(uint64_t));
euidBuff.copyOut(tc->getMemProxy());
}
// Set the suid
if (suid) {
- BufferArg suidBuff(suid, sizeof(IntReg));
- memcpy(suidBuff.bufferPtr(), &id, sizeof(IntReg));
+ BufferArg suidBuff(suid, sizeof(uint64_t));
+ memcpy(suidBuff.bufferPtr(), &id, sizeof(uint64_t));
suidBuff.copyOut(tc->getMemProxy());
}
return 0;
diff --git a/src/arch/sparc/process.cc b/src/arch/sparc/process.cc
index 7dda6ed..6659a04 100644
--- a/src/arch/sparc/process.cc
+++ b/src/arch/sparc/process.cc
@@ -183,7 +183,7 @@
pstate.ie = 1;
tc->setMiscReg(MISCREG_PSTATE, pstate);
- argsInit(sizeof(IntReg), PageBytes);
+ argsInit(sizeof(RegVal), PageBytes);
}
template<class IntType>
@@ -441,11 +441,11 @@
void Sparc32Process::flushWindows(ThreadContext *tc)
{
- IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3);
- IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4);
- IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6);
- MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
- MiscReg origCWP = CWP;
+ RegVal Cansave = tc->readIntReg(NumIntArchRegs + 3);
+ RegVal Canrestore = tc->readIntReg(NumIntArchRegs + 4);
+ RegVal Otherwin = tc->readIntReg(NumIntArchRegs + 6);
+ RegVal CWP = tc->readMiscReg(MISCREG_CWP);
+ RegVal origCWP = CWP;
CWP = (CWP + Cansave + 2) % NWindows;
while (NWindows - 2 - Cansave != 0) {
if (Otherwin) {
@@ -453,7 +453,7 @@
} else {
tc->setMiscReg(MISCREG_CWP, CWP);
// Do the stores
- IntReg sp = tc->readIntReg(StackPointerReg);
+ RegVal sp = tc->readIntReg(StackPointerReg);
for (int index = 16; index < 32; index++) {
uint32_t regVal = tc->readIntReg(index);
regVal = htog(regVal);
@@ -476,11 +476,11 @@
void
Sparc64Process::flushWindows(ThreadContext *tc)
{
- IntReg Cansave = tc->readIntReg(NumIntArchRegs + 3);
- IntReg Canrestore = tc->readIntReg(NumIntArchRegs + 4);
- IntReg Otherwin = tc->readIntReg(NumIntArchRegs + 6);
- MiscReg CWP = tc->readMiscReg(MISCREG_CWP);
- MiscReg origCWP = CWP;
+ RegVal Cansave = tc->readIntReg(NumIntArchRegs + 3);
+ RegVal Canrestore = tc->readIntReg(NumIntArchRegs + 4);
+ RegVal Otherwin = tc->readIntReg(NumIntArchRegs + 6);
+ RegVal CWP = tc->readMiscReg(MISCREG_CWP);
+ RegVal origCWP = CWP;
CWP = (CWP + Cansave + 2) % NWindows;
while (NWindows - 2 - Cansave != 0) {
if (Otherwin) {
@@ -488,9 +488,9 @@
} else {
tc->setMiscReg(MISCREG_CWP, CWP);
// Do the stores
- IntReg sp = tc->readIntReg(StackPointerReg);
+ RegVal sp = tc->readIntReg(StackPointerReg);
for (int index = 16; index < 32; index++) {
- IntReg regVal = tc->readIntReg(index);
+ RegVal regVal = tc->readIntReg(index);
regVal = htog(regVal);
if (!tc->getMemProxy().tryWriteBlob(
sp + 2047 + (index - 16) * 8, (uint8_t *)®Val, 8)) {
@@ -508,7 +508,7 @@
tc->setMiscReg(MISCREG_CWP, origCWP);
}
-IntReg
+RegVal
Sparc32Process::getSyscallArg(ThreadContext *tc, int &i)
{
assert(i < 6);
@@ -516,13 +516,13 @@
}
void
-Sparc32Process::setSyscallArg(ThreadContext *tc, int i, IntReg val)
+Sparc32Process::setSyscallArg(ThreadContext *tc, int i, RegVal val)
{
assert(i < 6);
tc->setIntReg(FirstArgumentReg + i, bits(val, 31, 0));
}
-IntReg
+RegVal
Sparc64Process::getSyscallArg(ThreadContext *tc, int &i)
{
assert(i < 6);
@@ -530,7 +530,7 @@
}
void
-Sparc64Process::setSyscallArg(ThreadContext *tc, int i, IntReg val)
+Sparc64Process::setSyscallArg(ThreadContext *tc, int i, RegVal val)
{
assert(i < 6);
tc->setIntReg(FirstArgumentReg + i, val);
@@ -547,7 +547,7 @@
// no error, clear XCC.C
tc->setIntReg(NumIntArchRegs + 2,
tc->readIntReg(NumIntArchRegs + 2) & 0xEE);
- IntReg val = sysret.returnValue();
+ RegVal val = sysret.returnValue();
if (pstate.am)
val = bits(val, 31, 0);
tc->setIntReg(ReturnValueReg, val);
@@ -555,7 +555,7 @@
// got an error, set XCC.C
tc->setIntReg(NumIntArchRegs + 2,
tc->readIntReg(NumIntArchRegs + 2) | 0x11);
- IntReg val = sysret.errnoValue();
+ RegVal val = sysret.errnoValue();
if (pstate.am)
val = bits(val, 31, 0);
tc->setIntReg(ReturnValueReg, val);
diff --git a/src/arch/sparc/process.hh b/src/arch/sparc/process.hh
index d7e0967..eeb2671 100644
--- a/src/arch/sparc/process.hh
+++ b/src/arch/sparc/process.hh
@@ -109,11 +109,11 @@
void flushWindows(ThreadContext *tc);
- SparcISA::IntReg getSyscallArg(ThreadContext *tc, int &i);
+ RegVal getSyscallArg(ThreadContext *tc, int &i);
/// Explicitly import the otherwise hidden getSyscallArg
using Process::getSyscallArg;
- void setSyscallArg(ThreadContext *tc, int i, SparcISA::IntReg val);
+ void setSyscallArg(ThreadContext *tc, int i, RegVal val);
};
class Sparc64Process : public SparcProcess
@@ -153,11 +153,11 @@
void flushWindows(ThreadContext *tc);
- SparcISA::IntReg getSyscallArg(ThreadContext *tc, int &i);
+ RegVal getSyscallArg(ThreadContext *tc, int &i);
/// Explicitly import the otherwise hidden getSyscallArg
using Process::getSyscallArg;
- void setSyscallArg(ThreadContext *tc, int i, SparcISA::IntReg val);
+ void setSyscallArg(ThreadContext *tc, int i, RegVal val);
};
#endif // __SPARC_PROCESS_HH__
diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index 362126c..5f12b98 100644
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -45,11 +45,6 @@
using SparcISAInst::MaxInstDestRegs;
using SparcISAInst::MaxMiscDestRegs;
-typedef RegVal IntReg;
-typedef RegVal MiscReg;
-typedef FloatRegVal FloatReg;
-typedef RegVal FloatRegBits;
-
// dummy typedef since we don't have CC regs
typedef uint8_t CCReg;
diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 1a248d3..4cafff4 100644
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -88,7 +88,7 @@
}
void
-ISA::setFSReg(int miscReg, MiscReg val, ThreadContext *tc)
+ISA::setFSReg(int miscReg, RegVal val, ThreadContext *tc)
{
BaseCPU *cpu = tc->getCpuPtr();
@@ -242,7 +242,7 @@
}
}
-MiscReg
+RegVal
ISA::readFSReg(int miscReg, ThreadContext * tc)
{
uint64_t temp;
