commit 1c508a206f9e91aad52ef6b009940f622884f58a
author Gabe Black <gabeblack@google.com> Mon Oct 15 20:45:45 2018 -0700
committer Gabe Black <gabeblack@google.com> Wed Oct 17 20:15:26 2018 +0000
tree e2ba992f2f14294c73f1f996cc05ab6beed008a5
parent e086e74a79df938351a742c0eaebff602c4ad97d

arch: Get rid of the unused type AnyReg.

This type is defined for all the ISAs but isn't used by anything.

Change-Id: I659a0c5abc7883d82fedd1cac2cd103612d315c8
Reviewed-on: https://gem5-review.googlesource.com/c/13539
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

src/arch/alpha/registers.hh

diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh
index 151ea7d..53ade47 100644
--- a/src/arch/alpha/registers.hh
+++ b/src/arch/alpha/registers.hh
@@ -66,13 +66,6 @@
 // This has to be one to prevent warnings that are treated as errors
 constexpr unsigned NumVecRegs = 1;
 
-union AnyReg
-{
-    IntReg  intreg;
-    FloatReg   fpreg;
-    MiscReg ctrlreg;
-};
-
 enum MiscRegIndex
 {
     MISCREG_FPCR = NumInternalProcRegs,

src/arch/arm/registers.hh

diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index 0a617e4..e7defd1 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -119,13 +119,6 @@
 const int SyscallPseudoReturnReg = ReturnValueReg;
 const int SyscallSuccessReg = ReturnValueReg;
 
-typedef union {
-    IntReg   intreg;
-    FloatReg fpreg;
-    CCReg    ccreg;
-    MiscReg  ctrlreg;
-} AnyReg;
-
 } // namespace ArmISA
 
 #endif

src/arch/mips/registers.hh

diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index b44283d..55c2dee 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -299,12 +299,6 @@
 // This has to be one to prevent warnings that are treated as errors
 constexpr unsigned NumVecRegs = 1;
 
-typedef union {
-    IntReg   intreg;
-    FloatReg fpreg;
-    MiscReg  ctrlreg;
-} AnyReg;
-
 } // namespace MipsISA
 
 #endif

src/arch/power/registers.hh

diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index 4e8c9e9..adbaae5 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -95,12 +95,6 @@
 const int SyscallPseudoReturnReg = 3;
 const int SyscallSuccessReg = 3;
 
-typedef union {
-    IntReg   intreg;
-    FloatReg fpreg;
-    MiscReg  ctrlreg;
-} AnyReg;
-
 enum MiscIntRegNums {
     INTREG_CR = NumIntArchRegs,
     INTREG_XER,

src/arch/sparc/registers.hh

diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index 596fdf4..a7f4d2a 100644
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -62,13 +62,6 @@
 // This has to be one to prevent warnings that are treated as errors
 constexpr unsigned NumVecRegs = 1;
 
-typedef union
-{
-    IntReg intReg;
-    FloatReg fpreg;
-    MiscReg ctrlreg;
-} AnyReg;
-
 // semantically meaningful register indices
 const int ZeroReg = 0;      // architecturally meaningful
 // the rest of these depend on the ABI

src/arch/x86/registers.hh

diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index 9db3349..c2977f8 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -107,13 +107,6 @@
 //technically for x87 (80 bits) or at all for xmm (128 bits)
 typedef double FloatReg;
 typedef uint64_t FloatRegBits;
-typedef union
-{
-    IntReg intReg;
-    FloatReg fpReg;
-    CCReg ccReg;
-    MiscReg ctrlReg;
-} AnyReg;
 
 } // namespace X86ISA