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# Copyright (c) 2009 Advanced Micro Devices, Inc.
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#
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# redistributions in binary form must reproduce the above copyright
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# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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#
# Authors: Steve Reinhardt
# Brad Beckmann
from m5.params import *
from ClockedObject import ClockedObject
from BasicLink import BasicLink
class RubyNetwork(ClockedObject):
type = 'RubyNetwork'
cxx_class = 'Network'
cxx_header = "mem/ruby/network/Network.hh"
abstract = True
topology = Param.String("Not Specified",
"the name of the imported topology module")
number_of_virtual_networks = Param.Unsigned("Number of virtual networks "
"used by the coherence protocol in use. The on-chip network "
"assumes the protocol numbers vnets starting from 0. Therefore, "
"the number of virtual networks should be one more than the "
"highest numbered vnet in use.")
control_msg_size = Param.Int(8, "")
ruby_system = Param.RubySystem("")
routers = VectorParam.BasicRouter("Network routers")
netifs = VectorParam.ClockedObject("Network Interfaces")
ext_links = VectorParam.BasicExtLink("Links to external nodes")
int_links = VectorParam.BasicIntLink("Links between internal nodes")
slave = VectorSlavePort("CPU slave port")
master = VectorMasterPort("CPU master port")