commit 272e4aa26d8c99ea2043a12e49ac25b2e81fc7ac
author Anouk Van Laer <anouk.vanlaer@arm.com> Wed Nov 07 14:04:47 2018 +0000
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Fri Jan 04 13:24:40 2019 +0000
tree 6de218e4294e25f9f238c2187e46c178b68ead6c
parent 90ed58bcb1791b36e2ecc585ff91b842b1d89610

dev-arm: Added VGIC GICV_IIDR response

Change-Id: I60e8eadbbbf07c0f8b726213fd580aeb0dd0e00b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15278
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

src/dev/arm/vgic.cc

diff --git a/src/dev/arm/vgic.cc b/src/dev/arm/vgic.cc
index 3e29582..adb670b 100644
--- a/src/dev/arm/vgic.cc
+++ b/src/dev/arm/vgic.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013 ARM Limited
+ * Copyright (c) 2013,2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -47,9 +47,9 @@
 #include "mem/packet_access.hh"
 
 VGic::VGic(const Params *p)
-    : PioDevice(p), platform(p->platform), gic(p->gic), vcpuAddr(p->vcpu_addr),
-      hvAddr(p->hv_addr), pioDelay(p->pio_delay),
-      maintInt(p->ppint)
+    : PioDevice(p), gicvIIDR(p->gicv_iidr), platform(p->platform),
+      gic(p->gic), vcpuAddr(p->vcpu_addr), hvAddr(p->hv_addr),
+      pioDelay(p->pio_delay), maintInt(p->ppint)
 {
     for (int x = 0; x < VGIC_CPU_MAX; x++) {
         postVIntEvent[x] = new EventFunctionWrapper(
@@ -127,6 +127,9 @@
                       lr->VirtualID, lr->CpuID, i, lr->EOI);
           }
       } break;
+      case GICV_IIDR:
+        pkt->setLE<uint32_t>(gicvIIDR);
+        break;
       default:
         panic("VGIC VCPU read of bad address %#x\n", daddr);
     }

src/dev/arm/vgic.hh

diff --git a/src/dev/arm/vgic.hh b/src/dev/arm/vgic.hh
index 40e42d4..872dfcf 100644
--- a/src/dev/arm/vgic.hh
+++ b/src/dev/arm/vgic.hh
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2013 ARM Limited
+ * Copyright (c) 2013,2018 ARM Limited
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -103,6 +103,7 @@
 
     static const uint32_t LR_PENDING    = 1;
     static const uint32_t LR_ACTIVE     = 2;
+    const uint32_t gicvIIDR;
 
     /** Post interrupt to CPU */
     void processPostVIntEvent(uint32_t cpu);