dev: Explicitly specify the endianness for packet accessors.
Generally speaking, the endianness of the data devices provide or
accept is dependent on the device and not the ISA the system
executes. This change makes the devices in dev pick an endianness
rather than using the guest's.
For the ISA bus and the UART, accesses are byte sized and so endianness
doesn't matter. The ISA and PCI busses and the devices which use them
are defined to be little endian.
Change-Id: Ib0aa70f192e1d6f3b886d9f3ad41ae03bddb583f
Reviewed-on: https://gem5-review.googlesource.com/c/13462
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
diff --git a/src/dev/i2c/bus.cc b/src/dev/i2c/bus.cc
index bf8cb87..ede9d52 100644
--- a/src/dev/i2c/bus.cc
+++ b/src/dev/i2c/bus.cc
@@ -72,7 +72,7 @@
{
assert(pkt->getAddr() == pioAddr + SB_CONTROLS);
- pkt->set<uint8_t>((sda << 1) | scl);
+ pkt->setRaw<uint8_t>((sda << 1) | scl);
pkt->makeAtomicResponse();
return pioDelay;
}
@@ -172,7 +172,7 @@
void
I2CBus::updateSignals(PacketPtr pkt)
{
- uint8_t msg = pkt->get<uint8_t>();
+ uint8_t msg = pkt->getRaw<uint8_t>();
Addr daddr = pkt->getAddr() - pioAddr;
switch (daddr) {
@@ -192,7 +192,7 @@
bool
I2CBus::isClockSet(PacketPtr pkt) const
{
- uint8_t msg = pkt->get<uint8_t>();
+ uint8_t msg = pkt->getRaw<uint8_t>();
Addr daddr = pkt->getAddr() - pioAddr;
return daddr == SB_CONTROLS && (msg & 1);
}
@@ -200,7 +200,7 @@
bool
I2CBus::isStart(PacketPtr pkt) const
{
- uint8_t msg = pkt->get<uint8_t>();
+ uint8_t msg = pkt->getRaw<uint8_t>();
Addr daddr = pkt->getAddr() - pioAddr;
return scl && (msg & 2) && daddr == SB_CONTROLC;
}
@@ -208,7 +208,7 @@
bool
I2CBus::isEnd(PacketPtr pkt) const
{
- uint8_t msg = pkt->get<uint8_t>();
+ uint8_t msg = pkt->getRaw<uint8_t>();
Addr daddr = pkt->getAddr() - pioAddr;
return scl && (msg & 2) && daddr == SB_CONTROLS;
}
diff --git a/src/dev/isa_fake.cc b/src/dev/isa_fake.cc
index 92ee19a..407d08c 100644
--- a/src/dev/isa_fake.cc
+++ b/src/dev/isa_fake.cc
@@ -69,16 +69,16 @@
pkt->getAddr(), pkt->getSize());
switch (pkt->getSize()) {
case sizeof(uint64_t):
- pkt->set(retData64);
+ pkt->setLE(retData64);
break;
case sizeof(uint32_t):
- pkt->set(retData32);
+ pkt->setLE(retData32);
break;
case sizeof(uint16_t):
- pkt->set(retData16);
+ pkt->setLE(retData16);
break;
case sizeof(uint8_t):
- pkt->set(retData8);
+ pkt->setLE(retData8);
break;
default:
if (params()->fake_mem)
@@ -98,16 +98,16 @@
uint64_t data;
switch (pkt->getSize()) {
case sizeof(uint64_t):
- data = pkt->get<uint64_t>();
+ data = pkt->getLE<uint64_t>();
break;
case sizeof(uint32_t):
- data = pkt->get<uint32_t>();
+ data = pkt->getLE<uint32_t>();
break;
case sizeof(uint16_t):
- data = pkt->get<uint16_t>();
+ data = pkt->getLE<uint16_t>();
break;
case sizeof(uint8_t):
- data = pkt->get<uint8_t>();
+ data = pkt->getLE<uint8_t>();
break;
default:
panic("invalid access size: %u\n", pkt->getSize());
@@ -126,16 +126,16 @@
if (params()->update_data) {
switch (pkt->getSize()) {
case sizeof(uint64_t):
- retData64 = pkt->get<uint64_t>();
+ retData64 = pkt->getLE<uint64_t>();
break;
case sizeof(uint32_t):
- retData32 = pkt->get<uint32_t>();
+ retData32 = pkt->getLE<uint32_t>();
break;
case sizeof(uint16_t):
- retData16 = pkt->get<uint16_t>();
+ retData16 = pkt->getLE<uint16_t>();
break;
case sizeof(uint8_t):
- retData8 = pkt->get<uint8_t>();
+ retData8 = pkt->getLE<uint8_t>();
break;
default:
panic("invalid access size!\n");
diff --git a/src/dev/net/i8254xGBe.cc b/src/dev/net/i8254xGBe.cc
index 88528c4..2d55603 100644
--- a/src/dev/net/i8254xGBe.cc
+++ b/src/dev/net/i8254xGBe.cc
@@ -194,27 +194,27 @@
switch (daddr) {
case REG_CTRL:
- pkt->set<uint32_t>(regs.ctrl());
+ pkt->setLE<uint32_t>(regs.ctrl());
break;
case REG_STATUS:
- pkt->set<uint32_t>(regs.sts());
+ pkt->setLE<uint32_t>(regs.sts());
break;
case REG_EECD:
- pkt->set<uint32_t>(regs.eecd());
+ pkt->setLE<uint32_t>(regs.eecd());
break;
case REG_EERD:
- pkt->set<uint32_t>(regs.eerd());
+ pkt->setLE<uint32_t>(regs.eerd());
break;
case REG_CTRL_EXT:
- pkt->set<uint32_t>(regs.ctrl_ext());
+ pkt->setLE<uint32_t>(regs.ctrl_ext());
break;
case REG_MDIC:
- pkt->set<uint32_t>(regs.mdic());
+ pkt->setLE<uint32_t>(regs.mdic());
break;
case REG_ICR:
DPRINTF(Ethernet, "Reading ICR. ICR=%#x IMR=%#x IAM=%#x IAME=%d\n",
regs.icr(), regs.imr, regs.iam, regs.ctrl_ext.iame());
- pkt->set<uint32_t>(regs.icr());
+ pkt->setLE<uint32_t>(regs.icr());
if (regs.icr.int_assert() || regs.imr == 0) {
regs.icr = regs.icr() & ~mask(30);
DPRINTF(Ethernet, "Cleared ICR. ICR=%#x\n", regs.icr());
@@ -226,55 +226,55 @@
case REG_EICR:
// This is only useful for MSI, but the driver reads it every time
// Just don't do anything
- pkt->set<uint32_t>(0);
+ pkt->setLE<uint32_t>(0);
break;
case REG_ITR:
- pkt->set<uint32_t>(regs.itr());
+ pkt->setLE<uint32_t>(regs.itr());
break;
case REG_RCTL:
- pkt->set<uint32_t>(regs.rctl());
+ pkt->setLE<uint32_t>(regs.rctl());
break;
case REG_FCTTV:
- pkt->set<uint32_t>(regs.fcttv());
+ pkt->setLE<uint32_t>(regs.fcttv());
break;
case REG_TCTL:
- pkt->set<uint32_t>(regs.tctl());
+ pkt->setLE<uint32_t>(regs.tctl());
break;
case REG_PBA:
- pkt->set<uint32_t>(regs.pba());
+ pkt->setLE<uint32_t>(regs.pba());
break;
case REG_WUC:
case REG_WUFC:
case REG_WUS:
case REG_LEDCTL:
- pkt->set<uint32_t>(0); // We don't care, so just return 0
+ pkt->setLE<uint32_t>(0); // We don't care, so just return 0
break;
case REG_FCRTL:
- pkt->set<uint32_t>(regs.fcrtl());
+ pkt->setLE<uint32_t>(regs.fcrtl());
break;
case REG_FCRTH:
- pkt->set<uint32_t>(regs.fcrth());
+ pkt->setLE<uint32_t>(regs.fcrth());
break;
case REG_RDBAL:
- pkt->set<uint32_t>(regs.rdba.rdbal());
+ pkt->setLE<uint32_t>(regs.rdba.rdbal());
break;
case REG_RDBAH:
- pkt->set<uint32_t>(regs.rdba.rdbah());
+ pkt->setLE<uint32_t>(regs.rdba.rdbah());
break;
case REG_RDLEN:
- pkt->set<uint32_t>(regs.rdlen());
+ pkt->setLE<uint32_t>(regs.rdlen());
break;
case REG_SRRCTL:
- pkt->set<uint32_t>(regs.srrctl());
+ pkt->setLE<uint32_t>(regs.srrctl());
break;
case REG_RDH:
- pkt->set<uint32_t>(regs.rdh());
+ pkt->setLE<uint32_t>(regs.rdh());
break;
case REG_RDT:
- pkt->set<uint32_t>(regs.rdt());
+ pkt->setLE<uint32_t>(regs.rdt());
break;
case REG_RDTR:
- pkt->set<uint32_t>(regs.rdtr());
+ pkt->setLE<uint32_t>(regs.rdtr());
if (regs.rdtr.fpd()) {
rxDescCache.writeback(0);
DPRINTF(EthernetIntr,
@@ -284,65 +284,65 @@
}
break;
case REG_RXDCTL:
- pkt->set<uint32_t>(regs.rxdctl());
+ pkt->setLE<uint32_t>(regs.rxdctl());
break;
case REG_RADV:
- pkt->set<uint32_t>(regs.radv());
+ pkt->setLE<uint32_t>(regs.radv());
break;
case REG_TDBAL:
- pkt->set<uint32_t>(regs.tdba.tdbal());
+ pkt->setLE<uint32_t>(regs.tdba.tdbal());
break;
case REG_TDBAH:
- pkt->set<uint32_t>(regs.tdba.tdbah());
+ pkt->setLE<uint32_t>(regs.tdba.tdbah());
break;
case REG_TDLEN:
- pkt->set<uint32_t>(regs.tdlen());
+ pkt->setLE<uint32_t>(regs.tdlen());
break;
case REG_TDH:
- pkt->set<uint32_t>(regs.tdh());
+ pkt->setLE<uint32_t>(regs.tdh());
break;
case REG_TXDCA_CTL:
- pkt->set<uint32_t>(regs.txdca_ctl());
+ pkt->setLE<uint32_t>(regs.txdca_ctl());
break;
case REG_TDT:
- pkt->set<uint32_t>(regs.tdt());
+ pkt->setLE<uint32_t>(regs.tdt());
break;
case REG_TIDV:
- pkt->set<uint32_t>(regs.tidv());
+ pkt->setLE<uint32_t>(regs.tidv());
break;
case REG_TXDCTL:
- pkt->set<uint32_t>(regs.txdctl());
+ pkt->setLE<uint32_t>(regs.txdctl());
break;
case REG_TADV:
- pkt->set<uint32_t>(regs.tadv());
+ pkt->setLE<uint32_t>(regs.tadv());
break;
case REG_TDWBAL:
- pkt->set<uint32_t>(regs.tdwba & mask(32));
+ pkt->setLE<uint32_t>(regs.tdwba & mask(32));
break;
case REG_TDWBAH:
- pkt->set<uint32_t>(regs.tdwba >> 32);
+ pkt->setLE<uint32_t>(regs.tdwba >> 32);
break;
case REG_RXCSUM:
- pkt->set<uint32_t>(regs.rxcsum());
+ pkt->setLE<uint32_t>(regs.rxcsum());
break;
case REG_RLPML:
- pkt->set<uint32_t>(regs.rlpml);
+ pkt->setLE<uint32_t>(regs.rlpml);
break;
case REG_RFCTL:
- pkt->set<uint32_t>(regs.rfctl());
+ pkt->setLE<uint32_t>(regs.rfctl());
break;
case REG_MANC:
- pkt->set<uint32_t>(regs.manc());
+ pkt->setLE<uint32_t>(regs.manc());
break;
case REG_SWSM:
- pkt->set<uint32_t>(regs.swsm());
+ pkt->setLE<uint32_t>(regs.swsm());
regs.swsm.smbi(1);
break;
case REG_FWSM:
- pkt->set<uint32_t>(regs.fwsm());
+ pkt->setLE<uint32_t>(regs.fwsm());
break;
case REG_SWFWSYNC:
- pkt->set<uint32_t>(regs.sw_fw_sync);
+ pkt->setLE<uint32_t>(regs.sw_fw_sync);
break;
default:
if (!IN_RANGE(daddr, REG_VFTA, VLAN_FILTER_TABLE_SIZE*4) &&
@@ -351,7 +351,7 @@
!IN_RANGE(daddr, REG_CRCERRS, STATS_REGS_SIZE))
panic("Read request to unknown register number: %#x\n", daddr);
else
- pkt->set<uint32_t>(0);
+ pkt->setLE<uint32_t>(0);
};
pkt->makeAtomicResponse();
@@ -375,12 +375,12 @@
assert(pkt->getSize() == sizeof(uint32_t));
DPRINTF(Ethernet, "Wrote device register %#X value %#X\n",
- daddr, pkt->get<uint32_t>());
+ daddr, pkt->getLE<uint32_t>());
//
// Handle write of register here
//
- uint32_t val = pkt->get<uint32_t>();
+ uint32_t val = pkt->getLE<uint32_t>();
Regs::RCTL oldrctl;
Regs::TCTL oldtctl;
diff --git a/src/dev/net/ns_gige.cc b/src/dev/net/ns_gige.cc
index e1289b4..1a5adb2 100644
--- a/src/dev/net/ns_gige.cc
+++ b/src/dev/net/ns_gige.cc
@@ -209,7 +209,7 @@
// don't implement all the MIB's. hopefully the kernel
// doesn't actually DEPEND upon their values
// MIB are just hardware stats keepers
- pkt->set<uint32_t>(0);
+ pkt->setLE<uint32_t>(0);
pkt->makeAtomicResponse();
return pioDelay;
} else if (daddr > 0x3FC)
@@ -427,7 +427,7 @@
panic("Something is messed up!\n");
if (pkt->getSize() == sizeof(uint32_t)) {
- uint32_t reg = pkt->get<uint32_t>();
+ uint32_t reg = pkt->getLE<uint32_t>();
uint16_t rfaddr;
DPRINTF(EthernetPIO, "write data=%d data=%#x\n", reg, reg);
diff --git a/src/dev/net/sinic.cc b/src/dev/net/sinic.cc
index 50341a4..ce9fbb6 100644
--- a/src/dev/net/sinic.cc
+++ b/src/dev/net/sinic.cc
@@ -248,13 +248,13 @@
uint64_t value M5_VAR_USED = 0;
if (pkt->getSize() == 4) {
uint32_t reg = regData32(raddr);
- pkt->set(reg);
+ pkt->setLE(reg);
value = reg;
}
if (pkt->getSize() == 8) {
uint64_t reg = regData64(raddr);
- pkt->set(reg);
+ pkt->setLE(reg);
value = reg;
}
@@ -333,26 +333,28 @@
DPRINTF(EthernetPIO,
"write %s vnic %d: cpu=%d val=%#x da=%#x pa=%#x size=%d\n",
- info.name, index, cpu, info.size == 4 ? pkt->get<uint32_t>() :
- pkt->get<uint64_t>(), daddr, pkt->getAddr(), pkt->getSize());
+ info.name, index, cpu, info.size == 4 ?
+ pkt->getLE<uint32_t>() : pkt->getLE<uint64_t>(),
+ daddr, pkt->getAddr(), pkt->getSize());
prepareWrite(cpu, index);
switch (raddr) {
case Regs::Config:
- changeConfig(pkt->get<uint32_t>());
+ changeConfig(pkt->getLE<uint32_t>());
break;
case Regs::Command:
- command(pkt->get<uint32_t>());
+ command(pkt->getLE<uint32_t>());
break;
case Regs::IntrStatus:
- devIntrClear(regs.IntrStatus & pkt->get<uint32_t>());
+ devIntrClear(regs.IntrStatus &
+ pkt->getLE<uint32_t>());
break;
case Regs::IntrMask:
- devIntrChangeMask(pkt->get<uint32_t>());
+ devIntrChangeMask(pkt->getLE<uint32_t>());
break;
case Regs::RxData:
@@ -362,10 +364,10 @@
vnic.rxUnique = rxUnique++;
vnic.RxDone = Regs::RxDone_Busy;
- vnic.RxData = pkt->get<uint64_t>();
+ vnic.RxData = pkt->getLE<uint64_t>();
rxBusyCount++;
- if (Regs::get_RxData_Vaddr(pkt->get<uint64_t>())) {
+ if (Regs::get_RxData_Vaddr(pkt->getLE<uint64_t>())) {
panic("vtophys not implemented in newmem");
#ifdef SINIC_VTOPHYS
Addr vaddr = Regs::get_RxData_Addr(reg64);
@@ -403,7 +405,7 @@
vnic.txUnique = txUnique++;
vnic.TxDone = Regs::TxDone_Busy;
- if (Regs::get_TxData_Vaddr(pkt->get<uint64_t>())) {
+ if (Regs::get_TxData_Vaddr(pkt->getLE<uint64_t>())) {
panic("vtophys won't work here in newmem.\n");
#ifdef SINIC_VTOPHYS
Addr vaddr = Regs::get_TxData_Addr(reg64);
diff --git a/src/dev/pci/copy_engine.cc b/src/dev/pci/copy_engine.cc
index 7c87da1..7f8959a 100644
--- a/src/dev/pci/copy_engine.cc
+++ b/src/dev/pci/copy_engine.cc
@@ -193,20 +193,20 @@
switch (daddr) {
case GEN_CHANCOUNT:
assert(size == sizeof(regs.chanCount));
- pkt->set<uint8_t>(regs.chanCount);
+ pkt->setLE<uint8_t>(regs.chanCount);
break;
case GEN_XFERCAP:
assert(size == sizeof(regs.xferCap));
- pkt->set<uint8_t>(regs.xferCap);
+ pkt->setLE<uint8_t>(regs.xferCap);
break;
case GEN_INTRCTRL:
assert(size == sizeof(uint8_t));
- pkt->set<uint8_t>(regs.intrctrl());
+ pkt->setLE<uint8_t>(regs.intrctrl());
regs.intrctrl.master_int_enable(0);
break;
case GEN_ATTNSTATUS:
assert(size == sizeof(regs.attnStatus));
- pkt->set<uint32_t>(regs.attnStatus);
+ pkt->setLE<uint32_t>(regs.attnStatus);
regs.attnStatus = 0;
break;
default:
@@ -244,42 +244,42 @@
switch (daddr) {
case CHAN_CONTROL:
assert(size == sizeof(uint16_t));
- pkt->set<uint16_t>(cr.ctrl());
+ pkt->setLE<uint16_t>(cr.ctrl());
cr.ctrl.in_use(1);
break;
case CHAN_STATUS:
assert(size == sizeof(uint64_t));
- pkt->set<uint64_t>(cr.status() | (busy ? 0 : 1));
+ pkt->setLE<uint64_t>(cr.status() | (busy ? 0 : 1));
break;
case CHAN_CHAINADDR:
assert(size == sizeof(uint64_t) || size == sizeof(uint32_t));
if (size == sizeof(uint64_t))
- pkt->set<uint64_t>(cr.descChainAddr);
+ pkt->setLE<uint64_t>(cr.descChainAddr);
else
- pkt->set<uint32_t>(bits(cr.descChainAddr,0,31));
+ pkt->setLE<uint32_t>(bits(cr.descChainAddr,0,31));
break;
case CHAN_CHAINADDR_HIGH:
assert(size == sizeof(uint32_t));
- pkt->set<uint32_t>(bits(cr.descChainAddr,32,63));
+ pkt->setLE<uint32_t>(bits(cr.descChainAddr,32,63));
break;
case CHAN_COMMAND:
assert(size == sizeof(uint8_t));
- pkt->set<uint32_t>(cr.command());
+ pkt->setLE<uint32_t>(cr.command());
break;
case CHAN_CMPLNADDR:
assert(size == sizeof(uint64_t) || size == sizeof(uint32_t));
if (size == sizeof(uint64_t))
- pkt->set<uint64_t>(cr.completionAddr);
+ pkt->setLE<uint64_t>(cr.completionAddr);
else
- pkt->set<uint32_t>(bits(cr.completionAddr,0,31));
+ pkt->setLE<uint32_t>(bits(cr.completionAddr,0,31));
break;
case CHAN_CMPLNADDR_HIGH:
assert(size == sizeof(uint32_t));
- pkt->set<uint32_t>(bits(cr.completionAddr,32,63));
+ pkt->setLE<uint32_t>(bits(cr.completionAddr,32,63));
break;
case CHAN_ERROR:
assert(size == sizeof(uint32_t));
- pkt->set<uint32_t>(cr.error());
+ pkt->setLE<uint32_t>(cr.error());
break;
default:
panic("Read request to unknown channel register number: (%d)%#x\n",
@@ -308,17 +308,21 @@
///
if (size == sizeof(uint64_t)) {
- uint64_t val M5_VAR_USED = pkt->get<uint64_t>();
- DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n", daddr, val);
+ uint64_t val M5_VAR_USED = pkt->getLE<uint64_t>();
+ DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n",
+ daddr, val);
} else if (size == sizeof(uint32_t)) {
- uint32_t val M5_VAR_USED = pkt->get<uint32_t>();
- DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n", daddr, val);
+ uint32_t val M5_VAR_USED = pkt->getLE<uint32_t>();
+ DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n",
+ daddr, val);
} else if (size == sizeof(uint16_t)) {
- uint16_t val M5_VAR_USED = pkt->get<uint16_t>();
- DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n", daddr, val);
+ uint16_t val M5_VAR_USED = pkt->getLE<uint16_t>();
+ DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n",
+ daddr, val);
} else if (size == sizeof(uint8_t)) {
- uint8_t val M5_VAR_USED = pkt->get<uint8_t>();
- DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n", daddr, val);
+ uint8_t val M5_VAR_USED = pkt->getLE<uint8_t>();
+ DPRINTF(DMACopyEngine, "Wrote device register %#X value %#X\n",
+ daddr, val);
} else {
panic("Unknown size for MMIO access: %d\n", size);
}
@@ -332,7 +336,7 @@
daddr);
break;
case GEN_INTRCTRL:
- regs.intrctrl.master_int_enable(bits(pkt->get<uint8_t>(),0,1));
+ regs.intrctrl.master_int_enable(bits(pkt->getLE<uint8_t>(), 0, 1));
break;
default:
panic("Read request to unknown register number: %#x\n", daddr);
@@ -370,7 +374,7 @@
assert(size == sizeof(uint16_t));
int old_int_disable;
old_int_disable = cr.ctrl.interrupt_disable();
- cr.ctrl(pkt->get<uint16_t>());
+ cr.ctrl(pkt->getLE<uint16_t>());
if (cr.ctrl.interrupt_disable())
cr.ctrl.interrupt_disable(0);
else
@@ -384,39 +388,39 @@
case CHAN_CHAINADDR:
assert(size == sizeof(uint64_t) || size == sizeof(uint32_t));
if (size == sizeof(uint64_t))
- cr.descChainAddr = pkt->get<uint64_t>();
+ cr.descChainAddr = pkt->getLE<uint64_t>();
else
- cr.descChainAddr = (uint64_t)pkt->get<uint32_t>() |
+ cr.descChainAddr = (uint64_t)pkt->getLE<uint32_t>() |
(cr.descChainAddr & ~mask(32));
DPRINTF(DMACopyEngine, "Chain Address %x\n", cr.descChainAddr);
break;
case CHAN_CHAINADDR_HIGH:
assert(size == sizeof(uint32_t));
- cr.descChainAddr = ((uint64_t)pkt->get<uint32_t>() <<32) |
+ cr.descChainAddr = ((uint64_t)pkt->getLE<uint32_t>() << 32) |
(cr.descChainAddr & mask(32));
DPRINTF(DMACopyEngine, "Chain Address %x\n", cr.descChainAddr);
break;
case CHAN_COMMAND:
assert(size == sizeof(uint8_t));
- cr.command(pkt->get<uint8_t>());
+ cr.command(pkt->getLE<uint8_t>());
recvCommand();
break;
case CHAN_CMPLNADDR:
assert(size == sizeof(uint64_t) || size == sizeof(uint32_t));
if (size == sizeof(uint64_t))
- cr.completionAddr = pkt->get<uint64_t>();
+ cr.completionAddr = pkt->getLE<uint64_t>();
else
- cr.completionAddr = pkt->get<uint32_t>() |
+ cr.completionAddr = pkt->getLE<uint32_t>() |
(cr.completionAddr & ~mask(32));
break;
case CHAN_CMPLNADDR_HIGH:
assert(size == sizeof(uint32_t));
- cr.completionAddr = ((uint64_t)pkt->get<uint32_t>() <<32) |
+ cr.completionAddr = ((uint64_t)pkt->getLE<uint32_t>() <<32) |
(cr.completionAddr & mask(32));
break;
case CHAN_ERROR:
assert(size == sizeof(uint32_t));
- cr.error(~pkt->get<uint32_t>() & cr.error());
+ cr.error(~pkt->getLE<uint32_t>() & cr.error());
break;
default:
panic("Read request to unknown channel register number: (%d)%#x\n",
diff --git a/src/dev/pci/device.cc b/src/dev/pci/device.cc
index 4d9d29b..1097573 100644
--- a/src/dev/pci/device.cc
+++ b/src/dev/pci/device.cc
@@ -228,13 +228,13 @@
"not implemented for %s!\n", this->name());
switch (pkt->getSize()) {
case sizeof(uint8_t):
- pkt->set<uint8_t>(0);
+ pkt->setLE<uint8_t>(0);
break;
case sizeof(uint16_t):
- pkt->set<uint16_t>(0);
+ pkt->setLE<uint16_t>(0);
break;
case sizeof(uint32_t):
- pkt->set<uint32_t>(0);
+ pkt->setLE<uint32_t>(0);
break;
default:
panic("invalid access size(?) for PCI configspace!\n");
@@ -245,25 +245,25 @@
switch (pkt->getSize()) {
case sizeof(uint8_t):
- pkt->set<uint8_t>(config.data[offset]);
+ pkt->setLE<uint8_t>(config.data[offset]);
DPRINTF(PciDevice,
"readConfig: dev %#x func %#x reg %#x 1 bytes: data = %#x\n",
_busAddr.dev, _busAddr.func, offset,
- (uint32_t)pkt->get<uint8_t>());
+ (uint32_t)pkt->getLE<uint8_t>());
break;
case sizeof(uint16_t):
- pkt->set<uint16_t>(*(uint16_t*)&config.data[offset]);
+ pkt->setLE<uint16_t>(*(uint16_t*)&config.data[offset]);
DPRINTF(PciDevice,
"readConfig: dev %#x func %#x reg %#x 2 bytes: data = %#x\n",
_busAddr.dev, _busAddr.func, offset,
- (uint32_t)pkt->get<uint16_t>());
+ (uint32_t)pkt->getLE<uint16_t>());
break;
case sizeof(uint32_t):
- pkt->set<uint32_t>(*(uint32_t*)&config.data[offset]);
+ pkt->setLE<uint32_t>(*(uint32_t*)&config.data[offset]);
DPRINTF(PciDevice,
"readConfig: dev %#x func %#x reg %#x 4 bytes: data = %#x\n",
_busAddr.dev, _busAddr.func, offset,
- (uint32_t)pkt->get<uint32_t>());
+ (uint32_t)pkt->getLE<uint32_t>());
break;
default:
panic("invalid access size(?) for PCI configspace!\n");
@@ -310,13 +310,13 @@
case sizeof(uint8_t):
switch (offset) {
case PCI0_INTERRUPT_LINE:
- config.interruptLine = pkt->get<uint8_t>();
+ config.interruptLine = pkt->getLE<uint8_t>();
break;
case PCI_CACHE_LINE_SIZE:
- config.cacheLineSize = pkt->get<uint8_t>();
+ config.cacheLineSize = pkt->getLE<uint8_t>();
break;
case PCI_LATENCY_TIMER:
- config.latencyTimer = pkt->get<uint8_t>();
+ config.latencyTimer = pkt->getLE<uint8_t>();
break;
/* Do nothing for these read-only registers */
case PCI0_INTERRUPT_PIN:
@@ -331,18 +331,18 @@
DPRINTF(PciDevice,
"writeConfig: dev %#x func %#x reg %#x 1 bytes: data = %#x\n",
_busAddr.dev, _busAddr.func, offset,
- (uint32_t)pkt->get<uint8_t>());
+ (uint32_t)pkt->getLE<uint8_t>());
break;
case sizeof(uint16_t):
switch (offset) {
case PCI_COMMAND:
- config.command = pkt->get<uint8_t>();
+ config.command = pkt->getLE<uint8_t>();
break;
case PCI_STATUS:
- config.status = pkt->get<uint8_t>();
+ config.status = pkt->getLE<uint8_t>();
break;
case PCI_CACHE_LINE_SIZE:
- config.cacheLineSize = pkt->get<uint8_t>();
+ config.cacheLineSize = pkt->getLE<uint8_t>();
break;
default:
panic("writing to a read only register");
@@ -350,7 +350,7 @@
DPRINTF(PciDevice,
"writeConfig: dev %#x func %#x reg %#x 2 bytes: data = %#x\n",
_busAddr.dev, _busAddr.func, offset,
- (uint32_t)pkt->get<uint16_t>());
+ (uint32_t)pkt->getLE<uint16_t>());
break;
case sizeof(uint32_t):
switch (offset) {
@@ -366,7 +366,7 @@
if (!legacyIO[barnum]) {
// convert BAR values to host endianness
uint32_t he_old_bar = letoh(config.baseAddr[barnum]);
- uint32_t he_new_bar = letoh(pkt->get<uint32_t>());
+ uint32_t he_new_bar = letoh(pkt->getLE<uint32_t>());
uint32_t bar_mask =
BAR_IO_SPACE(he_old_bar) ? BAR_IO_MASK : BAR_MEM_MASK;
@@ -393,17 +393,17 @@
break;
case PCI0_ROM_BASE_ADDR:
- if (letoh(pkt->get<uint32_t>()) == 0xfffffffe)
+ if (letoh(pkt->getLE<uint32_t>()) == 0xfffffffe)
config.expansionROM = htole((uint32_t)0xffffffff);
else
- config.expansionROM = pkt->get<uint32_t>();
+ config.expansionROM = pkt->getLE<uint32_t>();
break;
case PCI_COMMAND:
// This could also clear some of the error bits in the Status
// register. However they should never get set, so lets ignore
// it for now
- config.command = pkt->get<uint32_t>();
+ config.command = pkt->getLE<uint32_t>();
break;
default:
@@ -412,7 +412,7 @@
DPRINTF(PciDevice,
"writeConfig: dev %#x func %#x reg %#x 4 bytes: data = %#x\n",
_busAddr.dev, _busAddr.func, offset,
- (uint32_t)pkt->get<uint32_t>());
+ (uint32_t)pkt->getLE<uint32_t>());
break;
default:
panic("invalid access size(?) for PCI configspace!\n");
diff --git a/src/dev/serial/uart8250.cc b/src/dev/serial/uart8250.cc
index 43300f5..6b0d019 100644
--- a/src/dev/serial/uart8250.cc
+++ b/src/dev/serial/uart8250.cc
@@ -108,9 +108,9 @@
case 0x0:
if (!(LCR & 0x80)) { // read byte
if (device->dataAvailable())
- pkt->set(device->readData());
+ pkt->setRaw(device->readData());
else {
- pkt->set((uint8_t)0);
+ pkt->setRaw((uint8_t)0);
// A limited amount of these are ok.
DPRINTF(Uart, "empty read of RX register\n");
}
@@ -125,7 +125,7 @@
break;
case 0x1:
if (!(LCR & 0x80)) { // Intr Enable Register(IER)
- pkt->set(IER);
+ pkt->setRaw(IER);
} else { // DLM divisor latch MSB
;
}
@@ -134,20 +134,20 @@
DPRINTF(Uart, "IIR Read, status = %#x\n", (uint32_t)status);
if (status & RX_INT) /* Rx data interrupt has a higher priority */
- pkt->set(IIR_RXID);
+ pkt->setRaw(IIR_RXID);
else if (status & TX_INT) {
- pkt->set(IIR_TXID);
+ pkt->setRaw(IIR_TXID);
//Tx interrupts are cleared on IIR reads
status &= ~TX_INT;
} else
- pkt->set(IIR_NOPEND);
+ pkt->setRaw(IIR_NOPEND);
break;
case 0x3: // Line Control Register (LCR)
- pkt->set(LCR);
+ pkt->setRaw(LCR);
break;
case 0x4: // Modem Control Register (MCR)
- pkt->set(MCR);
+ pkt->setRaw(MCR);
break;
case 0x5: // Line Status Register (LSR)
uint8_t lsr;
@@ -156,13 +156,13 @@
if (device->dataAvailable())
lsr = UART_LSR_DR;
lsr |= UART_LSR_TEMT | UART_LSR_THRE;
- pkt->set(lsr);
+ pkt->setRaw(lsr);
break;
case 0x6: // Modem Status Register (MSR)
- pkt->set((uint8_t)0);
+ pkt->setRaw((uint8_t)0);
break;
case 0x7: // Scratch Register (SCR)
- pkt->set((uint8_t)0); // doesn't exist with at 8250.
+ pkt->setRaw((uint8_t)0); // doesn't exist with at 8250.
break;
default:
panic("Tried to access a UART port that doesn't exist\n");
@@ -184,12 +184,13 @@
Addr daddr = pkt->getAddr() - pioAddr;
- DPRINTF(Uart, " write register %#x value %#x\n", daddr, pkt->get<uint8_t>());
+ DPRINTF(Uart, " write register %#x value %#x\n", daddr,
+ pkt->getRaw<uint8_t>());
switch (daddr) {
case 0x0:
if (!(LCR & 0x80)) { // write byte
- device->writeData(pkt->get<uint8_t>());
+ device->writeData(pkt->getRaw<uint8_t>());
platform->clearConsoleInt();
status &= ~TX_INT;
if (UART_IER_THRI & IER)
@@ -200,10 +201,11 @@
break;
case 0x1:
if (!(LCR & 0x80)) { // Intr Enable Register(IER)
- IER = pkt->get<uint8_t>();
+ IER = pkt->getRaw<uint8_t>();
if (UART_IER_THRI & IER)
{
- DPRINTF(Uart, "IER: IER_THRI set, scheduling TX intrrupt\n");
+ DPRINTF(Uart,
+ "IER: IER_THRI set, scheduling TX intrrupt\n");
if (curTick() - lastTxInt > 225 * SimClock::Int::ns) {
DPRINTF(Uart, "-- Interrupting Immediately... %d,%d\n",
curTick(), lastTxInt);
@@ -216,7 +218,8 @@
}
else
{
- DPRINTF(Uart, "IER: IER_THRI cleared, descheduling TX intrrupt\n");
+ DPRINTF(Uart, "IER: IER_THRI cleared, "
+ "descheduling TX intrrupt\n");
if (txIntrEvent.scheduled())
deschedule(txIntrEvent);
if (status & TX_INT)
@@ -225,10 +228,12 @@
}
if ((UART_IER_RDI & IER) && device->dataAvailable()) {
- DPRINTF(Uart, "IER: IER_RDI set, scheduling RX intrrupt\n");
+ DPRINTF(Uart,
+ "IER: IER_RDI set, scheduling RX intrrupt\n");
scheduleIntr(&rxIntrEvent);
} else {
- DPRINTF(Uart, "IER: IER_RDI cleared, descheduling RX intrrupt\n");
+ DPRINTF(Uart, "IER: IER_RDI cleared, "
+ "descheduling RX intrrupt\n");
if (rxIntrEvent.scheduled())
deschedule(rxIntrEvent);
if (status & RX_INT)
@@ -242,10 +247,10 @@
case 0x2: // FIFO Control Register (FCR)
break;
case 0x3: // Line Control Register (LCR)
- LCR = pkt->get<uint8_t>();
+ LCR = pkt->getRaw<uint8_t>();
break;
case 0x4: // Modem Control Register (MCR)
- if (pkt->get<uint8_t>() == (UART_MCR_LOOP | 0x0A))
+ if (pkt->getRaw<uint8_t>() == (UART_MCR_LOOP | 0x0A))
MCR = 0x9A;
break;
case 0x7: // Scratch Register (SCR)
diff --git a/src/dev/storage/ide_ctrl.cc b/src/dev/storage/ide_ctrl.cc
index 12d606b..91f27be 100644
--- a/src/dev/storage/ide_ctrl.cc
+++ b/src/dev/storage/ide_ctrl.cc
@@ -185,67 +185,67 @@
case sizeof(uint8_t):
switch (offset) {
case DeviceTiming:
- pkt->set<uint8_t>(deviceTiming);
+ pkt->setLE<uint8_t>(deviceTiming);
break;
case UDMAControl:
- pkt->set<uint8_t>(udmaControl);
+ pkt->setLE<uint8_t>(udmaControl);
break;
case PrimaryTiming + 1:
- pkt->set<uint8_t>(bits(htole(primaryTiming), 15, 8));
+ pkt->setLE<uint8_t>(bits(htole(primaryTiming), 15, 8));
break;
case SecondaryTiming + 1:
- pkt->set<uint8_t>(bits(htole(secondaryTiming), 15, 8));
+ pkt->setLE<uint8_t>(bits(htole(secondaryTiming), 15, 8));
break;
case IDEConfig:
- pkt->set<uint8_t>(bits(htole(ideConfig), 7, 0));
+ pkt->setLE<uint8_t>(bits(htole(ideConfig), 7, 0));
break;
case IDEConfig + 1:
- pkt->set<uint8_t>(bits(htole(ideConfig), 15, 8));
+ pkt->setLE<uint8_t>(bits(htole(ideConfig), 15, 8));
break;
default:
panic("Invalid PCI configuration read for size 1 at offset: %#x!\n",
offset);
}
DPRINTF(IdeCtrl, "PCI read offset: %#x size: 1 data: %#x\n", offset,
- (uint32_t)pkt->get<uint8_t>());
+ (uint32_t)pkt->getLE<uint8_t>());
break;
case sizeof(uint16_t):
switch (offset) {
case UDMAControl:
- pkt->set<uint16_t>(udmaControl);
+ pkt->setLE<uint16_t>(udmaControl);
break;
case PrimaryTiming:
- pkt->set<uint16_t>(primaryTiming);
+ pkt->setLE<uint16_t>(primaryTiming);
break;
case SecondaryTiming:
- pkt->set<uint16_t>(secondaryTiming);
+ pkt->setLE<uint16_t>(secondaryTiming);
break;
case UDMATiming:
- pkt->set<uint16_t>(udmaTiming);
+ pkt->setLE<uint16_t>(udmaTiming);
break;
case IDEConfig:
- pkt->set<uint16_t>(ideConfig);
+ pkt->setLE<uint16_t>(ideConfig);
break;
default:
panic("Invalid PCI configuration read for size 2 offset: %#x!\n",
offset);
}
DPRINTF(IdeCtrl, "PCI read offset: %#x size: 2 data: %#x\n", offset,
- (uint32_t)pkt->get<uint16_t>());
+ (uint32_t)pkt->getLE<uint16_t>());
break;
case sizeof(uint32_t):
switch (offset) {
case PrimaryTiming:
- pkt->set<uint32_t>(primaryTiming);
+ pkt->setLE<uint32_t>(primaryTiming);
break;
case IDEConfig:
- pkt->set<uint32_t>(ideConfig);
+ pkt->setLE<uint32_t>(ideConfig);
break;
default:
panic("No 32bit reads implemented for this device.");
}
DPRINTF(IdeCtrl, "PCI read offset: %#x size: 4 data: %#x\n", offset,
- (uint32_t)pkt->get<uint32_t>());
+ (uint32_t)pkt->getLE<uint32_t>());
break;
default:
panic("invalid access size(?) for PCI configspace!\n");
@@ -266,40 +266,40 @@
case sizeof(uint8_t):
switch (offset) {
case DeviceTiming:
- deviceTiming = pkt->get<uint8_t>();
+ deviceTiming = pkt->getLE<uint8_t>();
break;
case UDMAControl:
- udmaControl = pkt->get<uint8_t>();
+ udmaControl = pkt->getLE<uint8_t>();
break;
case IDEConfig:
- replaceBits(ideConfig, 7, 0, pkt->get<uint8_t>());
+ replaceBits(ideConfig, 7, 0, pkt->getLE<uint8_t>());
break;
case IDEConfig + 1:
- replaceBits(ideConfig, 15, 8, pkt->get<uint8_t>());
+ replaceBits(ideConfig, 15, 8, pkt->getLE<uint8_t>());
break;
default:
panic("Invalid PCI configuration write "
"for size 1 offset: %#x!\n", offset);
}
DPRINTF(IdeCtrl, "PCI write offset: %#x size: 1 data: %#x\n",
- offset, (uint32_t)pkt->get<uint8_t>());
+ offset, (uint32_t)pkt->getLE<uint8_t>());
break;
case sizeof(uint16_t):
switch (offset) {
case UDMAControl:
- udmaControl = pkt->get<uint16_t>();
+ udmaControl = pkt->getLE<uint16_t>();
break;
case PrimaryTiming:
- primaryTiming = pkt->get<uint16_t>();
+ primaryTiming = pkt->getLE<uint16_t>();
break;
case SecondaryTiming:
- secondaryTiming = pkt->get<uint16_t>();
+ secondaryTiming = pkt->getLE<uint16_t>();
break;
case UDMATiming:
- udmaTiming = pkt->get<uint16_t>();
+ udmaTiming = pkt->getLE<uint16_t>();
break;
case IDEConfig:
- ideConfig = pkt->get<uint16_t>();
+ ideConfig = pkt->getLE<uint16_t>();
break;
default:
panic("Invalid PCI configuration write "
@@ -307,15 +307,15 @@
offset);
}
DPRINTF(IdeCtrl, "PCI write offset: %#x size: 2 data: %#x\n",
- offset, (uint32_t)pkt->get<uint16_t>());
+ offset, (uint32_t)pkt->getLE<uint16_t>());
break;
case sizeof(uint32_t):
switch (offset) {
case PrimaryTiming:
- primaryTiming = pkt->get<uint32_t>();
+ primaryTiming = pkt->getLE<uint32_t>();
break;
case IDEConfig:
- ideConfig = pkt->get<uint32_t>();
+ ideConfig = pkt->getLE<uint32_t>();
break;
default:
panic("Write of unimplemented PCI config. register: %x\n", offset);
@@ -537,11 +537,11 @@
#ifndef NDEBUG
uint32_t data;
if (pkt->getSize() == 1)
- data = pkt->get<uint8_t>();
+ data = pkt->getLE<uint8_t>();
else if (pkt->getSize() == 2)
- data = pkt->get<uint16_t>();
+ data = pkt->getLE<uint16_t>();
else
- data = pkt->get<uint32_t>();
+ data = pkt->getLE<uint32_t>();
DPRINTF(IdeCtrl, "%s from offset: %#x size: %#x data: %#x\n",
read ? "Read" : "Write", pkt->getAddr(), pkt->getSize(), data);
#endif
diff --git a/src/dev/virtio/pci.cc b/src/dev/virtio/pci.cc
index 783b43e..d1b8ea1 100644
--- a/src/dev/virtio/pci.cc
+++ b/src/dev/virtio/pci.cc
@@ -88,43 +88,43 @@
case OFF_DEVICE_FEATURES:
DPRINTF(VIOIface, " DEVICE_FEATURES request\n");
assert(size == sizeof(uint32_t));
- pkt->set<uint32_t>(vio.deviceFeatures);
+ pkt->setLE<uint32_t>(vio.deviceFeatures);
break;
case OFF_GUEST_FEATURES:
DPRINTF(VIOIface, " GUEST_FEATURES request\n");
assert(size == sizeof(uint32_t));
- pkt->set<uint32_t>(vio.getGuestFeatures());
+ pkt->setLE<uint32_t>(vio.getGuestFeatures());
break;
case OFF_QUEUE_ADDRESS:
DPRINTF(VIOIface, " QUEUE_ADDRESS request\n");
assert(size == sizeof(uint32_t));
- pkt->set<uint32_t>(vio.getQueueAddress());
+ pkt->setLE<uint32_t>(vio.getQueueAddress());
break;
case OFF_QUEUE_SIZE:
DPRINTF(VIOIface, " QUEUE_SIZE request\n");
assert(size == sizeof(uint16_t));
- pkt->set<uint16_t>(vio.getQueueSize());
+ pkt->setLE<uint16_t>(vio.getQueueSize());
break;
case OFF_QUEUE_SELECT:
DPRINTF(VIOIface, " QUEUE_SELECT\n");
assert(size == sizeof(uint16_t));
- pkt->set<uint16_t>(vio.getQueueSelect());
+ pkt->setLE<uint16_t>(vio.getQueueSelect());
break;
case OFF_QUEUE_NOTIFY:
DPRINTF(VIOIface, " QUEUE_NOTIFY request\n");
assert(size == sizeof(uint16_t));
- pkt->set<uint16_t>(queueNotify);
+ pkt->setLE<uint16_t>(queueNotify);
break;
case OFF_DEVICE_STATUS:
DPRINTF(VIOIface, " DEVICE_STATUS request\n");
assert(size == sizeof(uint8_t));
- pkt->set<uint8_t>(vio.getDeviceStatus());
+ pkt->setLE<uint8_t>(vio.getDeviceStatus());
break;
case OFF_ISR_STATUS: {
@@ -135,7 +135,7 @@
interruptDeliveryPending = false;
intrClear();
}
- pkt->set<uint8_t>(isr_status);
+ pkt->setLE<uint8_t>(isr_status);
} break;
default:
@@ -173,13 +173,13 @@
case OFF_GUEST_FEATURES:
DPRINTF(VIOIface, " WRITE GUEST_FEATURES request\n");
assert(size == sizeof(uint32_t));
- vio.setGuestFeatures(pkt->get<uint32_t>());
+ vio.setGuestFeatures(pkt->getLE<uint32_t>());
break;
case OFF_QUEUE_ADDRESS:
DPRINTF(VIOIface, " WRITE QUEUE_ADDRESS\n");
assert(size == sizeof(uint32_t));
- vio.setQueueAddress(pkt->get<uint32_t>());
+ vio.setQueueAddress(pkt->getLE<uint32_t>());
break;
case OFF_QUEUE_SIZE:
@@ -189,19 +189,19 @@
case OFF_QUEUE_SELECT:
DPRINTF(VIOIface, " WRITE QUEUE_SELECT\n");
assert(size == sizeof(uint16_t));
- vio.setQueueSelect(pkt->get<uint16_t>());
+ vio.setQueueSelect(pkt->getLE<uint16_t>());
break;
case OFF_QUEUE_NOTIFY:
DPRINTF(VIOIface, " WRITE QUEUE_NOTIFY\n");
assert(size == sizeof(uint16_t));
- queueNotify = pkt->get<uint16_t>();
+ queueNotify = pkt->getLE<uint16_t>();
vio.onNotify(queueNotify);
break;
case OFF_DEVICE_STATUS: {
assert(size == sizeof(uint8_t));
- uint8_t status(pkt->get<uint8_t>());
+ uint8_t status(pkt->getLE<uint8_t>());
DPRINTF(VIOIface, "VirtIO set status: 0x%x\n", status);
vio.setDeviceStatus(status);
} break;
