| # Copyright (c) 2012 ARM Limited |
| # All rights reserved. |
| # |
| # The license below extends only to copyright in the software and shall |
| # not be construed as granting a license to any other intellectual |
| # property including but not limited to intellectual property relating |
| # to a hardware implementation of the functionality of the software |
| # licensed hereunder. You may use the software subject to the license |
| # terms below provided that you ensure that this notice is replicated |
| # unmodified and in its entirety in all distributions of the software, |
| # modified or unmodified, in source code or in binary form. |
| # |
| # Redistribution and use in source and binary forms, with or without |
| # modification, are permitted provided that the following conditions are |
| # met: redistributions of source code must retain the above copyright |
| # notice, this list of conditions and the following disclaimer; |
| # redistributions in binary form must reproduce the above copyright |
| # notice, this list of conditions and the following disclaimer in the |
| # documentation and/or other materials provided with the distribution; |
| # neither the name of the copyright holders nor the names of its |
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| # this software without specific prior written permission. |
| # |
| # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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| # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| # |
| # Authors: Andreas Hansson |
| |
| import m5 |
| from m5.objects import * |
| |
| import argparse |
| |
| parser = argparse.ArgumentParser(description='Simple memory tester') |
| parser.add_argument('--bandwidth', default=None) |
| parser.add_argument('--latency', default=None) |
| parser.add_argument('--latency_var', default=None) |
| |
| args = parser.parse_args() |
| |
| # both traffic generator and communication monitor are only available |
| # if we have protobuf support, so potentially skip this test |
| # require_sim_object("TrafficGen") |
| # require_sim_object("CommMonitor") |
| # This needs to be fixed in the new infrastructure |
| |
| # even if this is only a traffic generator, call it cpu to make sure |
| # the scripts are happy |
| cpu = TrafficGen( |
| config_file=os.path.join(os.path.dirname(os.path.abspath(__file__)), |
| "tgen-simple-mem.cfg")) |
| |
| class MyMem(SimpleMemory): |
| if args.bandwidth: |
| bandwidth = args.bandwidth |
| if args.latency: |
| latency = args.latency |
| if args.latency_var: |
| latency_var = args.latency_var |
| |
| # system simulated |
| system = System(cpu = cpu, physmem = MyMem(), |
| membus = IOXBar(width = 16), |
| clk_domain = SrcClockDomain(clock = '1GHz', |
| voltage_domain = |
| VoltageDomain())) |
| |
| # add a communication monitor, and also trace all the packets and |
| # calculate and verify stack distance |
| system.monitor = CommMonitor() |
| system.monitor.trace = MemTraceProbe(trace_file = "monitor.ptrc.gz") |
| system.monitor.stackdist = StackDistProbe(verify = True) |
| |
| # connect the traffic generator to the bus via a communication monitor |
| system.cpu.port = system.monitor.slave |
| system.monitor.master = system.membus.slave |
| |
| # connect the system port even if it is not used in this example |
| system.system_port = system.membus.slave |
| |
| # connect memory to the membus |
| system.physmem.port = system.membus.master |
| |
| # ----------------------- |
| # run simulation |
| # ----------------------- |
| |
| root = Root(full_system = False, system = system) |
| root.system.mem_mode = 'timing' |
| |
| m5.instantiate() |
| exit_event = m5.simulate(100000000000) |
| |
| print(exit_event.getCause()) |