| [root] |
| type=Root |
| children=system |
| full_system=false |
| time_sync_enable=false |
| time_sync_period=100000000000 |
| time_sync_spin_threshold=100000000 |
| |
| [system] |
| type=System |
| children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus |
| boot_osflags=a |
| clock=1000 |
| init_param=0 |
| kernel= |
| load_addr_mask=1099511627775 |
| mem_mode=timing |
| mem_ranges= |
| memories=system.physmem |
| num_work_ids=16 |
| readfile= |
| symbolfile= |
| work_begin_ckpt_count=0 |
| work_begin_cpu_id_exit=-1 |
| work_begin_exit_count=0 |
| work_cpus_ckpt_count=0 |
| work_end_ckpt_count=0 |
| work_end_exit_count=0 |
| work_item_id=-1 |
| system_port=system.membus.slave[1] |
| |
| [system.cpu0] |
| type=TimingSimpleCPU |
| children=dcache dtb icache interrupts isa itb tracer workload |
| branchPred=Null |
| checker=Null |
| clock=500 |
| cpu_id=0 |
| do_checkpoint_insts=true |
| do_quiesce=true |
| do_statistics_insts=true |
| dtb=system.cpu0.dtb |
| function_trace=false |
| function_trace_start=0 |
| interrupts=system.cpu0.interrupts |
| isa=system.cpu0.isa |
| itb=system.cpu0.itb |
| max_insts_all_threads=0 |
| max_insts_any_thread=0 |
| max_loads_all_threads=0 |
| max_loads_any_thread=0 |
| numThreads=1 |
| profile=0 |
| progress_interval=0 |
| switched_out=false |
| system=system |
| tracer=system.cpu0.tracer |
| workload=system.cpu0.workload |
| dcache_port=system.cpu0.dcache.cpu_side |
| icache_port=system.cpu0.icache.cpu_side |
| |
| [system.cpu0.dcache] |
| type=BaseCache |
| addr_ranges=0:18446744073709551615 |
| assoc=4 |
| block_size=64 |
| clock=500 |
| forward_snoops=true |
| hit_latency=2 |
| is_top_level=true |
| max_miss_count=0 |
| mshrs=4 |
| prefetch_on_access=false |
| prefetcher=Null |
| response_latency=2 |
| size=32768 |
| system=system |
| tgts_per_mshr=20 |
| two_queue=false |
| write_buffers=8 |
| cpu_side=system.cpu0.dcache_port |
| mem_side=system.toL2Bus.slave[1] |
| |
| [system.cpu0.dtb] |
| type=SparcTLB |
| size=64 |
| |
| [system.cpu0.icache] |
| type=BaseCache |
| addr_ranges=0:18446744073709551615 |
| assoc=1 |
| block_size=64 |
| clock=500 |
| forward_snoops=true |
| hit_latency=2 |
| is_top_level=true |
| max_miss_count=0 |
| mshrs=4 |
| prefetch_on_access=false |
| prefetcher=Null |
| response_latency=2 |
| size=32768 |
| system=system |
| tgts_per_mshr=20 |
| two_queue=false |
| write_buffers=8 |
| cpu_side=system.cpu0.icache_port |
| mem_side=system.toL2Bus.slave[0] |
| |
| [system.cpu0.interrupts] |
| type=SparcInterrupts |
| |
| [system.cpu0.isa] |
| type=SparcISA |
| |
| [system.cpu0.itb] |
| type=SparcTLB |
| size=64 |
| |
| [system.cpu0.tracer] |
| type=ExeTracer |
| |
| [system.cpu0.workload] |
| type=LiveProcess |
| cmd=test_atomic 4 |
| cwd= |
| egid=100 |
| env= |
| errout=cerr |
| euid=100 |
| executable=tests/test-progs/m5threads/bin/sparc/linux/test_atomic |
| gid=100 |
| input=cin |
| max_stack_size=67108864 |
| output=cout |
| pid=100 |
| ppid=99 |
| simpoint=0 |
| system=system |
| uid=100 |
| |
| [system.cpu1] |
| type=TimingSimpleCPU |
| children=dcache dtb icache interrupts isa itb tracer |
| branchPred=Null |
| checker=Null |
| clock=500 |
| cpu_id=1 |
| do_checkpoint_insts=true |
| do_quiesce=true |
| do_statistics_insts=true |
| dtb=system.cpu1.dtb |
| function_trace=false |
| function_trace_start=0 |
| interrupts=system.cpu1.interrupts |
| isa=system.cpu1.isa |
| itb=system.cpu1.itb |
| max_insts_all_threads=0 |
| max_insts_any_thread=0 |
| max_loads_all_threads=0 |
| max_loads_any_thread=0 |
| numThreads=1 |
| profile=0 |
| progress_interval=0 |
| switched_out=false |
| system=system |
| tracer=system.cpu1.tracer |
| workload=system.cpu0.workload |
| dcache_port=system.cpu1.dcache.cpu_side |
| icache_port=system.cpu1.icache.cpu_side |
| |
| [system.cpu1.dcache] |
| type=BaseCache |
| addr_ranges=0:18446744073709551615 |
| assoc=4 |
| block_size=64 |
| clock=500 |
| forward_snoops=true |
| hit_latency=2 |
| is_top_level=true |
| max_miss_count=0 |
| mshrs=4 |
| prefetch_on_access=false |
| prefetcher=Null |
| response_latency=2 |
| size=32768 |
| system=system |
| tgts_per_mshr=20 |
| two_queue=false |
| write_buffers=8 |
| cpu_side=system.cpu1.dcache_port |
| mem_side=system.toL2Bus.slave[3] |
| |
| [system.cpu1.dtb] |
| type=SparcTLB |
| size=64 |
| |
| [system.cpu1.icache] |
| type=BaseCache |
| addr_ranges=0:18446744073709551615 |
| assoc=1 |
| block_size=64 |
| clock=500 |
| forward_snoops=true |
| hit_latency=2 |
| is_top_level=true |
| max_miss_count=0 |
| mshrs=4 |
| prefetch_on_access=false |
| prefetcher=Null |
| response_latency=2 |
| size=32768 |
| system=system |
| tgts_per_mshr=20 |
| two_queue=false |
| write_buffers=8 |
| cpu_side=system.cpu1.icache_port |
| mem_side=system.toL2Bus.slave[2] |
| |
| [system.cpu1.interrupts] |
| type=SparcInterrupts |
| |
| [system.cpu1.isa] |
| type=SparcISA |
| |
| [system.cpu1.itb] |
| type=SparcTLB |
| size=64 |
| |
| [system.cpu1.tracer] |
| type=ExeTracer |
| |
| [system.cpu2] |
| type=TimingSimpleCPU |
| children=dcache dtb icache interrupts isa itb tracer |
| branchPred=Null |
| checker=Null |
| clock=500 |
| cpu_id=2 |
| do_checkpoint_insts=true |
| do_quiesce=true |
| do_statistics_insts=true |
| dtb=system.cpu2.dtb |
| function_trace=false |
| function_trace_start=0 |
| interrupts=system.cpu2.interrupts |
| isa=system.cpu2.isa |
| itb=system.cpu2.itb |
| max_insts_all_threads=0 |
| max_insts_any_thread=0 |
| max_loads_all_threads=0 |
| max_loads_any_thread=0 |
| numThreads=1 |
| profile=0 |
| progress_interval=0 |
| switched_out=false |
| system=system |
| tracer=system.cpu2.tracer |
| workload=system.cpu0.workload |
| dcache_port=system.cpu2.dcache.cpu_side |
| icache_port=system.cpu2.icache.cpu_side |
| |
| [system.cpu2.dcache] |
| type=BaseCache |
| addr_ranges=0:18446744073709551615 |
| assoc=4 |
| block_size=64 |
| clock=500 |
| forward_snoops=true |
| hit_latency=2 |
| is_top_level=true |
| max_miss_count=0 |
| mshrs=4 |
| prefetch_on_access=false |
| prefetcher=Null |
| response_latency=2 |
| size=32768 |
| system=system |
| tgts_per_mshr=20 |
| two_queue=false |
| write_buffers=8 |
| cpu_side=system.cpu2.dcache_port |
| mem_side=system.toL2Bus.slave[5] |
| |
| [system.cpu2.dtb] |
| type=SparcTLB |
| size=64 |
| |
| [system.cpu2.icache] |
| type=BaseCache |
| addr_ranges=0:18446744073709551615 |
| assoc=1 |
| block_size=64 |
| clock=500 |
| forward_snoops=true |
| hit_latency=2 |
| is_top_level=true |
| max_miss_count=0 |
| mshrs=4 |
| prefetch_on_access=false |
| prefetcher=Null |
| response_latency=2 |
| size=32768 |
| system=system |
| tgts_per_mshr=20 |
| two_queue=false |
| write_buffers=8 |
| cpu_side=system.cpu2.icache_port |
| mem_side=system.toL2Bus.slave[4] |
| |
| [system.cpu2.interrupts] |
| type=SparcInterrupts |
| |
| [system.cpu2.isa] |
| type=SparcISA |
| |
| [system.cpu2.itb] |
| type=SparcTLB |
| size=64 |
| |
| [system.cpu2.tracer] |
| type=ExeTracer |
| |
| [system.cpu3] |
| type=TimingSimpleCPU |
| children=dcache dtb icache interrupts isa itb tracer |
| branchPred=Null |
| checker=Null |
| clock=500 |
| cpu_id=3 |
| do_checkpoint_insts=true |
| do_quiesce=true |
| do_statistics_insts=true |
| dtb=system.cpu3.dtb |
| function_trace=false |
| function_trace_start=0 |
| interrupts=system.cpu3.interrupts |
| isa=system.cpu3.isa |
| itb=system.cpu3.itb |
| max_insts_all_threads=0 |
| max_insts_any_thread=0 |
| max_loads_all_threads=0 |
| max_loads_any_thread=0 |
| numThreads=1 |
| profile=0 |
| progress_interval=0 |
| switched_out=false |
| system=system |
| tracer=system.cpu3.tracer |
| workload=system.cpu0.workload |
| dcache_port=system.cpu3.dcache.cpu_side |
| icache_port=system.cpu3.icache.cpu_side |
| |
| [system.cpu3.dcache] |
| type=BaseCache |
| addr_ranges=0:18446744073709551615 |
| assoc=4 |
| block_size=64 |
| clock=500 |
| forward_snoops=true |
| hit_latency=2 |
| is_top_level=true |
| max_miss_count=0 |
| mshrs=4 |
| prefetch_on_access=false |
| prefetcher=Null |
| response_latency=2 |
| size=32768 |
| system=system |
| tgts_per_mshr=20 |
| two_queue=false |
| write_buffers=8 |
| cpu_side=system.cpu3.dcache_port |
| mem_side=system.toL2Bus.slave[7] |
| |
| [system.cpu3.dtb] |
| type=SparcTLB |
| size=64 |
| |
| [system.cpu3.icache] |
| type=BaseCache |
| addr_ranges=0:18446744073709551615 |
| assoc=1 |
| block_size=64 |
| clock=500 |
| forward_snoops=true |
| hit_latency=2 |
| is_top_level=true |
| max_miss_count=0 |
| mshrs=4 |
| prefetch_on_access=false |
| prefetcher=Null |
| response_latency=2 |
| size=32768 |
| system=system |
| tgts_per_mshr=20 |
| two_queue=false |
| write_buffers=8 |
| cpu_side=system.cpu3.icache_port |
| mem_side=system.toL2Bus.slave[6] |
| |
| [system.cpu3.interrupts] |
| type=SparcInterrupts |
| |
| [system.cpu3.isa] |
| type=SparcISA |
| |
| [system.cpu3.itb] |
| type=SparcTLB |
| size=64 |
| |
| [system.cpu3.tracer] |
| type=ExeTracer |
| |
| [system.l2c] |
| type=BaseCache |
| addr_ranges=0:18446744073709551615 |
| assoc=8 |
| block_size=64 |
| clock=500 |
| forward_snoops=true |
| hit_latency=20 |
| is_top_level=false |
| max_miss_count=0 |
| mshrs=20 |
| prefetch_on_access=false |
| prefetcher=Null |
| response_latency=20 |
| size=4194304 |
| system=system |
| tgts_per_mshr=12 |
| two_queue=false |
| write_buffers=8 |
| cpu_side=system.toL2Bus.master[0] |
| mem_side=system.membus.slave[0] |
| |
| [system.membus] |
| type=CoherentBus |
| block_size=64 |
| clock=1000 |
| header_cycles=1 |
| system=system |
| use_default_range=false |
| width=8 |
| master=system.physmem.port |
| slave=system.l2c.mem_side system.system_port |
| |
| [system.physmem] |
| type=SimpleMemory |
| bandwidth=73.000000 |
| clock=1000 |
| conf_table_reported=false |
| in_addr_map=true |
| latency=30000 |
| latency_var=0 |
| null=false |
| range=0:134217727 |
| zero=false |
| port=system.membus.master[0] |
| |
| [system.toL2Bus] |
| type=CoherentBus |
| block_size=64 |
| clock=500 |
| header_cycles=1 |
| system=system |
| use_default_range=false |
| width=8 |
| master=system.l2c.cpu_side |
| slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side |
| |
