| |
| ---------- Begin Simulation Statistics ---------- |
| sim_seconds 0.000034 # Number of seconds simulated |
| sim_ticks 33932500 # Number of ticks simulated |
| final_tick 33932500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| sim_freq 1000000000000 # Frequency of simulated ticks |
| host_inst_rate 431758 # Simulator instruction rate (inst/s) |
| host_op_rate 430982 # Simulator op (including micro ops) rate (op/s) |
| host_tick_rate 2588300068 # Simulator tick rate (ticks/s) |
| host_mem_usage 244424 # Number of bytes of host memory used |
| host_seconds 0.01 # Real time elapsed on the host |
| sim_insts 5641 # Number of instructions simulated |
| sim_ops 5641 # Number of ops (including micro ops) simulated |
| system.voltage_domain.voltage 1 # Voltage in Volts |
| system.clk_domain.clock 1000 # Clock period in ticks |
| system.physmem.bytes_read::cpu.inst 18752 # Number of bytes read from this memory |
| system.physmem.bytes_read::cpu.data 8768 # Number of bytes read from this memory |
| system.physmem.bytes_read::total 27520 # Number of bytes read from this memory |
| system.physmem.bytes_inst_read::cpu.inst 18752 # Number of instructions bytes read from this memory |
| system.physmem.bytes_inst_read::total 18752 # Number of instructions bytes read from this memory |
| system.physmem.num_reads::cpu.inst 293 # Number of read requests responded to by this memory |
| system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory |
| system.physmem.num_reads::total 430 # Number of read requests responded to by this memory |
| system.physmem.bw_read::cpu.inst 552626538 # Total read bandwidth from this memory (bytes/s) |
| system.physmem.bw_read::cpu.data 258395344 # Total read bandwidth from this memory (bytes/s) |
| system.physmem.bw_read::total 811021882 # Total read bandwidth from this memory (bytes/s) |
| system.physmem.bw_inst_read::cpu.inst 552626538 # Instruction read bandwidth from this memory (bytes/s) |
| system.physmem.bw_inst_read::total 552626538 # Instruction read bandwidth from this memory (bytes/s) |
| system.physmem.bw_total::cpu.inst 552626538 # Total bandwidth to/from this memory (bytes/s) |
| system.physmem.bw_total::cpu.data 258395344 # Total bandwidth to/from this memory (bytes/s) |
| system.physmem.bw_total::total 811021882 # Total bandwidth to/from this memory (bytes/s) |
| system.cpu_clk_domain.clock 500 # Clock period in ticks |
| system.cpu.dtb.read_hits 0 # DTB read hits |
| system.cpu.dtb.read_misses 0 # DTB read misses |
| system.cpu.dtb.read_accesses 0 # DTB read accesses |
| system.cpu.dtb.write_hits 0 # DTB write hits |
| system.cpu.dtb.write_misses 0 # DTB write misses |
| system.cpu.dtb.write_accesses 0 # DTB write accesses |
| system.cpu.dtb.hits 0 # DTB hits |
| system.cpu.dtb.misses 0 # DTB misses |
| system.cpu.dtb.accesses 0 # DTB accesses |
| system.cpu.itb.read_hits 0 # DTB read hits |
| system.cpu.itb.read_misses 0 # DTB read misses |
| system.cpu.itb.read_accesses 0 # DTB read accesses |
| system.cpu.itb.write_hits 0 # DTB write hits |
| system.cpu.itb.write_misses 0 # DTB write misses |
| system.cpu.itb.write_accesses 0 # DTB write accesses |
| system.cpu.itb.hits 0 # DTB hits |
| system.cpu.itb.misses 0 # DTB misses |
| system.cpu.itb.accesses 0 # DTB accesses |
| system.cpu.workload.num_syscalls 7 # Number of system calls |
| system.cpu.numCycles 67865 # number of cpu cycles simulated |
| system.cpu.numWorkItemsStarted 0 # number of work items this cpu started |
| system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| system.cpu.committedInsts 5641 # Number of instructions committed |
| system.cpu.committedOps 5641 # Number of ops (including micro ops) committed |
| system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses |
| system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses |
| system.cpu.num_func_calls 191 # number of times a function call or return occured |
| system.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls |
| system.cpu.num_int_insts 4957 # number of integer instructions |
| system.cpu.num_fp_insts 2 # number of float instructions |
| system.cpu.num_int_register_reads 7072 # number of times the integer registers were read |
| system.cpu.num_int_register_writes 3291 # number of times the integer registers were written |
| system.cpu.num_fp_register_reads 3 # number of times the floating registers were read |
| system.cpu.num_fp_register_writes 1 # number of times the floating registers were written |
| system.cpu.num_mem_refs 2037 # number of memory refs |
| system.cpu.num_load_insts 1135 # Number of load instructions |
| system.cpu.num_store_insts 902 # Number of store instructions |
| system.cpu.num_idle_cycles 0 # Number of idle cycles |
| system.cpu.num_busy_cycles 67865 # Number of busy cycles |
| system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles |
| system.cpu.idle_fraction 0 # Percentage of idle cycles |
| system.cpu.Branches 886 # Number of branches fetched |
| system.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction |
| system.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction |
| system.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction |
| system.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction |
| system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction |
| system.cpu.op_class::FloatCmp 0 0.00% 63.90% # Class of executed instruction |
| system.cpu.op_class::FloatCvt 0 0.00% 63.90% # Class of executed instruction |
| system.cpu.op_class::FloatMult 0 0.00% 63.90% # Class of executed instruction |
| system.cpu.op_class::FloatDiv 0 0.00% 63.90% # Class of executed instruction |
| system.cpu.op_class::FloatSqrt 0 0.00% 63.90% # Class of executed instruction |
| system.cpu.op_class::SimdAdd 0 0.00% 63.90% # Class of executed instruction |
| system.cpu.op_class::SimdAddAcc 0 0.00% 63.90% # Class of executed instruction |
| system.cpu.op_class::SimdAlu 0 0.00% 63.90% # Class of executed instruction |
| system.cpu.op_class::SimdCmp 0 0.00% 63.90% # Class of executed instruction |
| system.cpu.op_class::SimdCvt 0 0.00% 63.90% # Class of executed instruction |
| system.cpu.op_class::SimdMisc 0 0.00% 63.90% # Class of executed instruction |
| system.cpu.op_class::SimdMult 0 0.00% 63.90% # Class of executed instruction |
| system.cpu.op_class::SimdMultAcc 0 0.00% 63.90% # Class of executed instruction |
| system.cpu.op_class::SimdShift 0 0.00% 63.90% # Class of executed instruction |
| system.cpu.op_class::SimdShiftAcc 0 0.00% 63.90% # Class of executed instruction |
| system.cpu.op_class::SimdSqrt 0 0.00% 63.90% # Class of executed instruction |
| system.cpu.op_class::SimdFloatAdd 0 0.00% 63.90% # Class of executed instruction |
| system.cpu.op_class::SimdFloatAlu 0 0.00% 63.90% # Class of executed instruction |
| system.cpu.op_class::SimdFloatCmp 0 0.00% 63.90% # Class of executed instruction |
| system.cpu.op_class::SimdFloatCvt 0 0.00% 63.90% # Class of executed instruction |
| system.cpu.op_class::SimdFloatDiv 0 0.00% 63.90% # Class of executed instruction |
| system.cpu.op_class::SimdFloatMisc 0 0.00% 63.90% # Class of executed instruction |
| system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction |
| system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction |
| system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction |
| system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction |
| system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction |
| system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction |
| system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| system.cpu.op_class::total 5642 # Class of executed instruction |
| system.cpu.dcache.tags.replacements 0 # number of replacements |
| system.cpu.dcache.tags.tagsinuse 86.030444 # Cycle average of tags in use |
| system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks. |
| system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. |
| system.cpu.dcache.tags.avg_refs 13.861314 # Average number of references to valid blocks. |
| system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| system.cpu.dcache.tags.occ_blocks::cpu.data 86.030444 # Average occupied blocks per requestor |
| system.cpu.dcache.tags.occ_percent::cpu.data 0.021004 # Average percentage of cache occupancy |
| system.cpu.dcache.tags.occ_percent::total 0.021004 # Average percentage of cache occupancy |
| system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id |
| system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id |
| system.cpu.dcache.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id |
| system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id |
| system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses |
| system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses |
| system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits |
| system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits |
| system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits |
| system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits |
| system.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits |
| system.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits |
| system.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits |
| system.cpu.dcache.overall_hits::total 1899 # number of overall hits |
| system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses |
| system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses |
| system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses |
| system.cpu.dcache.WriteReq_misses::total 50 # number of WriteReq misses |
| system.cpu.dcache.demand_misses::cpu.data 137 # number of demand (read+write) misses |
| system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses |
| system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses |
| system.cpu.dcache.overall_misses::total 137 # number of overall misses |
| system.cpu.dcache.ReadReq_miss_latency::cpu.data 5394000 # number of ReadReq miss cycles |
| system.cpu.dcache.ReadReq_miss_latency::total 5394000 # number of ReadReq miss cycles |
| system.cpu.dcache.WriteReq_miss_latency::cpu.data 3100000 # number of WriteReq miss cycles |
| system.cpu.dcache.WriteReq_miss_latency::total 3100000 # number of WriteReq miss cycles |
| system.cpu.dcache.demand_miss_latency::cpu.data 8494000 # number of demand (read+write) miss cycles |
| system.cpu.dcache.demand_miss_latency::total 8494000 # number of demand (read+write) miss cycles |
| system.cpu.dcache.overall_miss_latency::cpu.data 8494000 # number of overall miss cycles |
| system.cpu.dcache.overall_miss_latency::total 8494000 # number of overall miss cycles |
| system.cpu.dcache.ReadReq_accesses::cpu.data 1135 # number of ReadReq accesses(hits+misses) |
| system.cpu.dcache.ReadReq_accesses::total 1135 # number of ReadReq accesses(hits+misses) |
| system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) |
| system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) |
| system.cpu.dcache.demand_accesses::cpu.data 2036 # number of demand (read+write) accesses |
| system.cpu.dcache.demand_accesses::total 2036 # number of demand (read+write) accesses |
| system.cpu.dcache.overall_accesses::cpu.data 2036 # number of overall (read+write) accesses |
| system.cpu.dcache.overall_accesses::total 2036 # number of overall (read+write) accesses |
| system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076652 # miss rate for ReadReq accesses |
| system.cpu.dcache.ReadReq_miss_rate::total 0.076652 # miss rate for ReadReq accesses |
| system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses |
| system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses |
| system.cpu.dcache.demand_miss_rate::cpu.data 0.067289 # miss rate for demand accesses |
| system.cpu.dcache.demand_miss_rate::total 0.067289 # miss rate for demand accesses |
| system.cpu.dcache.overall_miss_rate::cpu.data 0.067289 # miss rate for overall accesses |
| system.cpu.dcache.overall_miss_rate::total 0.067289 # miss rate for overall accesses |
| system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency |
| system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency |
| system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency |
| system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency |
| system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency |
| system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency |
| system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency |
| system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency |
| system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses |
| system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses |
| system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses |
| system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses |
| system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses |
| system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses |
| system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses |
| system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses |
| system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5307000 # number of ReadReq MSHR miss cycles |
| system.cpu.dcache.ReadReq_mshr_miss_latency::total 5307000 # number of ReadReq MSHR miss cycles |
| system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3050000 # number of WriteReq MSHR miss cycles |
| system.cpu.dcache.WriteReq_mshr_miss_latency::total 3050000 # number of WriteReq MSHR miss cycles |
| system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8357000 # number of demand (read+write) MSHR miss cycles |
| system.cpu.dcache.demand_mshr_miss_latency::total 8357000 # number of demand (read+write) MSHR miss cycles |
| system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8357000 # number of overall MSHR miss cycles |
| system.cpu.dcache.overall_mshr_miss_latency::total 8357000 # number of overall MSHR miss cycles |
| system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076652 # mshr miss rate for ReadReq accesses |
| system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076652 # mshr miss rate for ReadReq accesses |
| system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses |
| system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses |
| system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for demand accesses |
| system.cpu.dcache.demand_mshr_miss_rate::total 0.067289 # mshr miss rate for demand accesses |
| system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for overall accesses |
| system.cpu.dcache.overall_mshr_miss_rate::total 0.067289 # mshr miss rate for overall accesses |
| system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency |
| system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency |
| system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency |
| system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency |
| system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency |
| system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency |
| system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency |
| system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency |
| system.cpu.icache.tags.replacements 13 # number of replacements |
| system.cpu.icache.tags.tagsinuse 128.953338 # Cycle average of tags in use |
| system.cpu.icache.tags.total_refs 5348 # Total number of references to valid blocks. |
| system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. |
| system.cpu.icache.tags.avg_refs 18.128814 # Average number of references to valid blocks. |
| system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| system.cpu.icache.tags.occ_blocks::cpu.inst 128.953338 # Average occupied blocks per requestor |
| system.cpu.icache.tags.occ_percent::cpu.inst 0.062965 # Average percentage of cache occupancy |
| system.cpu.icache.tags.occ_percent::total 0.062965 # Average percentage of cache occupancy |
| system.cpu.icache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id |
| system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id |
| system.cpu.icache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id |
| system.cpu.icache.tags.occ_task_id_percent::1024 0.137695 # Percentage of cache occupancy per task id |
| system.cpu.icache.tags.tag_accesses 11581 # Number of tag accesses |
| system.cpu.icache.tags.data_accesses 11581 # Number of data accesses |
| system.cpu.icache.ReadReq_hits::cpu.inst 5348 # number of ReadReq hits |
| system.cpu.icache.ReadReq_hits::total 5348 # number of ReadReq hits |
| system.cpu.icache.demand_hits::cpu.inst 5348 # number of demand (read+write) hits |
| system.cpu.icache.demand_hits::total 5348 # number of demand (read+write) hits |
| system.cpu.icache.overall_hits::cpu.inst 5348 # number of overall hits |
| system.cpu.icache.overall_hits::total 5348 # number of overall hits |
| system.cpu.icache.ReadReq_misses::cpu.inst 295 # number of ReadReq misses |
| system.cpu.icache.ReadReq_misses::total 295 # number of ReadReq misses |
| system.cpu.icache.demand_misses::cpu.inst 295 # number of demand (read+write) misses |
| system.cpu.icache.demand_misses::total 295 # number of demand (read+write) misses |
| system.cpu.icache.overall_misses::cpu.inst 295 # number of overall misses |
| system.cpu.icache.overall_misses::total 295 # number of overall misses |
| system.cpu.icache.ReadReq_miss_latency::cpu.inst 18192500 # number of ReadReq miss cycles |
| system.cpu.icache.ReadReq_miss_latency::total 18192500 # number of ReadReq miss cycles |
| system.cpu.icache.demand_miss_latency::cpu.inst 18192500 # number of demand (read+write) miss cycles |
| system.cpu.icache.demand_miss_latency::total 18192500 # number of demand (read+write) miss cycles |
| system.cpu.icache.overall_miss_latency::cpu.inst 18192500 # number of overall miss cycles |
| system.cpu.icache.overall_miss_latency::total 18192500 # number of overall miss cycles |
| system.cpu.icache.ReadReq_accesses::cpu.inst 5643 # number of ReadReq accesses(hits+misses) |
| system.cpu.icache.ReadReq_accesses::total 5643 # number of ReadReq accesses(hits+misses) |
| system.cpu.icache.demand_accesses::cpu.inst 5643 # number of demand (read+write) accesses |
| system.cpu.icache.demand_accesses::total 5643 # number of demand (read+write) accesses |
| system.cpu.icache.overall_accesses::cpu.inst 5643 # number of overall (read+write) accesses |
| system.cpu.icache.overall_accesses::total 5643 # number of overall (read+write) accesses |
| system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052277 # miss rate for ReadReq accesses |
| system.cpu.icache.ReadReq_miss_rate::total 0.052277 # miss rate for ReadReq accesses |
| system.cpu.icache.demand_miss_rate::cpu.inst 0.052277 # miss rate for demand accesses |
| system.cpu.icache.demand_miss_rate::total 0.052277 # miss rate for demand accesses |
| system.cpu.icache.overall_miss_rate::cpu.inst 0.052277 # miss rate for overall accesses |
| system.cpu.icache.overall_miss_rate::total 0.052277 # miss rate for overall accesses |
| system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61669.491525 # average ReadReq miss latency |
| system.cpu.icache.ReadReq_avg_miss_latency::total 61669.491525 # average ReadReq miss latency |
| system.cpu.icache.demand_avg_miss_latency::cpu.inst 61669.491525 # average overall miss latency |
| system.cpu.icache.demand_avg_miss_latency::total 61669.491525 # average overall miss latency |
| system.cpu.icache.overall_avg_miss_latency::cpu.inst 61669.491525 # average overall miss latency |
| system.cpu.icache.overall_avg_miss_latency::total 61669.491525 # average overall miss latency |
| system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| system.cpu.icache.writebacks::writebacks 13 # number of writebacks |
| system.cpu.icache.writebacks::total 13 # number of writebacks |
| system.cpu.icache.ReadReq_mshr_misses::cpu.inst 295 # number of ReadReq MSHR misses |
| system.cpu.icache.ReadReq_mshr_misses::total 295 # number of ReadReq MSHR misses |
| system.cpu.icache.demand_mshr_misses::cpu.inst 295 # number of demand (read+write) MSHR misses |
| system.cpu.icache.demand_mshr_misses::total 295 # number of demand (read+write) MSHR misses |
| system.cpu.icache.overall_mshr_misses::cpu.inst 295 # number of overall MSHR misses |
| system.cpu.icache.overall_mshr_misses::total 295 # number of overall MSHR misses |
| system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17897500 # number of ReadReq MSHR miss cycles |
| system.cpu.icache.ReadReq_mshr_miss_latency::total 17897500 # number of ReadReq MSHR miss cycles |
| system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17897500 # number of demand (read+write) MSHR miss cycles |
| system.cpu.icache.demand_mshr_miss_latency::total 17897500 # number of demand (read+write) MSHR miss cycles |
| system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17897500 # number of overall MSHR miss cycles |
| system.cpu.icache.overall_mshr_miss_latency::total 17897500 # number of overall MSHR miss cycles |
| system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for ReadReq accesses |
| system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052277 # mshr miss rate for ReadReq accesses |
| system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for demand accesses |
| system.cpu.icache.demand_mshr_miss_rate::total 0.052277 # mshr miss rate for demand accesses |
| system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for overall accesses |
| system.cpu.icache.overall_mshr_miss_rate::total 0.052277 # mshr miss rate for overall accesses |
| system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60669.491525 # average ReadReq mshr miss latency |
| system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60669.491525 # average ReadReq mshr miss latency |
| system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency |
| system.cpu.icache.demand_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency |
| system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency |
| system.cpu.icache.overall_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency |
| system.cpu.l2cache.tags.replacements 0 # number of replacements |
| system.cpu.l2cache.tags.tagsinuse 183.490494 # Cycle average of tags in use |
| system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks. |
| system.cpu.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks. |
| system.cpu.l2cache.tags.avg_refs 0.039474 # Average number of references to valid blocks. |
| system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.087016 # Average occupied blocks per requestor |
| system.cpu.l2cache.tags.occ_blocks::cpu.data 53.403478 # Average occupied blocks per requestor |
| system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003970 # Average percentage of cache occupancy |
| system.cpu.l2cache.tags.occ_percent::cpu.data 0.001630 # Average percentage of cache occupancy |
| system.cpu.l2cache.tags.occ_percent::total 0.005600 # Average percentage of cache occupancy |
| system.cpu.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id |
| system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011597 # Percentage of cache occupancy per task id |
| system.cpu.l2cache.tags.tag_accesses 3990 # Number of tag accesses |
| system.cpu.l2cache.tags.data_accesses 3990 # Number of data accesses |
| system.cpu.l2cache.WritebackClean_hits::writebacks 13 # number of WritebackClean hits |
| system.cpu.l2cache.WritebackClean_hits::total 13 # number of WritebackClean hits |
| system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits |
| system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits |
| system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits |
| system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits |
| system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits |
| system.cpu.l2cache.overall_hits::total 2 # number of overall hits |
| system.cpu.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses |
| system.cpu.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses |
| system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 293 # number of ReadCleanReq misses |
| system.cpu.l2cache.ReadCleanReq_misses::total 293 # number of ReadCleanReq misses |
| system.cpu.l2cache.ReadSharedReq_misses::cpu.data 87 # number of ReadSharedReq misses |
| system.cpu.l2cache.ReadSharedReq_misses::total 87 # number of ReadSharedReq misses |
| system.cpu.l2cache.demand_misses::cpu.inst 293 # number of demand (read+write) misses |
| system.cpu.l2cache.demand_misses::cpu.data 137 # number of demand (read+write) misses |
| system.cpu.l2cache.demand_misses::total 430 # number of demand (read+write) misses |
| system.cpu.l2cache.overall_misses::cpu.inst 293 # number of overall misses |
| system.cpu.l2cache.overall_misses::cpu.data 137 # number of overall misses |
| system.cpu.l2cache.overall_misses::total 430 # number of overall misses |
| system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2975000 # number of ReadExReq miss cycles |
| system.cpu.l2cache.ReadExReq_miss_latency::total 2975000 # number of ReadExReq miss cycles |
| system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 17434000 # number of ReadCleanReq miss cycles |
| system.cpu.l2cache.ReadCleanReq_miss_latency::total 17434000 # number of ReadCleanReq miss cycles |
| system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5176500 # number of ReadSharedReq miss cycles |
| system.cpu.l2cache.ReadSharedReq_miss_latency::total 5176500 # number of ReadSharedReq miss cycles |
| system.cpu.l2cache.demand_miss_latency::cpu.inst 17434000 # number of demand (read+write) miss cycles |
| system.cpu.l2cache.demand_miss_latency::cpu.data 8151500 # number of demand (read+write) miss cycles |
| system.cpu.l2cache.demand_miss_latency::total 25585500 # number of demand (read+write) miss cycles |
| system.cpu.l2cache.overall_miss_latency::cpu.inst 17434000 # number of overall miss cycles |
| system.cpu.l2cache.overall_miss_latency::cpu.data 8151500 # number of overall miss cycles |
| system.cpu.l2cache.overall_miss_latency::total 25585500 # number of overall miss cycles |
| system.cpu.l2cache.WritebackClean_accesses::writebacks 13 # number of WritebackClean accesses(hits+misses) |
| system.cpu.l2cache.WritebackClean_accesses::total 13 # number of WritebackClean accesses(hits+misses) |
| system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) |
| system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) |
| system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 295 # number of ReadCleanReq accesses(hits+misses) |
| system.cpu.l2cache.ReadCleanReq_accesses::total 295 # number of ReadCleanReq accesses(hits+misses) |
| system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 87 # number of ReadSharedReq accesses(hits+misses) |
| system.cpu.l2cache.ReadSharedReq_accesses::total 87 # number of ReadSharedReq accesses(hits+misses) |
| system.cpu.l2cache.demand_accesses::cpu.inst 295 # number of demand (read+write) accesses |
| system.cpu.l2cache.demand_accesses::cpu.data 137 # number of demand (read+write) accesses |
| system.cpu.l2cache.demand_accesses::total 432 # number of demand (read+write) accesses |
| system.cpu.l2cache.overall_accesses::cpu.inst 295 # number of overall (read+write) accesses |
| system.cpu.l2cache.overall_accesses::cpu.data 137 # number of overall (read+write) accesses |
| system.cpu.l2cache.overall_accesses::total 432 # number of overall (read+write) accesses |
| system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses |
| system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses |
| system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.993220 # miss rate for ReadCleanReq accesses |
| system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.993220 # miss rate for ReadCleanReq accesses |
| system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses |
| system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses |
| system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993220 # miss rate for demand accesses |
| system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses |
| system.cpu.l2cache.demand_miss_rate::total 0.995370 # miss rate for demand accesses |
| system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993220 # miss rate for overall accesses |
| system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses |
| system.cpu.l2cache.overall_miss_rate::total 0.995370 # miss rate for overall accesses |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency |
| system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.706485 # average ReadCleanReq miss latency |
| system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.706485 # average ReadCleanReq miss latency |
| system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency |
| system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.706485 # average overall miss latency |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency |
| system.cpu.l2cache.demand_avg_miss_latency::total 59501.162791 # average overall miss latency |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.706485 # average overall miss latency |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency |
| system.cpu.l2cache.overall_avg_miss_latency::total 59501.162791 # average overall miss latency |
| system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses |
| system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses |
| system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 293 # number of ReadCleanReq MSHR misses |
| system.cpu.l2cache.ReadCleanReq_mshr_misses::total 293 # number of ReadCleanReq MSHR misses |
| system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 87 # number of ReadSharedReq MSHR misses |
| system.cpu.l2cache.ReadSharedReq_mshr_misses::total 87 # number of ReadSharedReq MSHR misses |
| system.cpu.l2cache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses |
| system.cpu.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses |
| system.cpu.l2cache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses |
| system.cpu.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses |
| system.cpu.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses |
| system.cpu.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2475000 # number of ReadExReq MSHR miss cycles |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2475000 # number of ReadExReq MSHR miss cycles |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14504000 # number of ReadCleanReq MSHR miss cycles |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14504000 # number of ReadCleanReq MSHR miss cycles |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4306500 # number of ReadSharedReq MSHR miss cycles |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4306500 # number of ReadSharedReq MSHR miss cycles |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14504000 # number of demand (read+write) MSHR miss cycles |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6781500 # number of demand (read+write) MSHR miss cycles |
| system.cpu.l2cache.demand_mshr_miss_latency::total 21285500 # number of demand (read+write) MSHR miss cycles |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14504000 # number of overall MSHR miss cycles |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6781500 # number of overall MSHR miss cycles |
| system.cpu.l2cache.overall_mshr_miss_latency::total 21285500 # number of overall MSHR miss cycles |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for ReadCleanReq accesses |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993220 # mshr miss rate for ReadCleanReq accesses |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for demand accesses |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses |
| system.cpu.l2cache.demand_mshr_miss_rate::total 0.995370 # mshr miss rate for demand accesses |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for overall accesses |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses |
| system.cpu.l2cache.overall_mshr_miss_rate::total 0.995370 # mshr miss rate for overall accesses |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.706485 # average ReadCleanReq mshr miss latency |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.706485 # average ReadCleanReq mshr miss latency |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.706485 # average overall mshr miss latency |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.162791 # average overall mshr miss latency |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.706485 # average overall mshr miss latency |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.162791 # average overall mshr miss latency |
| system.cpu.toL2Bus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. |
| system.cpu.toL2Bus.snoop_filter.hit_single_requests 13 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. |
| system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::WritebackClean 13 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::ReadCleanReq 295 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::ReadSharedReq 87 # Transaction distribution |
| system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 603 # Packet count per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_count::total 877 # Packet count per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19712 # Cumulative packet size per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_size::total 28480 # Cumulative packet size per connected master and slave (bytes) |
| system.cpu.toL2Bus.snoops 0 # Total snoops (count) |
| system.cpu.toL2Bus.snoop_fanout::samples 432 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::0 432 100.00% 100.00% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::total 432 # Request fanout histogram |
| system.cpu.toL2Bus.reqLayer0.occupancy 235500 # Layer occupancy (ticks) |
| system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) |
| system.cpu.toL2Bus.respLayer0.occupancy 442500 # Layer occupancy (ticks) |
| system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) |
| system.cpu.toL2Bus.respLayer1.occupancy 205500 # Layer occupancy (ticks) |
| system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) |
| system.membus.trans_dist::ReadResp 380 # Transaction distribution |
| system.membus.trans_dist::ReadExReq 50 # Transaction distribution |
| system.membus.trans_dist::ReadExResp 50 # Transaction distribution |
| system.membus.trans_dist::ReadSharedReq 380 # Transaction distribution |
| system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 860 # Packet count per connected master and slave (bytes) |
| system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes) |
| system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27520 # Cumulative packet size per connected master and slave (bytes) |
| system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes) |
| system.membus.snoops 0 # Total snoops (count) |
| system.membus.snoop_fanout::samples 430 # Request fanout histogram |
| system.membus.snoop_fanout::mean 0 # Request fanout histogram |
| system.membus.snoop_fanout::stdev 0 # Request fanout histogram |
| system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| system.membus.snoop_fanout::0 430 100.00% 100.00% # Request fanout histogram |
| system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram |
| system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| system.membus.snoop_fanout::min_value 0 # Request fanout histogram |
| system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| system.membus.snoop_fanout::total 430 # Request fanout histogram |
| system.membus.reqLayer0.occupancy 430500 # Layer occupancy (ticks) |
| system.membus.reqLayer0.utilization 1.3 # Layer utilization (%) |
| system.membus.respLayer1.occupancy 2150000 # Layer occupancy (ticks) |
| system.membus.respLayer1.utilization 6.3 # Layer utilization (%) |
| |
| ---------- End Simulation Statistics ---------- |
