| |
| ---------- Begin Simulation Statistics ---------- |
| sim_seconds 0.000026 # Number of seconds simulated |
| sim_ticks 25816500 # Number of ticks simulated |
| final_tick 25816500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| sim_freq 1000000000000 # Frequency of simulated ticks |
| host_inst_rate 77759 # Simulator instruction rate (inst/s) |
| host_op_rate 90742 # Simulator op (including micro ops) rate (op/s) |
| host_tick_rate 439383785 # Simulator tick rate (ticks/s) |
| host_mem_usage 301384 # Number of bytes of host memory used |
| host_seconds 0.06 # Real time elapsed on the host |
| sim_insts 4566 # Number of instructions simulated |
| sim_ops 5330 # Number of ops (including micro ops) simulated |
| system.voltage_domain.voltage 1 # Voltage in Volts |
| system.clk_domain.clock 1000 # Clock period in ticks |
| system.physmem.bytes_read::cpu.inst 14400 # Number of bytes read from this memory |
| system.physmem.bytes_read::cpu.data 8000 # Number of bytes read from this memory |
| system.physmem.bytes_read::total 22400 # Number of bytes read from this memory |
| system.physmem.bytes_inst_read::cpu.inst 14400 # Number of instructions bytes read from this memory |
| system.physmem.bytes_inst_read::total 14400 # Number of instructions bytes read from this memory |
| system.physmem.num_reads::cpu.inst 225 # Number of read requests responded to by this memory |
| system.physmem.num_reads::cpu.data 125 # Number of read requests responded to by this memory |
| system.physmem.num_reads::total 350 # Number of read requests responded to by this memory |
| system.physmem.bw_read::cpu.inst 557782813 # Total read bandwidth from this memory (bytes/s) |
| system.physmem.bw_read::cpu.data 309879341 # Total read bandwidth from this memory (bytes/s) |
| system.physmem.bw_read::total 867662154 # Total read bandwidth from this memory (bytes/s) |
| system.physmem.bw_inst_read::cpu.inst 557782813 # Instruction read bandwidth from this memory (bytes/s) |
| system.physmem.bw_inst_read::total 557782813 # Instruction read bandwidth from this memory (bytes/s) |
| system.physmem.bw_total::cpu.inst 557782813 # Total bandwidth to/from this memory (bytes/s) |
| system.physmem.bw_total::cpu.data 309879341 # Total bandwidth to/from this memory (bytes/s) |
| system.physmem.bw_total::total 867662154 # Total bandwidth to/from this memory (bytes/s) |
| system.cpu_clk_domain.clock 500 # Clock period in ticks |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits |
| system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses |
| system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits |
| system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses |
| system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits |
| system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB |
| system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch |
| system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions |
| system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses |
| system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses |
| system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses |
| system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits |
| system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses |
| system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| system.cpu.dtb.walker.walks 0 # Table walker walks requested |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.inst_hits 0 # ITB inst hits |
| system.cpu.dtb.inst_misses 0 # ITB inst misses |
| system.cpu.dtb.read_hits 0 # DTB read hits |
| system.cpu.dtb.read_misses 0 # DTB read misses |
| system.cpu.dtb.write_hits 0 # DTB write hits |
| system.cpu.dtb.write_misses 0 # DTB write misses |
| system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed |
| system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID |
| system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB |
| system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch |
| system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions |
| system.cpu.dtb.read_accesses 0 # DTB read accesses |
| system.cpu.dtb.write_accesses 0 # DTB write accesses |
| system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| system.cpu.dtb.hits 0 # DTB hits |
| system.cpu.dtb.misses 0 # DTB misses |
| system.cpu.dtb.accesses 0 # DTB accesses |
| system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits |
| system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses |
| system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits |
| system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses |
| system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits |
| system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB |
| system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch |
| system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions |
| system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses |
| system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses |
| system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses |
| system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits |
| system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses |
| system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| system.cpu.itb.walker.walks 0 # Table walker walks requested |
| system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.inst_hits 0 # ITB inst hits |
| system.cpu.itb.inst_misses 0 # ITB inst misses |
| system.cpu.itb.read_hits 0 # DTB read hits |
| system.cpu.itb.read_misses 0 # DTB read misses |
| system.cpu.itb.write_hits 0 # DTB write hits |
| system.cpu.itb.write_misses 0 # DTB write misses |
| system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed |
| system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID |
| system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB |
| system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch |
| system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions |
| system.cpu.itb.read_accesses 0 # DTB read accesses |
| system.cpu.itb.write_accesses 0 # DTB write accesses |
| system.cpu.itb.inst_accesses 0 # ITB inst accesses |
| system.cpu.itb.hits 0 # DTB hits |
| system.cpu.itb.misses 0 # DTB misses |
| system.cpu.itb.accesses 0 # DTB accesses |
| system.cpu.workload.num_syscalls 13 # Number of system calls |
| system.cpu.numCycles 51633 # number of cpu cycles simulated |
| system.cpu.numWorkItemsStarted 0 # number of work items this cpu started |
| system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| system.cpu.committedInsts 4566 # Number of instructions committed |
| system.cpu.committedOps 5330 # Number of ops (including micro ops) committed |
| system.cpu.num_int_alu_accesses 4624 # Number of integer alu accesses |
| system.cpu.num_fp_alu_accesses 16 # Number of float alu accesses |
| system.cpu.num_func_calls 203 # number of times a function call or return occured |
| system.cpu.num_conditional_control_insts 722 # number of instructions that are conditional controls |
| system.cpu.num_int_insts 4624 # number of integer instructions |
| system.cpu.num_fp_insts 16 # number of float instructions |
| system.cpu.num_int_register_reads 7573 # number of times the integer registers were read |
| system.cpu.num_int_register_writes 2728 # number of times the integer registers were written |
| system.cpu.num_fp_register_reads 16 # number of times the floating registers were read |
| system.cpu.num_fp_register_writes 0 # number of times the floating registers were written |
| system.cpu.num_cc_register_reads 19187 # number of times the CC registers were read |
| system.cpu.num_cc_register_writes 2432 # number of times the CC registers were written |
| system.cpu.num_mem_refs 1965 # number of memory refs |
| system.cpu.num_load_insts 1027 # Number of load instructions |
| system.cpu.num_store_insts 938 # Number of store instructions |
| system.cpu.num_idle_cycles 0.002000 # Number of idle cycles |
| system.cpu.num_busy_cycles 51632.998000 # Number of busy cycles |
| system.cpu.not_idle_fraction 1.000000 # Percentage of non-idle cycles |
| system.cpu.idle_fraction 0.000000 # Percentage of idle cycles |
| system.cpu.Branches 1008 # Number of branches fetched |
| system.cpu.op_class::No_OpClass 0 0.00% 0.00% # Class of executed instruction |
| system.cpu.op_class::IntAlu 3419 63.42% 63.42% # Class of executed instruction |
| system.cpu.op_class::IntMult 4 0.07% 63.49% # Class of executed instruction |
| system.cpu.op_class::IntDiv 0 0.00% 63.49% # Class of executed instruction |
| system.cpu.op_class::FloatAdd 0 0.00% 63.49% # Class of executed instruction |
| system.cpu.op_class::FloatCmp 0 0.00% 63.49% # Class of executed instruction |
| system.cpu.op_class::FloatCvt 0 0.00% 63.49% # Class of executed instruction |
| system.cpu.op_class::FloatMult 0 0.00% 63.49% # Class of executed instruction |
| system.cpu.op_class::FloatDiv 0 0.00% 63.49% # Class of executed instruction |
| system.cpu.op_class::FloatSqrt 0 0.00% 63.49% # Class of executed instruction |
| system.cpu.op_class::SimdAdd 0 0.00% 63.49% # Class of executed instruction |
| system.cpu.op_class::SimdAddAcc 0 0.00% 63.49% # Class of executed instruction |
| system.cpu.op_class::SimdAlu 0 0.00% 63.49% # Class of executed instruction |
| system.cpu.op_class::SimdCmp 0 0.00% 63.49% # Class of executed instruction |
| system.cpu.op_class::SimdCvt 0 0.00% 63.49% # Class of executed instruction |
| system.cpu.op_class::SimdMisc 0 0.00% 63.49% # Class of executed instruction |
| system.cpu.op_class::SimdMult 0 0.00% 63.49% # Class of executed instruction |
| system.cpu.op_class::SimdMultAcc 0 0.00% 63.49% # Class of executed instruction |
| system.cpu.op_class::SimdShift 0 0.00% 63.49% # Class of executed instruction |
| system.cpu.op_class::SimdShiftAcc 0 0.00% 63.49% # Class of executed instruction |
| system.cpu.op_class::SimdSqrt 0 0.00% 63.49% # Class of executed instruction |
| system.cpu.op_class::SimdFloatAdd 0 0.00% 63.49% # Class of executed instruction |
| system.cpu.op_class::SimdFloatAlu 0 0.00% 63.49% # Class of executed instruction |
| system.cpu.op_class::SimdFloatCmp 0 0.00% 63.49% # Class of executed instruction |
| system.cpu.op_class::SimdFloatCvt 0 0.00% 63.49% # Class of executed instruction |
| system.cpu.op_class::SimdFloatDiv 0 0.00% 63.49% # Class of executed instruction |
| system.cpu.op_class::SimdFloatMisc 3 0.06% 63.55% # Class of executed instruction |
| system.cpu.op_class::SimdFloatMult 0 0.00% 63.55% # Class of executed instruction |
| system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.55% # Class of executed instruction |
| system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.55% # Class of executed instruction |
| system.cpu.op_class::MemRead 1027 19.05% 82.60% # Class of executed instruction |
| system.cpu.op_class::MemWrite 938 17.40% 100.00% # Class of executed instruction |
| system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction |
| system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction |
| system.cpu.op_class::total 5391 # Class of executed instruction |
| system.cpu.dcache.tags.replacements 0 # number of replacements |
| system.cpu.dcache.tags.tagsinuse 82.896193 # Cycle average of tags in use |
| system.cpu.dcache.tags.total_refs 1786 # Total number of references to valid blocks. |
| system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. |
| system.cpu.dcache.tags.avg_refs 12.666667 # Average number of references to valid blocks. |
| system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| system.cpu.dcache.tags.occ_blocks::cpu.data 82.896193 # Average occupied blocks per requestor |
| system.cpu.dcache.tags.occ_percent::cpu.data 0.020238 # Average percentage of cache occupancy |
| system.cpu.dcache.tags.occ_percent::total 0.020238 # Average percentage of cache occupancy |
| system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id |
| system.cpu.dcache.tags.age_task_id_blocks_1024::0 41 # Occupied blocks per task id |
| system.cpu.dcache.tags.age_task_id_blocks_1024::1 100 # Occupied blocks per task id |
| system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id |
| system.cpu.dcache.tags.tag_accesses 3995 # Number of tag accesses |
| system.cpu.dcache.tags.data_accesses 3995 # Number of data accesses |
| system.cpu.dcache.ReadReq_hits::cpu.data 894 # number of ReadReq hits |
| system.cpu.dcache.ReadReq_hits::total 894 # number of ReadReq hits |
| system.cpu.dcache.WriteReq_hits::cpu.data 870 # number of WriteReq hits |
| system.cpu.dcache.WriteReq_hits::total 870 # number of WriteReq hits |
| system.cpu.dcache.LoadLockedReq_hits::cpu.data 11 # number of LoadLockedReq hits |
| system.cpu.dcache.LoadLockedReq_hits::total 11 # number of LoadLockedReq hits |
| system.cpu.dcache.StoreCondReq_hits::cpu.data 11 # number of StoreCondReq hits |
| system.cpu.dcache.StoreCondReq_hits::total 11 # number of StoreCondReq hits |
| system.cpu.dcache.demand_hits::cpu.data 1764 # number of demand (read+write) hits |
| system.cpu.dcache.demand_hits::total 1764 # number of demand (read+write) hits |
| system.cpu.dcache.overall_hits::cpu.data 1764 # number of overall hits |
| system.cpu.dcache.overall_hits::total 1764 # number of overall hits |
| system.cpu.dcache.ReadReq_misses::cpu.data 98 # number of ReadReq misses |
| system.cpu.dcache.ReadReq_misses::total 98 # number of ReadReq misses |
| system.cpu.dcache.WriteReq_misses::cpu.data 43 # number of WriteReq misses |
| system.cpu.dcache.WriteReq_misses::total 43 # number of WriteReq misses |
| system.cpu.dcache.demand_misses::cpu.data 141 # number of demand (read+write) misses |
| system.cpu.dcache.demand_misses::total 141 # number of demand (read+write) misses |
| system.cpu.dcache.overall_misses::cpu.data 141 # number of overall misses |
| system.cpu.dcache.overall_misses::total 141 # number of overall misses |
| system.cpu.dcache.ReadReq_miss_latency::cpu.data 4718000 # number of ReadReq miss cycles |
| system.cpu.dcache.ReadReq_miss_latency::total 4718000 # number of ReadReq miss cycles |
| system.cpu.dcache.WriteReq_miss_latency::cpu.data 2365000 # number of WriteReq miss cycles |
| system.cpu.dcache.WriteReq_miss_latency::total 2365000 # number of WriteReq miss cycles |
| system.cpu.dcache.demand_miss_latency::cpu.data 7083000 # number of demand (read+write) miss cycles |
| system.cpu.dcache.demand_miss_latency::total 7083000 # number of demand (read+write) miss cycles |
| system.cpu.dcache.overall_miss_latency::cpu.data 7083000 # number of overall miss cycles |
| system.cpu.dcache.overall_miss_latency::total 7083000 # number of overall miss cycles |
| system.cpu.dcache.ReadReq_accesses::cpu.data 992 # number of ReadReq accesses(hits+misses) |
| system.cpu.dcache.ReadReq_accesses::total 992 # number of ReadReq accesses(hits+misses) |
| system.cpu.dcache.WriteReq_accesses::cpu.data 913 # number of WriteReq accesses(hits+misses) |
| system.cpu.dcache.WriteReq_accesses::total 913 # number of WriteReq accesses(hits+misses) |
| system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 # number of LoadLockedReq accesses(hits+misses) |
| system.cpu.dcache.LoadLockedReq_accesses::total 11 # number of LoadLockedReq accesses(hits+misses) |
| system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 # number of StoreCondReq accesses(hits+misses) |
| system.cpu.dcache.StoreCondReq_accesses::total 11 # number of StoreCondReq accesses(hits+misses) |
| system.cpu.dcache.demand_accesses::cpu.data 1905 # number of demand (read+write) accesses |
| system.cpu.dcache.demand_accesses::total 1905 # number of demand (read+write) accesses |
| system.cpu.dcache.overall_accesses::cpu.data 1905 # number of overall (read+write) accesses |
| system.cpu.dcache.overall_accesses::total 1905 # number of overall (read+write) accesses |
| system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.098790 # miss rate for ReadReq accesses |
| system.cpu.dcache.ReadReq_miss_rate::total 0.098790 # miss rate for ReadReq accesses |
| system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.047097 # miss rate for WriteReq accesses |
| system.cpu.dcache.WriteReq_miss_rate::total 0.047097 # miss rate for WriteReq accesses |
| system.cpu.dcache.demand_miss_rate::cpu.data 0.074016 # miss rate for demand accesses |
| system.cpu.dcache.demand_miss_rate::total 0.074016 # miss rate for demand accesses |
| system.cpu.dcache.overall_miss_rate::cpu.data 0.074016 # miss rate for overall accesses |
| system.cpu.dcache.overall_miss_rate::total 0.074016 # miss rate for overall accesses |
| system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 48142.857143 # average ReadReq miss latency |
| system.cpu.dcache.ReadReq_avg_miss_latency::total 48142.857143 # average ReadReq miss latency |
| system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency |
| system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency |
| system.cpu.dcache.demand_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency |
| system.cpu.dcache.demand_avg_miss_latency::total 50234.042553 # average overall miss latency |
| system.cpu.dcache.overall_avg_miss_latency::cpu.data 50234.042553 # average overall miss latency |
| system.cpu.dcache.overall_avg_miss_latency::total 50234.042553 # average overall miss latency |
| system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| system.cpu.dcache.fast_writes 0 # number of fast writes performed |
| system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| system.cpu.dcache.ReadReq_mshr_misses::cpu.data 98 # number of ReadReq MSHR misses |
| system.cpu.dcache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses |
| system.cpu.dcache.WriteReq_mshr_misses::cpu.data 43 # number of WriteReq MSHR misses |
| system.cpu.dcache.WriteReq_mshr_misses::total 43 # number of WriteReq MSHR misses |
| system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses |
| system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses |
| system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses |
| system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses |
| system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4571000 # number of ReadReq MSHR miss cycles |
| system.cpu.dcache.ReadReq_mshr_miss_latency::total 4571000 # number of ReadReq MSHR miss cycles |
| system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2300500 # number of WriteReq MSHR miss cycles |
| system.cpu.dcache.WriteReq_mshr_miss_latency::total 2300500 # number of WriteReq MSHR miss cycles |
| system.cpu.dcache.demand_mshr_miss_latency::cpu.data 6871500 # number of demand (read+write) MSHR miss cycles |
| system.cpu.dcache.demand_mshr_miss_latency::total 6871500 # number of demand (read+write) MSHR miss cycles |
| system.cpu.dcache.overall_mshr_miss_latency::cpu.data 6871500 # number of overall MSHR miss cycles |
| system.cpu.dcache.overall_mshr_miss_latency::total 6871500 # number of overall MSHR miss cycles |
| system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.098790 # mshr miss rate for ReadReq accesses |
| system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.098790 # mshr miss rate for ReadReq accesses |
| system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.047097 # mshr miss rate for WriteReq accesses |
| system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.047097 # mshr miss rate for WriteReq accesses |
| system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for demand accesses |
| system.cpu.dcache.demand_mshr_miss_rate::total 0.074016 # mshr miss rate for demand accesses |
| system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.074016 # mshr miss rate for overall accesses |
| system.cpu.dcache.overall_mshr_miss_rate::total 0.074016 # mshr miss rate for overall accesses |
| system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 46642.857143 # average ReadReq mshr miss latency |
| system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 46642.857143 # average ReadReq mshr miss latency |
| system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency |
| system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency |
| system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 48734.042553 # average overall mshr miss latency |
| system.cpu.dcache.demand_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency |
| system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 48734.042553 # average overall mshr miss latency |
| system.cpu.dcache.overall_avg_mshr_miss_latency::total 48734.042553 # average overall mshr miss latency |
| system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| system.cpu.icache.tags.replacements 1 # number of replacements |
| system.cpu.icache.tags.tagsinuse 114.417529 # Cycle average of tags in use |
| system.cpu.icache.tags.total_refs 4365 # Total number of references to valid blocks. |
| system.cpu.icache.tags.sampled_refs 241 # Sample count of references to valid blocks. |
| system.cpu.icache.tags.avg_refs 18.112033 # Average number of references to valid blocks. |
| system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| system.cpu.icache.tags.occ_blocks::cpu.inst 114.417529 # Average occupied blocks per requestor |
| system.cpu.icache.tags.occ_percent::cpu.inst 0.055868 # Average percentage of cache occupancy |
| system.cpu.icache.tags.occ_percent::total 0.055868 # Average percentage of cache occupancy |
| system.cpu.icache.tags.occ_task_id_blocks::1024 240 # Occupied blocks per task id |
| system.cpu.icache.tags.age_task_id_blocks_1024::0 107 # Occupied blocks per task id |
| system.cpu.icache.tags.age_task_id_blocks_1024::1 133 # Occupied blocks per task id |
| system.cpu.icache.tags.occ_task_id_percent::1024 0.117188 # Percentage of cache occupancy per task id |
| system.cpu.icache.tags.tag_accesses 9453 # Number of tag accesses |
| system.cpu.icache.tags.data_accesses 9453 # Number of data accesses |
| system.cpu.icache.ReadReq_hits::cpu.inst 4365 # number of ReadReq hits |
| system.cpu.icache.ReadReq_hits::total 4365 # number of ReadReq hits |
| system.cpu.icache.demand_hits::cpu.inst 4365 # number of demand (read+write) hits |
| system.cpu.icache.demand_hits::total 4365 # number of demand (read+write) hits |
| system.cpu.icache.overall_hits::cpu.inst 4365 # number of overall hits |
| system.cpu.icache.overall_hits::total 4365 # number of overall hits |
| system.cpu.icache.ReadReq_misses::cpu.inst 241 # number of ReadReq misses |
| system.cpu.icache.ReadReq_misses::total 241 # number of ReadReq misses |
| system.cpu.icache.demand_misses::cpu.inst 241 # number of demand (read+write) misses |
| system.cpu.icache.demand_misses::total 241 # number of demand (read+write) misses |
| system.cpu.icache.overall_misses::cpu.inst 241 # number of overall misses |
| system.cpu.icache.overall_misses::total 241 # number of overall misses |
| system.cpu.icache.ReadReq_miss_latency::cpu.inst 12588500 # number of ReadReq miss cycles |
| system.cpu.icache.ReadReq_miss_latency::total 12588500 # number of ReadReq miss cycles |
| system.cpu.icache.demand_miss_latency::cpu.inst 12588500 # number of demand (read+write) miss cycles |
| system.cpu.icache.demand_miss_latency::total 12588500 # number of demand (read+write) miss cycles |
| system.cpu.icache.overall_miss_latency::cpu.inst 12588500 # number of overall miss cycles |
| system.cpu.icache.overall_miss_latency::total 12588500 # number of overall miss cycles |
| system.cpu.icache.ReadReq_accesses::cpu.inst 4606 # number of ReadReq accesses(hits+misses) |
| system.cpu.icache.ReadReq_accesses::total 4606 # number of ReadReq accesses(hits+misses) |
| system.cpu.icache.demand_accesses::cpu.inst 4606 # number of demand (read+write) accesses |
| system.cpu.icache.demand_accesses::total 4606 # number of demand (read+write) accesses |
| system.cpu.icache.overall_accesses::cpu.inst 4606 # number of overall (read+write) accesses |
| system.cpu.icache.overall_accesses::total 4606 # number of overall (read+write) accesses |
| system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052323 # miss rate for ReadReq accesses |
| system.cpu.icache.ReadReq_miss_rate::total 0.052323 # miss rate for ReadReq accesses |
| system.cpu.icache.demand_miss_rate::cpu.inst 0.052323 # miss rate for demand accesses |
| system.cpu.icache.demand_miss_rate::total 0.052323 # miss rate for demand accesses |
| system.cpu.icache.overall_miss_rate::cpu.inst 0.052323 # miss rate for overall accesses |
| system.cpu.icache.overall_miss_rate::total 0.052323 # miss rate for overall accesses |
| system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 52234.439834 # average ReadReq miss latency |
| system.cpu.icache.ReadReq_avg_miss_latency::total 52234.439834 # average ReadReq miss latency |
| system.cpu.icache.demand_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency |
| system.cpu.icache.demand_avg_miss_latency::total 52234.439834 # average overall miss latency |
| system.cpu.icache.overall_avg_miss_latency::cpu.inst 52234.439834 # average overall miss latency |
| system.cpu.icache.overall_avg_miss_latency::total 52234.439834 # average overall miss latency |
| system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| system.cpu.icache.fast_writes 0 # number of fast writes performed |
| system.cpu.icache.cache_copies 0 # number of cache copies performed |
| system.cpu.icache.ReadReq_mshr_misses::cpu.inst 241 # number of ReadReq MSHR misses |
| system.cpu.icache.ReadReq_mshr_misses::total 241 # number of ReadReq MSHR misses |
| system.cpu.icache.demand_mshr_misses::cpu.inst 241 # number of demand (read+write) MSHR misses |
| system.cpu.icache.demand_mshr_misses::total 241 # number of demand (read+write) MSHR misses |
| system.cpu.icache.overall_mshr_misses::cpu.inst 241 # number of overall MSHR misses |
| system.cpu.icache.overall_mshr_misses::total 241 # number of overall MSHR misses |
| system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12227000 # number of ReadReq MSHR miss cycles |
| system.cpu.icache.ReadReq_mshr_miss_latency::total 12227000 # number of ReadReq MSHR miss cycles |
| system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12227000 # number of demand (read+write) MSHR miss cycles |
| system.cpu.icache.demand_mshr_miss_latency::total 12227000 # number of demand (read+write) MSHR miss cycles |
| system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12227000 # number of overall MSHR miss cycles |
| system.cpu.icache.overall_mshr_miss_latency::total 12227000 # number of overall MSHR miss cycles |
| system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for ReadReq accesses |
| system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052323 # mshr miss rate for ReadReq accesses |
| system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for demand accesses |
| system.cpu.icache.demand_mshr_miss_rate::total 0.052323 # mshr miss rate for demand accesses |
| system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052323 # mshr miss rate for overall accesses |
| system.cpu.icache.overall_mshr_miss_rate::total 0.052323 # mshr miss rate for overall accesses |
| system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50734.439834 # average ReadReq mshr miss latency |
| system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50734.439834 # average ReadReq mshr miss latency |
| system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency |
| system.cpu.icache.demand_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency |
| system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50734.439834 # average overall mshr miss latency |
| system.cpu.icache.overall_avg_mshr_miss_latency::total 50734.439834 # average overall mshr miss latency |
| system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| system.cpu.l2cache.tags.replacements 0 # number of replacements |
| system.cpu.l2cache.tags.tagsinuse 153.834298 # Cycle average of tags in use |
| system.cpu.l2cache.tags.total_refs 32 # Total number of references to valid blocks. |
| system.cpu.l2cache.tags.sampled_refs 307 # Sample count of references to valid blocks. |
| system.cpu.l2cache.tags.avg_refs 0.104235 # Average number of references to valid blocks. |
| system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| system.cpu.l2cache.tags.occ_blocks::cpu.inst 105.699770 # Average occupied blocks per requestor |
| system.cpu.l2cache.tags.occ_blocks::cpu.data 48.134528 # Average occupied blocks per requestor |
| system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003226 # Average percentage of cache occupancy |
| system.cpu.l2cache.tags.occ_percent::cpu.data 0.001469 # Average percentage of cache occupancy |
| system.cpu.l2cache.tags.occ_percent::total 0.004695 # Average percentage of cache occupancy |
| system.cpu.l2cache.tags.occ_task_id_blocks::1024 307 # Occupied blocks per task id |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::0 128 # Occupied blocks per task id |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::1 179 # Occupied blocks per task id |
| system.cpu.l2cache.tags.occ_task_id_percent::1024 0.009369 # Percentage of cache occupancy per task id |
| system.cpu.l2cache.tags.tag_accesses 3406 # Number of tag accesses |
| system.cpu.l2cache.tags.data_accesses 3406 # Number of data accesses |
| system.cpu.l2cache.ReadReq_hits::cpu.inst 16 # number of ReadReq hits |
| system.cpu.l2cache.ReadReq_hits::cpu.data 16 # number of ReadReq hits |
| system.cpu.l2cache.ReadReq_hits::total 32 # number of ReadReq hits |
| system.cpu.l2cache.demand_hits::cpu.inst 16 # number of demand (read+write) hits |
| system.cpu.l2cache.demand_hits::cpu.data 16 # number of demand (read+write) hits |
| system.cpu.l2cache.demand_hits::total 32 # number of demand (read+write) hits |
| system.cpu.l2cache.overall_hits::cpu.inst 16 # number of overall hits |
| system.cpu.l2cache.overall_hits::cpu.data 16 # number of overall hits |
| system.cpu.l2cache.overall_hits::total 32 # number of overall hits |
| system.cpu.l2cache.ReadReq_misses::cpu.inst 225 # number of ReadReq misses |
| system.cpu.l2cache.ReadReq_misses::cpu.data 82 # number of ReadReq misses |
| system.cpu.l2cache.ReadReq_misses::total 307 # number of ReadReq misses |
| system.cpu.l2cache.ReadExReq_misses::cpu.data 43 # number of ReadExReq misses |
| system.cpu.l2cache.ReadExReq_misses::total 43 # number of ReadExReq misses |
| system.cpu.l2cache.demand_misses::cpu.inst 225 # number of demand (read+write) misses |
| system.cpu.l2cache.demand_misses::cpu.data 125 # number of demand (read+write) misses |
| system.cpu.l2cache.demand_misses::total 350 # number of demand (read+write) misses |
| system.cpu.l2cache.overall_misses::cpu.inst 225 # number of overall misses |
| system.cpu.l2cache.overall_misses::cpu.data 125 # number of overall misses |
| system.cpu.l2cache.overall_misses::total 350 # number of overall misses |
| system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11818000 # number of ReadReq miss cycles |
| system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4305000 # number of ReadReq miss cycles |
| system.cpu.l2cache.ReadReq_miss_latency::total 16123000 # number of ReadReq miss cycles |
| system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2257500 # number of ReadExReq miss cycles |
| system.cpu.l2cache.ReadExReq_miss_latency::total 2257500 # number of ReadExReq miss cycles |
| system.cpu.l2cache.demand_miss_latency::cpu.inst 11818000 # number of demand (read+write) miss cycles |
| system.cpu.l2cache.demand_miss_latency::cpu.data 6562500 # number of demand (read+write) miss cycles |
| system.cpu.l2cache.demand_miss_latency::total 18380500 # number of demand (read+write) miss cycles |
| system.cpu.l2cache.overall_miss_latency::cpu.inst 11818000 # number of overall miss cycles |
| system.cpu.l2cache.overall_miss_latency::cpu.data 6562500 # number of overall miss cycles |
| system.cpu.l2cache.overall_miss_latency::total 18380500 # number of overall miss cycles |
| system.cpu.l2cache.ReadReq_accesses::cpu.inst 241 # number of ReadReq accesses(hits+misses) |
| system.cpu.l2cache.ReadReq_accesses::cpu.data 98 # number of ReadReq accesses(hits+misses) |
| system.cpu.l2cache.ReadReq_accesses::total 339 # number of ReadReq accesses(hits+misses) |
| system.cpu.l2cache.ReadExReq_accesses::cpu.data 43 # number of ReadExReq accesses(hits+misses) |
| system.cpu.l2cache.ReadExReq_accesses::total 43 # number of ReadExReq accesses(hits+misses) |
| system.cpu.l2cache.demand_accesses::cpu.inst 241 # number of demand (read+write) accesses |
| system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses |
| system.cpu.l2cache.demand_accesses::total 382 # number of demand (read+write) accesses |
| system.cpu.l2cache.overall_accesses::cpu.inst 241 # number of overall (read+write) accesses |
| system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses |
| system.cpu.l2cache.overall_accesses::total 382 # number of overall (read+write) accesses |
| system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.933610 # miss rate for ReadReq accesses |
| system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.836735 # miss rate for ReadReq accesses |
| system.cpu.l2cache.ReadReq_miss_rate::total 0.905605 # miss rate for ReadReq accesses |
| system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses |
| system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses |
| system.cpu.l2cache.demand_miss_rate::cpu.inst 0.933610 # miss rate for demand accesses |
| system.cpu.l2cache.demand_miss_rate::cpu.data 0.886525 # miss rate for demand accesses |
| system.cpu.l2cache.demand_miss_rate::total 0.916230 # miss rate for demand accesses |
| system.cpu.l2cache.overall_miss_rate::cpu.inst 0.933610 # miss rate for overall accesses |
| system.cpu.l2cache.overall_miss_rate::cpu.data 0.886525 # miss rate for overall accesses |
| system.cpu.l2cache.overall_miss_rate::total 0.916230 # miss rate for overall accesses |
| system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52524.444444 # average ReadReq miss latency |
| system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency |
| system.cpu.l2cache.ReadReq_avg_miss_latency::total 52517.915309 # average ReadReq miss latency |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency |
| system.cpu.l2cache.demand_avg_miss_latency::total 52515.714286 # average overall miss latency |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52524.444444 # average overall miss latency |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency |
| system.cpu.l2cache.overall_avg_miss_latency::total 52515.714286 # average overall miss latency |
| system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| system.cpu.l2cache.fast_writes 0 # number of fast writes performed |
| system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 225 # number of ReadReq MSHR misses |
| system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 82 # number of ReadReq MSHR misses |
| system.cpu.l2cache.ReadReq_mshr_misses::total 307 # number of ReadReq MSHR misses |
| system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 43 # number of ReadExReq MSHR misses |
| system.cpu.l2cache.ReadExReq_mshr_misses::total 43 # number of ReadExReq MSHR misses |
| system.cpu.l2cache.demand_mshr_misses::cpu.inst 225 # number of demand (read+write) MSHR misses |
| system.cpu.l2cache.demand_mshr_misses::cpu.data 125 # number of demand (read+write) MSHR misses |
| system.cpu.l2cache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses |
| system.cpu.l2cache.overall_mshr_misses::cpu.inst 225 # number of overall MSHR misses |
| system.cpu.l2cache.overall_mshr_misses::cpu.data 125 # number of overall MSHR misses |
| system.cpu.l2cache.overall_mshr_misses::total 350 # number of overall MSHR misses |
| system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 9112500 # number of ReadReq MSHR miss cycles |
| system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3321000 # number of ReadReq MSHR miss cycles |
| system.cpu.l2cache.ReadReq_mshr_miss_latency::total 12433500 # number of ReadReq MSHR miss cycles |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 1741500 # number of ReadExReq MSHR miss cycles |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1741500 # number of ReadExReq MSHR miss cycles |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 9112500 # number of demand (read+write) MSHR miss cycles |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5062500 # number of demand (read+write) MSHR miss cycles |
| system.cpu.l2cache.demand_mshr_miss_latency::total 14175000 # number of demand (read+write) MSHR miss cycles |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 9112500 # number of overall MSHR miss cycles |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5062500 # number of overall MSHR miss cycles |
| system.cpu.l2cache.overall_mshr_miss_latency::total 14175000 # number of overall MSHR miss cycles |
| system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for ReadReq accesses |
| system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.836735 # mshr miss rate for ReadReq accesses |
| system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.905605 # mshr miss rate for ReadReq accesses |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for demand accesses |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for demand accesses |
| system.cpu.l2cache.demand_mshr_miss_rate::total 0.916230 # mshr miss rate for demand accesses |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.933610 # mshr miss rate for overall accesses |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.886525 # mshr miss rate for overall accesses |
| system.cpu.l2cache.overall_mshr_miss_rate::total 0.916230 # mshr miss rate for overall accesses |
| system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency |
| system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency |
| system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency |
| system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| system.cpu.toL2Bus.trans_dist::ReadReq 339 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::ReadResp 339 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::ReadExReq 43 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::ReadExResp 43 # Transaction distribution |
| system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 482 # Packet count per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_count::total 764 # Packet count per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 15424 # Cumulative packet size per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_size::total 24448 # Cumulative packet size per connected master and slave (bytes) |
| system.cpu.toL2Bus.snoops 0 # Total snoops (count) |
| system.cpu.toL2Bus.snoop_fanout::samples 382 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::1 382 100.00% 100.00% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::total 382 # Request fanout histogram |
| system.cpu.toL2Bus.reqLayer0.occupancy 191000 # Layer occupancy (ticks) |
| system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) |
| system.cpu.toL2Bus.respLayer0.occupancy 361500 # Layer occupancy (ticks) |
| system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) |
| system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks) |
| system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%) |
| system.membus.trans_dist::ReadReq 307 # Transaction distribution |
| system.membus.trans_dist::ReadResp 307 # Transaction distribution |
| system.membus.trans_dist::ReadExReq 43 # Transaction distribution |
| system.membus.trans_dist::ReadExResp 43 # Transaction distribution |
| system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 700 # Packet count per connected master and slave (bytes) |
| system.membus.pkt_count::total 700 # Packet count per connected master and slave (bytes) |
| system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22400 # Cumulative packet size per connected master and slave (bytes) |
| system.membus.pkt_size::total 22400 # Cumulative packet size per connected master and slave (bytes) |
| system.membus.snoops 0 # Total snoops (count) |
| system.membus.snoop_fanout::samples 350 # Request fanout histogram |
| system.membus.snoop_fanout::mean 0 # Request fanout histogram |
| system.membus.snoop_fanout::stdev 0 # Request fanout histogram |
| system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| system.membus.snoop_fanout::0 350 100.00% 100.00% # Request fanout histogram |
| system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram |
| system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| system.membus.snoop_fanout::min_value 0 # Request fanout histogram |
| system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| system.membus.snoop_fanout::total 350 # Request fanout histogram |
| system.membus.reqLayer0.occupancy 355500 # Layer occupancy (ticks) |
| system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) |
| system.membus.respLayer1.occupancy 1755500 # Layer occupancy (ticks) |
| system.membus.respLayer1.utilization 6.8 # Layer utilization (%) |
| |
| ---------- End Simulation Statistics ---------- |
