arch, cpu: Remove float type accessors.
Use the binary accessors instead.
Change-Id: Iff1877e92c79df02b3d13635391a8c2f025776a2
Reviewed-on: https://gem5-review.googlesource.com/c/14457
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index ae8efa4..6a5d6af 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -88,7 +88,7 @@
// (no longer very clean due to the change in setIntReg() in the
// cpu model. Consider changing later.)
cpu->thread->setIntReg(ZeroReg, 0);
- cpu->thread->setFloatReg(ZeroReg, 0.0);
+ cpu->thread->setFloatRegBits(ZeroReg, 0);
}
////////////////////////////////////////////////////////////////////////
diff --git a/src/arch/arm/tracers/tarmac_record.cc b/src/arch/arm/tracers/tarmac_record.cc
index 7034d25..5dbb847 100644
--- a/src/arch/arm/tracers/tarmac_record.cc
+++ b/src/arch/arm/tracers/tarmac_record.cc
@@ -235,7 +235,7 @@
regValid = true;
regName = "f" + std::to_string(regRelIdx);
- valueLo = thread->readFloatReg(regRelIdx);
+ valueLo = bitsToFloat32(thread->readFloatRegBits(regRelIdx));
}
void
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index d30d54a..1dc7fc0 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -152,7 +152,7 @@
dest->setIntRegFlat(i, src->readIntRegFlat(i));
for (int i = 0; i < NumFloatRegs; i++)
- dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
+ dest->setFloatRegBitsFlat(i, src->readFloatRegBitsFlat(i));
for (int i = 0; i < NumVecRegs; i++)
dest->setVecRegFlat(i, src->readVecRegFlat(i));
diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index 2a9a8d8..c8163b7 100644
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -225,7 +225,7 @@
// (no longer very clean due to the change in setIntReg() in the
// cpu model. Consider changing later.)
cpu->thread->setIntReg(ZeroReg, 0);
- cpu->thread->setFloatReg(ZeroReg, 0.0);
+ cpu->thread->setFloatRegBits(ZeroReg, 0);
}
void
@@ -247,7 +247,7 @@
// Then loop through the floating point registers.
for (int i = 0; i < NumFloatRegs; i++)
- dest->setFloatRegFlat(i, src->readFloatRegFlat(i));
+ dest->setFloatRegBitsFlat(i, src->readFloatRegBitsFlat(i));
// Would need to add condition-code regs if implemented
assert(NumCCRegs == 0);
diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh
index b4431da..ae2911c 100644
--- a/src/cpu/base_dyn_inst.hh
+++ b/src/cpu/base_dyn_inst.hh
@@ -660,12 +660,6 @@
setScalarResult(val);
}
- /** Records an fp register being set to a value. */
- void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
- {
- setScalarResult(val);
- }
-
/** Record a vector register being set to a value */
void setVecRegOperand(const StaticInst *si, int idx,
const VecRegContainer& val)
diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index cb87f62..5673641 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -196,13 +196,6 @@
return thread->readIntReg(reg.index());
}
- FloatReg readFloatRegOperand(const StaticInst *si, int idx) override
- {
- const RegId& reg = si->srcRegIdx(idx);
- assert(reg.isFloatReg());
- return thread->readFloatReg(reg.index());
- }
-
FloatRegBits readFloatRegOperandBits(const StaticInst *si,
int idx) override
{
@@ -353,15 +346,6 @@
setScalarResult(val);
}
- void setFloatRegOperand(const StaticInst *si, int idx,
- FloatReg val) override
- {
- const RegId& reg = si->destRegIdx(idx);
- assert(reg.isFloatReg());
- thread->setFloatReg(reg.index(), val);
- setScalarResult(val);
- }
-
void setFloatRegOperandBits(const StaticInst *si, int idx,
FloatRegBits val) override
{
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 4fa5956..f6c3543 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -208,7 +208,7 @@
// maintain $r0 semantics
thread->setIntReg(ZeroReg, 0);
#if THE_ISA == ALPHA_ISA
- thread->setFloatReg(ZeroReg, 0.0);
+ thread->setFloatRegBits(ZeroReg, 0);
#endif
// Check if any recent PC changes match up with anything we
diff --git a/src/cpu/checker/thread_context.hh b/src/cpu/checker/thread_context.hh
index 975bd9f..85053df 100644
--- a/src/cpu/checker/thread_context.hh
+++ b/src/cpu/checker/thread_context.hh
@@ -209,9 +209,6 @@
uint64_t readIntReg(int reg_idx)
{ return actualTC->readIntReg(reg_idx); }
- FloatReg readFloatReg(int reg_idx)
- { return actualTC->readFloatReg(reg_idx); }
-
FloatRegBits readFloatRegBits(int reg_idx)
{ return actualTC->readFloatRegBits(reg_idx); }
@@ -273,12 +270,6 @@
checkerTC->setIntReg(reg_idx, val);
}
- void setFloatReg(int reg_idx, FloatReg val)
- {
- actualTC->setFloatReg(reg_idx, val);
- checkerTC->setFloatReg(reg_idx, val);
- }
-
void setFloatRegBits(int reg_idx, FloatRegBits val)
{
actualTC->setFloatRegBits(reg_idx, val);
@@ -382,12 +373,6 @@
void setIntRegFlat(int idx, uint64_t val)
{ actualTC->setIntRegFlat(idx, val); }
- FloatReg readFloatRegFlat(int idx)
- { return actualTC->readFloatRegFlat(idx); }
-
- void setFloatRegFlat(int idx, FloatReg val)
- { actualTC->setFloatRegFlat(idx, val); }
-
FloatRegBits readFloatRegBitsFlat(int idx)
{ return actualTC->readFloatRegBitsFlat(idx); }
diff --git a/src/cpu/exec_context.hh b/src/cpu/exec_context.hh
index bc9b486..89efe84 100644
--- a/src/cpu/exec_context.hh
+++ b/src/cpu/exec_context.hh
@@ -104,18 +104,11 @@
* @name Floating Point Register Interfaces
*/
- /** Reads a floating point register of single register width. */
- virtual FloatReg readFloatRegOperand(const StaticInst *si, int idx) = 0;
-
/** Reads a floating point register in its binary format, instead
* of by value. */
virtual FloatRegBits readFloatRegOperandBits(const StaticInst *si,
int idx) = 0;
- /** Sets a floating point register of single width to a value. */
- virtual void setFloatRegOperand(const StaticInst *si,
- int idx, FloatReg val) = 0;
-
/** Sets the bits of a floating point register of single width
* to a binary value. */
virtual void setFloatRegOperandBits(const StaticInst *si,
diff --git a/src/cpu/kvm/x86_cpu.cc b/src/cpu/kvm/x86_cpu.cc
index 012cccd..c7625bc 100644
--- a/src/cpu/kvm/x86_cpu.cc
+++ b/src/cpu/kvm/x86_cpu.cc
@@ -840,7 +840,8 @@
const unsigned top((fpu.fsw >> 11) & 0x7);
for (int i = 0; i < 8; ++i) {
const unsigned reg_idx((i + top) & 0x7);
- const double value(tc->readFloatReg(FLOATREG_FPR(reg_idx)));
+ const double value(bitsToFloat64(
+ tc->readFloatRegBits(FLOATREG_FPR(reg_idx))));
DPRINTF(KvmContext, "Setting KVM FP reg %i (st[%i]) := %f\n",
reg_idx, i, value);
X86ISA::storeFloat80(fpu.fpr[i], value);
@@ -1055,7 +1056,7 @@
const double value(X86ISA::loadFloat80(fpu.fpr[i]));
DPRINTF(KvmContext, "Setting gem5 FP reg %i (st[%i]) := %f\n",
reg_idx, i, value);
- tc->setFloatReg(FLOATREG_FPR(reg_idx), value);
+ tc->setFloatRegBits(FLOATREG_FPR(reg_idx), floatToBits64(value));
}
// TODO: We should update the MMX state
diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 238d113..19bae74 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -99,7 +99,7 @@
setPredicate(true);
thread.setIntReg(TheISA::ZeroReg, 0);
#if THE_ISA == ALPHA_ISA
- thread.setFloatReg(TheISA::ZeroReg, 0.0);
+ thread.setFloatRegBits(TheISA::ZeroReg, 0);
#endif
}
@@ -129,14 +129,6 @@
return thread.readIntReg(reg.index());
}
- TheISA::FloatReg
- readFloatRegOperand(const StaticInst *si, int idx) override
- {
- const RegId& reg = si->srcRegIdx(idx);
- assert(reg.isFloatReg());
- return thread.readFloatReg(reg.index());
- }
-
TheISA::FloatRegBits
readFloatRegOperandBits(const StaticInst *si, int idx) override
{
@@ -178,15 +170,6 @@
}
void
- setFloatRegOperand(const StaticInst *si, int idx,
- TheISA::FloatReg val) override
- {
- const RegId& reg = si->destRegIdx(idx);
- assert(reg.isFloatReg());
- thread.setFloatReg(reg.index(), val);
- }
-
- void
setFloatRegOperandBits(const StaticInst *si, int idx,
TheISA::FloatRegBits val) override
{
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 2f79345..e5b8103 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1284,14 +1284,6 @@
}
template <class Impl>
-FloatReg
-FullO3CPU<Impl>::readFloatReg(PhysRegIdPtr phys_reg)
-{
- fpRegfileReads++;
- return regFile.readFloatReg(phys_reg);
-}
-
-template <class Impl>
FloatRegBits
FullO3CPU<Impl>::readFloatRegBits(PhysRegIdPtr phys_reg)
{
@@ -1343,14 +1335,6 @@
template <class Impl>
void
-FullO3CPU<Impl>::setFloatReg(PhysRegIdPtr phys_reg, FloatReg val)
-{
- fpRegfileWrites++;
- regFile.setFloatReg(phys_reg, val);
-}
-
-template <class Impl>
-void
FullO3CPU<Impl>::setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val)
{
fpRegfileWrites++;
@@ -1393,19 +1377,8 @@
}
template <class Impl>
-float
-FullO3CPU<Impl>::readArchFloatReg(int reg_idx, ThreadID tid)
-{
- fpRegfileReads++;
- PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
- RegId(FloatRegClass, reg_idx));
-
- return regFile.readFloatReg(phys_reg);
-}
-
-template <class Impl>
uint64_t
-FullO3CPU<Impl>::readArchFloatRegInt(int reg_idx, ThreadID tid)
+FullO3CPU<Impl>::readArchFloatRegBits(int reg_idx, ThreadID tid)
{
fpRegfileReads++;
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
@@ -1468,18 +1441,7 @@
template <class Impl>
void
-FullO3CPU<Impl>::setArchFloatReg(int reg_idx, float val, ThreadID tid)
-{
- fpRegfileWrites++;
- PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
- RegId(FloatRegClass, reg_idx));
-
- regFile.setFloatReg(phys_reg, val);
-}
-
-template <class Impl>
-void
-FullO3CPU<Impl>::setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid)
+FullO3CPU<Impl>::setArchFloatRegBits(int reg_idx, uint64_t val, ThreadID tid)
{
fpRegfileWrites++;
PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 19b9a34..4c46776 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -401,8 +401,6 @@
uint64_t readIntReg(PhysRegIdPtr phys_reg);
- TheISA::FloatReg readFloatReg(PhysRegIdPtr phys_reg);
-
TheISA::FloatRegBits readFloatRegBits(PhysRegIdPtr phys_reg);
const VecRegContainer& readVecReg(PhysRegIdPtr reg_idx) const;
@@ -449,8 +447,6 @@
void setIntReg(PhysRegIdPtr phys_reg, uint64_t val);
- void setFloatReg(PhysRegIdPtr phys_reg, TheISA::FloatReg val);
-
void setFloatRegBits(PhysRegIdPtr phys_reg, TheISA::FloatRegBits val);
void setVecReg(PhysRegIdPtr reg_idx, const VecRegContainer& val);
@@ -461,9 +457,7 @@
uint64_t readArchIntReg(int reg_idx, ThreadID tid);
- float readArchFloatReg(int reg_idx, ThreadID tid);
-
- uint64_t readArchFloatRegInt(int reg_idx, ThreadID tid);
+ uint64_t readArchFloatRegBits(int reg_idx, ThreadID tid);
const VecRegContainer& readArchVecReg(int reg_idx, ThreadID tid) const;
/** Read architectural vector register for modification. */
@@ -502,9 +496,7 @@
*/
void setArchIntReg(int reg_idx, uint64_t val, ThreadID tid);
- void setArchFloatReg(int reg_idx, float val, ThreadID tid);
-
- void setArchFloatRegInt(int reg_idx, uint64_t val, ThreadID tid);
+ void setArchFloatRegBits(int reg_idx, uint64_t val, ThreadID tid);
void setArchVecReg(int reg_idx, const VecRegContainer& val, ThreadID tid);
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 47dc830..d4fbc78 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -273,11 +273,6 @@
return this->cpu->readIntReg(this->_srcRegIdx[idx]);
}
- FloatReg readFloatRegOperand(const StaticInst *si, int idx)
- {
- return this->cpu->readFloatReg(this->_srcRegIdx[idx]);
- }
-
FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
{
return this->cpu->readFloatRegBits(this->_srcRegIdx[idx]);
@@ -380,12 +375,6 @@
BaseDynInst<Impl>::setIntRegOperand(si, idx, val);
}
- void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
- {
- this->cpu->setFloatReg(this->_destRegIdx[idx], val);
- BaseDynInst<Impl>::setFloatRegOperand(si, idx, val);
- }
-
void setFloatRegOperandBits(const StaticInst *si, int idx,
FloatRegBits val)
{
diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh
index 7feec93..2f87421 100644
--- a/src/cpu/o3/regfile.hh
+++ b/src/cpu/o3/regfile.hh
@@ -187,18 +187,6 @@
return intRegFile[phys_reg->index()];
}
- /** Reads a floating point register (double precision). */
- FloatReg readFloatReg(PhysRegIdPtr phys_reg) const
- {
- assert(phys_reg->isFloatPhysReg());
-
- DPRINTF(IEW, "RegFile: Access to float register %i, has "
- "data %#x\n", phys_reg->index(),
- floatRegFile[phys_reg->index()].q);
-
- return floatRegFile[phys_reg->index()].d;
- }
-
FloatRegBits readFloatRegBits(PhysRegIdPtr phys_reg) const
{
assert(phys_reg->isFloatPhysReg());
@@ -298,18 +286,6 @@
intRegFile[phys_reg->index()] = val;
}
- /** Sets a double precision floating point register to the given value. */
- void setFloatReg(PhysRegIdPtr phys_reg, FloatReg val)
- {
- assert(phys_reg->isFloatPhysReg());
-
- DPRINTF(IEW, "RegFile: Setting float register %i to %#x\n",
- phys_reg->index(), (uint64_t)val);
-
- if (!phys_reg->isZeroReg())
- floatRegFile[phys_reg->index()].d = val;
- }
-
void setFloatRegBits(PhysRegIdPtr phys_reg, FloatRegBits val)
{
assert(phys_reg->isFloatPhysReg());
diff --git a/src/cpu/o3/thread_context.hh b/src/cpu/o3/thread_context.hh
index 2256a8a..1fbf565 100644
--- a/src/cpu/o3/thread_context.hh
+++ b/src/cpu/o3/thread_context.hh
@@ -184,11 +184,6 @@
reg_idx)).index());
}
- virtual FloatReg readFloatReg(int reg_idx) {
- return readFloatRegFlat(flattenRegId(RegId(FloatRegClass,
- reg_idx)).index());
- }
-
virtual FloatRegBits readFloatRegBits(int reg_idx) {
return readFloatRegBitsFlat(flattenRegId(RegId(FloatRegClass,
reg_idx)).index());
@@ -268,11 +263,6 @@
setIntRegFlat(flattenRegId(RegId(IntRegClass, reg_idx)).index(), val);
}
- virtual void setFloatReg(int reg_idx, FloatReg val) {
- setFloatRegFlat(flattenRegId(RegId(FloatRegClass,
- reg_idx)).index(), val);
- }
-
virtual void setFloatRegBits(int reg_idx, FloatRegBits val) {
setFloatRegBitsFlat(flattenRegId(RegId(FloatRegClass,
reg_idx)).index(), val);
@@ -364,9 +354,6 @@
virtual uint64_t readIntRegFlat(int idx);
virtual void setIntRegFlat(int idx, uint64_t val);
- virtual FloatReg readFloatRegFlat(int idx);
- virtual void setFloatRegFlat(int idx, FloatReg val);
-
virtual FloatRegBits readFloatRegBitsFlat(int idx);
virtual void setFloatRegBitsFlat(int idx, FloatRegBits val);
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index d9f84fb..f4b5cb4 100644
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -200,17 +200,10 @@
}
template <class Impl>
-TheISA::FloatReg
-O3ThreadContext<Impl>::readFloatRegFlat(int reg_idx)
-{
- return cpu->readArchFloatReg(reg_idx, thread->threadId());
-}
-
-template <class Impl>
TheISA::FloatRegBits
O3ThreadContext<Impl>::readFloatRegBitsFlat(int reg_idx)
{
- return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
+ return cpu->readArchFloatRegBits(reg_idx, thread->threadId());
}
template <class Impl>
@@ -253,18 +246,9 @@
template <class Impl>
void
-O3ThreadContext<Impl>::setFloatRegFlat(int reg_idx, FloatReg val)
-{
- cpu->setArchFloatReg(reg_idx, val, thread->threadId());
-
- conditionalSquash();
-}
-
-template <class Impl>
-void
O3ThreadContext<Impl>::setFloatRegBitsFlat(int reg_idx, FloatRegBits val)
{
- cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
+ cpu->setArchFloatRegBits(reg_idx, val, thread->threadId());
conditionalSquash();
}
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 825d310..c597ac9 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -493,7 +493,7 @@
// maintain $r0 semantics
thread->setIntReg(ZeroReg, 0);
#if THE_ISA == ALPHA_ISA
- thread->setFloatReg(ZeroReg, 0.0);
+ thread->setFloatRegBits(ZeroReg, 0);
#endif // ALPHA_ISA
// check for instruction-count-based events
diff --git a/src/cpu/simple/exec_context.hh b/src/cpu/simple/exec_context.hh
index 8ff18dd..1aababf 100644
--- a/src/cpu/simple/exec_context.hh
+++ b/src/cpu/simple/exec_context.hh
@@ -191,15 +191,6 @@
thread->setIntReg(reg.index(), val);
}
- /** Reads a floating point register of single register width. */
- FloatReg readFloatRegOperand(const StaticInst *si, int idx) override
- {
- numFpRegReads++;
- const RegId& reg = si->srcRegIdx(idx);
- assert(reg.isFloatReg());
- return thread->readFloatReg(reg.index());
- }
-
/** Reads a floating point register in its binary format, instead
* of by value. */
FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx) override
@@ -210,16 +201,6 @@
return thread->readFloatRegBits(reg.index());
}
- /** Sets a floating point register of single width to a value. */
- void setFloatRegOperand(const StaticInst *si, int idx,
- FloatReg val) override
- {
- numFpRegWrites++;
- const RegId& reg = si->destRegIdx(idx);
- assert(reg.isFloatReg());
- thread->setFloatReg(reg.index(), val);
- }
-
/** Sets the bits of a floating point register of single width
* to a binary value. */
void setFloatRegOperandBits(const StaticInst *si, int idx,
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 3c64082..601aa7c 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -253,16 +253,6 @@
return regVal;
}
- FloatReg readFloatReg(int reg_idx)
- {
- int flatIndex = isa->flattenFloatIndex(reg_idx);
- assert(flatIndex < TheISA::NumFloatRegs);
- FloatReg regVal(readFloatRegFlat(flatIndex));
- DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n",
- reg_idx, flatIndex, regVal, floatRegs.i[flatIndex]);
- return regVal;
- }
-
FloatRegBits readFloatRegBits(int reg_idx)
{
int flatIndex = isa->flattenFloatIndex(reg_idx);
@@ -390,15 +380,6 @@
setIntRegFlat(flatIndex, val);
}
- void setFloatReg(int reg_idx, FloatReg val)
- {
- int flatIndex = isa->flattenFloatIndex(reg_idx);
- assert(flatIndex < TheISA::NumFloatRegs);
- setFloatRegFlat(flatIndex, val);
- DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n",
- reg_idx, flatIndex, val, floatRegs.i[flatIndex]);
- }
-
void setFloatRegBits(int reg_idx, FloatRegBits val)
{
int flatIndex = isa->flattenFloatIndex(reg_idx);
@@ -537,9 +518,6 @@
uint64_t readIntRegFlat(int idx) { return intRegs[idx]; }
void setIntRegFlat(int idx, uint64_t val) { intRegs[idx] = val; }
- FloatReg readFloatRegFlat(int idx) { return floatRegs.f[idx]; }
- void setFloatRegFlat(int idx, FloatReg val) { floatRegs.f[idx] = val; }
-
FloatRegBits readFloatRegBitsFlat(int idx) { return floatRegs.i[idx]; }
void setFloatRegBitsFlat(int idx, FloatRegBits val) {
floatRegs.i[idx] = val;
diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh
index 1e30649..f9dfd83 100644
--- a/src/cpu/thread_context.hh
+++ b/src/cpu/thread_context.hh
@@ -210,8 +210,6 @@
//
virtual uint64_t readIntReg(int reg_idx) = 0;
- virtual FloatReg readFloatReg(int reg_idx) = 0;
-
virtual FloatRegBits readFloatRegBits(int reg_idx) = 0;
virtual const VecRegContainer& readVecReg(const RegId& reg) const = 0;
@@ -252,8 +250,6 @@
virtual void setIntReg(int reg_idx, uint64_t val) = 0;
- virtual void setFloatReg(int reg_idx, FloatReg val) = 0;
-
virtual void setFloatRegBits(int reg_idx, FloatRegBits val) = 0;
virtual void setVecReg(const RegId& reg, const VecRegContainer& val) = 0;
@@ -337,9 +333,6 @@
virtual uint64_t readIntRegFlat(int idx) = 0;
virtual void setIntRegFlat(int idx, uint64_t val) = 0;
- virtual FloatReg readFloatRegFlat(int idx) = 0;
- virtual void setFloatRegFlat(int idx, FloatReg val) = 0;
-
virtual FloatRegBits readFloatRegBitsFlat(int idx) = 0;
virtual void setFloatRegBitsFlat(int idx, FloatRegBits val) = 0;
@@ -464,9 +457,6 @@
uint64_t readIntReg(int reg_idx)
{ return actualTC->readIntReg(reg_idx); }
- FloatReg readFloatReg(int reg_idx)
- { return actualTC->readFloatReg(reg_idx); }
-
FloatRegBits readFloatRegBits(int reg_idx)
{ return actualTC->readFloatRegBits(reg_idx); }
@@ -522,9 +512,6 @@
void setIntReg(int reg_idx, uint64_t val)
{ actualTC->setIntReg(reg_idx, val); }
- void setFloatReg(int reg_idx, FloatReg val)
- { actualTC->setFloatReg(reg_idx, val); }
-
void setFloatRegBits(int reg_idx, FloatRegBits val)
{ actualTC->setFloatRegBits(reg_idx, val); }
@@ -584,12 +571,6 @@
void setIntRegFlat(int idx, uint64_t val)
{ actualTC->setIntRegFlat(idx, val); }
- FloatReg readFloatRegFlat(int idx)
- { return actualTC->readFloatRegFlat(idx); }
-
- void setFloatRegFlat(int idx, FloatReg val)
- { actualTC->setFloatRegFlat(idx, val); }
-
FloatRegBits readFloatRegBitsFlat(int idx)
{ return actualTC->readFloatRegBitsFlat(idx); }
