misc: minor fix for the gem5-SystemC/TLM coupling.

This patch has a minor fix for the coupling between gem5 and SystemC-TLM.

It also fixes some typos in the related documentation.

Change-Id: I894568729b8ebdacc5b81c9f46e8f9d137da210f
Reviewed-on: https://gem5-review.googlesource.com/2480
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
diff --git a/util/systemc/.gitignore b/util/systemc/.gitignore
new file mode 100644
index 0000000..5761abc
--- /dev/null
+++ b/util/systemc/.gitignore
@@ -0,0 +1 @@
+*.o
diff --git a/util/tlm/.gitignore b/util/tlm/.gitignore
new file mode 100644
index 0000000..5761abc
--- /dev/null
+++ b/util/tlm/.gitignore
@@ -0,0 +1 @@
+*.o
diff --git a/util/tlm/README b/util/tlm/README
index 7eeafa7..bcaec69 100644
--- a/util/tlm/README
+++ b/util/tlm/README
@@ -29,11 +29,11 @@
 Gem5SlaveTransactor is a SystemC module that provides a initiator socket and
 represents the TLM end of the bridge. SCSlavePort implements gem5's
 ExternalSlave::Port interface and forms the gem5 side of the bridge. All gem5
-requests send to the SCSlavePort, are translated to TLM requests and forwarded
+requests sent to the SCSlavePort, are translated to TLM requests and forwarded
 to the TLM world through the initiator socket of the Gem5SlaveTransactor. Then
 the TLM world handles the request and eventually issues a response. When the
-response arrives at the Gem5SlaveTransactor it gets translated back into a TLM
-response and forwarded to the gem5 world through the SCSlavePort.  SCSLavePort
+response arrives at the Gem5SlaveTransactor it gets translated back into a
+gem5 response and forwarded to the gem5 world through the SCSlavePort. SCSLavePort
 and Gem5SlaveTransactor are bound to each other by configuring them for the
 same port name.
 
diff --git a/util/tlm/examples/slave_port/tlm_elastic.py b/util/tlm/examples/slave_port/tlm_elastic.py
index 3de0670..8930e2e 100644
--- a/util/tlm/examples/slave_port/tlm_elastic.py
+++ b/util/tlm/examples/slave_port/tlm_elastic.py
@@ -36,7 +36,7 @@
 from m5.objects import *
 from m5.util import addToPath, fatal
 
-addToPath('../../configs/common/')
+addToPath('../../../../configs/common/')
 
 from Caches import *