src/arch/riscv/isa/micro.isa

// -*- mode:c++ -*-

// Copyright (c) 2015 Riscv Developers
// Copyright (c) 2016 The University of Virginia
// All rights reserved.
//
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// modification, are permitted provided that the following conditions are
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// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// Authors: Alec Roelke

def template MacroInitiateAcc {{
    Fault initiateAcc(%(CPU_exec_context)s *xc,
        Trace::InstRecord *traceData) const
    {
        panic("Tried to execute a macroop directly!\n");
        return NoFault;
    }
}};

def template MacroCompleteAcc {{
    Fault completeAcc(PacketPtr pkt, %(CPU_exec_context)s *xc,
        Trace::InstRecord *traceData) const
    {
        panic("Tried to execute a macroop directly!\n");
        return NoFault;
    }
}};

def template MacroExecute {{
    Fault execute(%(CPU_exec_context)s *xc, Trace::InstRecord *traceData) const
    {
        panic("Tried to execute a macroop directly!\n");
        return NoFault;
    }
}};

output header {{
    /**
     * Base class for all RISC-V Macroops
     */
    class RiscvMacroInst : public RiscvStaticInst
    {
    protected:
        std::vector<StaticInstPtr> microops;

        // Constructor
        RiscvMacroInst(const char *mnem, ExtMachInst _machInst,
            OpClass __opClass)
                : RiscvStaticInst(mnem, _machInst, __opClass)
        {
            flags[IsMacroop] = true;
        }

        ~RiscvMacroInst()
        {
            microops.clear();
        }

        StaticInstPtr fetchMicroop(MicroPC upc) const
        {
            return microops[upc];
        }

        %(MacroInitiateAcc)s

        %(MacroCompleteAcc)s

        %(MacroExecute)s
    };

    /**
     * Base class for all RISC-V Microops
     */
    class RiscvMicroInst : public RiscvStaticInst
    {
    protected:
        // Constructor
        RiscvMicroInst(const char *mnem, ExtMachInst _machInst,
            OpClass __opClass)
                : RiscvStaticInst(mnem, _machInst, __opClass)
        {
            flags[IsMicroop] = true;
        }

        void advancePC(RiscvISA::PCState &pcState) const
        {
            if (flags[IsLastMicroop]) {
                pcState.uEnd();
            } else {
                pcState.uAdvance();
            }
        }
    };
}};