| |
| ---------- Begin Simulation Statistics ---------- |
| sim_seconds 0.000020 |
| sim_ticks 20302000 |
| final_tick 20302000 |
| sim_freq 1000000000000 |
| host_inst_rate 45535 |
| host_op_rate 53318 |
| host_tick_rate 201173118 |
| host_mem_usage 277864 |
| host_seconds 0.10 |
| sim_insts 4592 |
| sim_ops 5378 |
| system.voltage_domain.voltage 1 |
| system.clk_domain.clock 1000 |
| system.physmem.pwrStateResidencyTicks::UNDEFINED 20302000 |
| system.physmem.bytes_read::cpu.inst 18560 |
| system.physmem.bytes_read::cpu.data 8128 |
| system.physmem.bytes_read::cpu.l2cache.prefetcher 1728 |
| system.physmem.bytes_read::total 28416 |
| system.physmem.bytes_inst_read::cpu.inst 18560 |
| system.physmem.bytes_inst_read::total 18560 |
| system.physmem.num_reads::cpu.inst 290 |
| system.physmem.num_reads::cpu.data 127 |
| system.physmem.num_reads::cpu.l2cache.prefetcher 27 |
| system.physmem.num_reads::total 444 |
| system.physmem.bw_read::cpu.inst 914195646 |
| system.physmem.bw_read::cpu.data 400354645 |
| system.physmem.bw_read::cpu.l2cache.prefetcher 85114767 |
| system.physmem.bw_read::total 1399665058 |
| system.physmem.bw_inst_read::cpu.inst 914195646 |
| system.physmem.bw_inst_read::total 914195646 |
| system.physmem.bw_total::cpu.inst 914195646 |
| system.physmem.bw_total::cpu.data 400354645 |
| system.physmem.bw_total::cpu.l2cache.prefetcher 85114767 |
| system.physmem.bw_total::total 1399665058 |
| system.physmem.readReqs 445 |
| system.physmem.writeReqs 0 |
| system.physmem.readBursts 445 |
| system.physmem.writeBursts 0 |
| system.physmem.bytesReadDRAM 28480 |
| system.physmem.bytesReadWrQ 0 |
| system.physmem.bytesWritten 0 |
| system.physmem.bytesReadSys 28480 |
| system.physmem.bytesWrittenSys 0 |
| system.physmem.servicedByWrQ 0 |
| system.physmem.mergedWrBursts 0 |
| system.physmem.neitherReadNorWriteReqs 0 |
| system.physmem.perBankRdBursts::0 103 |
| system.physmem.perBankRdBursts::1 48 |
| system.physmem.perBankRdBursts::2 19 |
| system.physmem.perBankRdBursts::3 45 |
| system.physmem.perBankRdBursts::4 19 |
| system.physmem.perBankRdBursts::5 37 |
| system.physmem.perBankRdBursts::6 46 |
| system.physmem.perBankRdBursts::7 10 |
| system.physmem.perBankRdBursts::8 4 |
| system.physmem.perBankRdBursts::9 8 |
| system.physmem.perBankRdBursts::10 27 |
| system.physmem.perBankRdBursts::11 47 |
| system.physmem.perBankRdBursts::12 17 |
| system.physmem.perBankRdBursts::13 8 |
| system.physmem.perBankRdBursts::14 0 |
| system.physmem.perBankRdBursts::15 7 |
| system.physmem.perBankWrBursts::0 0 |
| system.physmem.perBankWrBursts::1 0 |
| system.physmem.perBankWrBursts::2 0 |
| system.physmem.perBankWrBursts::3 0 |
| system.physmem.perBankWrBursts::4 0 |
| system.physmem.perBankWrBursts::5 0 |
| system.physmem.perBankWrBursts::6 0 |
| system.physmem.perBankWrBursts::7 0 |
| system.physmem.perBankWrBursts::8 0 |
| system.physmem.perBankWrBursts::9 0 |
| system.physmem.perBankWrBursts::10 0 |
| system.physmem.perBankWrBursts::11 0 |
| system.physmem.perBankWrBursts::12 0 |
| system.physmem.perBankWrBursts::13 0 |
| system.physmem.perBankWrBursts::14 0 |
| system.physmem.perBankWrBursts::15 0 |
| system.physmem.numRdRetry 0 |
| system.physmem.numWrRetry 0 |
| system.physmem.totGap 20260500 |
| system.physmem.readPktSize::0 0 |
| system.physmem.readPktSize::1 0 |
| system.physmem.readPktSize::2 0 |
| system.physmem.readPktSize::3 0 |
| system.physmem.readPktSize::4 0 |
| system.physmem.readPktSize::5 0 |
| system.physmem.readPktSize::6 445 |
| system.physmem.writePktSize::0 0 |
| system.physmem.writePktSize::1 0 |
| system.physmem.writePktSize::2 0 |
| system.physmem.writePktSize::3 0 |
| system.physmem.writePktSize::4 0 |
| system.physmem.writePktSize::5 0 |
| system.physmem.writePktSize::6 0 |
| system.physmem.rdQLenPdf::0 241 |
| system.physmem.rdQLenPdf::1 136 |
| system.physmem.rdQLenPdf::2 36 |
| system.physmem.rdQLenPdf::3 17 |
| system.physmem.rdQLenPdf::4 5 |
| system.physmem.rdQLenPdf::5 2 |
| system.physmem.rdQLenPdf::6 2 |
| system.physmem.rdQLenPdf::7 2 |
| system.physmem.rdQLenPdf::8 2 |
| system.physmem.rdQLenPdf::9 2 |
| system.physmem.rdQLenPdf::10 0 |
| system.physmem.rdQLenPdf::11 0 |
| system.physmem.rdQLenPdf::12 0 |
| system.physmem.rdQLenPdf::13 0 |
| system.physmem.rdQLenPdf::14 0 |
| system.physmem.rdQLenPdf::15 0 |
| system.physmem.rdQLenPdf::16 0 |
| system.physmem.rdQLenPdf::17 0 |
| system.physmem.rdQLenPdf::18 0 |
| system.physmem.rdQLenPdf::19 0 |
| system.physmem.rdQLenPdf::20 0 |
| system.physmem.rdQLenPdf::21 0 |
| system.physmem.rdQLenPdf::22 0 |
| system.physmem.rdQLenPdf::23 0 |
| system.physmem.rdQLenPdf::24 0 |
| system.physmem.rdQLenPdf::25 0 |
| system.physmem.rdQLenPdf::26 0 |
| system.physmem.rdQLenPdf::27 0 |
| system.physmem.rdQLenPdf::28 0 |
| system.physmem.rdQLenPdf::29 0 |
| system.physmem.rdQLenPdf::30 0 |
| system.physmem.rdQLenPdf::31 0 |
| system.physmem.wrQLenPdf::0 0 |
| system.physmem.wrQLenPdf::1 0 |
| system.physmem.wrQLenPdf::2 0 |
| system.physmem.wrQLenPdf::3 0 |
| system.physmem.wrQLenPdf::4 0 |
| system.physmem.wrQLenPdf::5 0 |
| system.physmem.wrQLenPdf::6 0 |
| system.physmem.wrQLenPdf::7 0 |
| system.physmem.wrQLenPdf::8 0 |
| system.physmem.wrQLenPdf::9 0 |
| system.physmem.wrQLenPdf::10 0 |
| system.physmem.wrQLenPdf::11 0 |
| system.physmem.wrQLenPdf::12 0 |
| system.physmem.wrQLenPdf::13 0 |
| system.physmem.wrQLenPdf::14 0 |
| system.physmem.wrQLenPdf::15 0 |
| system.physmem.wrQLenPdf::16 0 |
| system.physmem.wrQLenPdf::17 0 |
| system.physmem.wrQLenPdf::18 0 |
| system.physmem.wrQLenPdf::19 0 |
| system.physmem.wrQLenPdf::20 0 |
| system.physmem.wrQLenPdf::21 0 |
| system.physmem.wrQLenPdf::22 0 |
| system.physmem.wrQLenPdf::23 0 |
| system.physmem.wrQLenPdf::24 0 |
| system.physmem.wrQLenPdf::25 0 |
| system.physmem.wrQLenPdf::26 0 |
| system.physmem.wrQLenPdf::27 0 |
| system.physmem.wrQLenPdf::28 0 |
| system.physmem.wrQLenPdf::29 0 |
| system.physmem.wrQLenPdf::30 0 |
| system.physmem.wrQLenPdf::31 0 |
| system.physmem.wrQLenPdf::32 0 |
| system.physmem.wrQLenPdf::33 0 |
| system.physmem.wrQLenPdf::34 0 |
| system.physmem.wrQLenPdf::35 0 |
| system.physmem.wrQLenPdf::36 0 |
| system.physmem.wrQLenPdf::37 0 |
| system.physmem.wrQLenPdf::38 0 |
| system.physmem.wrQLenPdf::39 0 |
| system.physmem.wrQLenPdf::40 0 |
| system.physmem.wrQLenPdf::41 0 |
| system.physmem.wrQLenPdf::42 0 |
| system.physmem.wrQLenPdf::43 0 |
| system.physmem.wrQLenPdf::44 0 |
| system.physmem.wrQLenPdf::45 0 |
| system.physmem.wrQLenPdf::46 0 |
| system.physmem.wrQLenPdf::47 0 |
| system.physmem.wrQLenPdf::48 0 |
| system.physmem.wrQLenPdf::49 0 |
| system.physmem.wrQLenPdf::50 0 |
| system.physmem.wrQLenPdf::51 0 |
| system.physmem.wrQLenPdf::52 0 |
| system.physmem.wrQLenPdf::53 0 |
| system.physmem.wrQLenPdf::54 0 |
| system.physmem.wrQLenPdf::55 0 |
| system.physmem.wrQLenPdf::56 0 |
| system.physmem.wrQLenPdf::57 0 |
| system.physmem.wrQLenPdf::58 0 |
| system.physmem.wrQLenPdf::59 0 |
| system.physmem.wrQLenPdf::60 0 |
| system.physmem.wrQLenPdf::61 0 |
| system.physmem.wrQLenPdf::62 0 |
| system.physmem.wrQLenPdf::63 0 |
| system.physmem.bytesPerActivate::samples 62 |
| system.physmem.bytesPerActivate::mean 435.612903 |
| system.physmem.bytesPerActivate::gmean 295.844737 |
| system.physmem.bytesPerActivate::stdev 352.802892 |
| system.physmem.bytesPerActivate::0-127 8 12.90% 12.90% |
| system.physmem.bytesPerActivate::128-255 16 25.81% 38.71% |
| system.physmem.bytesPerActivate::256-383 10 16.13% 54.84% |
| system.physmem.bytesPerActivate::384-511 7 11.29% 66.13% |
| system.physmem.bytesPerActivate::512-639 2 3.23% 69.35% |
| system.physmem.bytesPerActivate::640-767 3 4.84% 74.19% |
| system.physmem.bytesPerActivate::768-895 2 3.23% 77.42% |
| system.physmem.bytesPerActivate::896-1023 4 6.45% 83.87% |
| system.physmem.bytesPerActivate::1024-1151 10 16.13% 100.00% |
| system.physmem.bytesPerActivate::total 62 |
| system.physmem.totQLat 6135000 |
| system.physmem.totMemAccLat 14478750 |
| system.physmem.totBusLat 2225000 |
| system.physmem.avgQLat 13786.52 |
| system.physmem.avgBusLat 5000.00 |
| system.physmem.avgMemAccLat 32536.52 |
| system.physmem.avgRdBW 1402.82 |
| system.physmem.avgWrBW 0.00 |
| system.physmem.avgRdBWSys 1402.82 |
| system.physmem.avgWrBWSys 0.00 |
| system.physmem.peakBW 12800.00 |
| system.physmem.busUtil 10.96 |
| system.physmem.busUtilRead 10.96 |
| system.physmem.busUtilWrite 0.00 |
| system.physmem.avgRdQLen 1.85 |
| system.physmem.avgWrQLen 0.00 |
| system.physmem.readRowHits 373 |
| system.physmem.writeRowHits 0 |
| system.physmem.readRowHitRate 83.82 |
| system.physmem.writeRowHitRate nan |
| system.physmem.avgGap 45529.21 |
| system.physmem.pageHitRate 83.82 |
| system.physmem_0.actEnergy 349860 |
| system.physmem_0.preEnergy 170775 |
| system.physmem_0.readEnergy 2334780 |
| system.physmem_0.writeEnergy 0 |
| system.physmem_0.refreshEnergy 1229280.000000 |
| system.physmem_0.actBackEnergy 3562500 |
| system.physmem_0.preBackEnergy 28800 |
| system.physmem_0.actPowerDownEnergy 5660100 |
| system.physmem_0.prePowerDownEnergy 960 |
| system.physmem_0.selfRefreshEnergy 0 |
| system.physmem_0.totalEnergy 13337055 |
| system.physmem_0.averagePower 656.916882 |
| system.physmem_0.totalIdleTime 12261000 |
| system.physmem_0.memoryStateTime::IDLE 19000 |
| system.physmem_0.memoryStateTime::REF 520000 |
| system.physmem_0.memoryStateTime::SREF 0 |
| system.physmem_0.memoryStateTime::PRE_PDN 2500 |
| system.physmem_0.memoryStateTime::ACT 7351250 |
| system.physmem_0.memoryStateTime::ACT_PDN 12409250 |
| system.physmem_1.actEnergy 164220 |
| system.physmem_1.preEnergy 64515 |
| system.physmem_1.readEnergy 842520 |
| system.physmem_1.writeEnergy 0 |
| system.physmem_1.refreshEnergy 1229280.000000 |
| system.physmem_1.actBackEnergy 1478010 |
| system.physmem_1.preBackEnergy 68640 |
| system.physmem_1.actPowerDownEnergy 7415130 |
| system.physmem_1.prePowerDownEnergy 238560 |
| system.physmem_1.selfRefreshEnergy 0 |
| system.physmem_1.totalEnergy 11500875 |
| system.physmem_1.averagePower 566.475803 |
| system.physmem_1.totalIdleTime 16880000 |
| system.physmem_1.memoryStateTime::IDLE 110000 |
| system.physmem_1.memoryStateTime::REF 520000 |
| system.physmem_1.memoryStateTime::SREF 0 |
| system.physmem_1.memoryStateTime::PRE_PDN 620500 |
| system.physmem_1.memoryStateTime::ACT 2792000 |
| system.physmem_1.memoryStateTime::ACT_PDN 16259500 |
| system.pwrStateResidencyTicks::UNDEFINED 20302000 |
| system.cpu.branchPred.lookups 2438 |
| system.cpu.branchPred.condPredicted 1441 |
| system.cpu.branchPred.condIncorrect 523 |
| system.cpu.branchPred.BTBLookups 913 |
| system.cpu.branchPred.BTBHits 446 |
| system.cpu.branchPred.BTBCorrect 0 |
| system.cpu.branchPred.BTBHitPct 48.849945 |
| system.cpu.branchPred.usedRAS 286 |
| system.cpu.branchPred.RASInCorrect 57 |
| system.cpu.branchPred.indirectLookups 163 |
| system.cpu.branchPred.indirectHits 13 |
| system.cpu.branchPred.indirectMisses 150 |
| system.cpu.branchPredindirectMispredicted 59 |
| system.cpu_clk_domain.clock 500 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 |
| system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 |
| system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.accesses 0 |
| system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 |
| system.cpu.dtb.walker.walks 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.dtb.walker.walkRequestOrigin::total 0 |
| system.cpu.dtb.inst_hits 0 |
| system.cpu.dtb.inst_misses 0 |
| system.cpu.dtb.read_hits 0 |
| system.cpu.dtb.read_misses 0 |
| system.cpu.dtb.write_hits 0 |
| system.cpu.dtb.write_misses 0 |
| system.cpu.dtb.flush_tlb 0 |
| system.cpu.dtb.flush_tlb_mva 0 |
| system.cpu.dtb.flush_tlb_mva_asid 0 |
| system.cpu.dtb.flush_tlb_asid 0 |
| system.cpu.dtb.flush_entries 0 |
| system.cpu.dtb.align_faults 0 |
| system.cpu.dtb.prefetch_faults 0 |
| system.cpu.dtb.domain_faults 0 |
| system.cpu.dtb.perms_faults 0 |
| system.cpu.dtb.read_accesses 0 |
| system.cpu.dtb.write_accesses 0 |
| system.cpu.dtb.inst_accesses 0 |
| system.cpu.dtb.hits 0 |
| system.cpu.dtb.misses 0 |
| system.cpu.dtb.accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 |
| system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.read_hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.read_misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.write_hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.write_misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 |
| system.cpu.istage2_mmu.stage2_tlb.align_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.accesses 0 |
| system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 20302000 |
| system.cpu.itb.walker.walks 0 |
| system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.itb.walker.walkRequestOrigin::total 0 |
| system.cpu.itb.inst_hits 0 |
| system.cpu.itb.inst_misses 0 |
| system.cpu.itb.read_hits 0 |
| system.cpu.itb.read_misses 0 |
| system.cpu.itb.write_hits 0 |
| system.cpu.itb.write_misses 0 |
| system.cpu.itb.flush_tlb 0 |
| system.cpu.itb.flush_tlb_mva 0 |
| system.cpu.itb.flush_tlb_mva_asid 0 |
| system.cpu.itb.flush_tlb_asid 0 |
| system.cpu.itb.flush_entries 0 |
| system.cpu.itb.align_faults 0 |
| system.cpu.itb.prefetch_faults 0 |
| system.cpu.itb.domain_faults 0 |
| system.cpu.itb.perms_faults 0 |
| system.cpu.itb.read_accesses 0 |
| system.cpu.itb.write_accesses 0 |
| system.cpu.itb.inst_accesses 0 |
| system.cpu.itb.hits 0 |
| system.cpu.itb.misses 0 |
| system.cpu.itb.accesses 0 |
| system.cpu.workload.numSyscalls 13 |
| system.cpu.pwrStateResidencyTicks::ON 20302000 |
| system.cpu.numCycles 40605 |
| system.cpu.numWorkItemsStarted 0 |
| system.cpu.numWorkItemsCompleted 0 |
| system.cpu.fetch.icacheStallCycles 6162 |
| system.cpu.fetch.Insts 11460 |
| system.cpu.fetch.Branches 2438 |
| system.cpu.fetch.predictedBranches 745 |
| system.cpu.fetch.Cycles 8314 |
| system.cpu.fetch.SquashCycles 1088 |
| system.cpu.fetch.MiscStallCycles 142 |
| system.cpu.fetch.PendingTrapStallCycles 286 |
| system.cpu.fetch.IcacheWaitRetryStallCycles 466 |
| system.cpu.fetch.CacheLines 3900 |
| system.cpu.fetch.IcacheSquashes 180 |
| system.cpu.fetch.rateDist::samples 15914 |
| system.cpu.fetch.rateDist::mean 0.856227 |
| system.cpu.fetch.rateDist::stdev 1.206589 |
| system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% |
| system.cpu.fetch.rateDist::0 9531 59.89% 59.89% |
| system.cpu.fetch.rateDist::1 2501 15.72% 75.61% |
| system.cpu.fetch.rateDist::2 521 3.27% 78.88% |
| system.cpu.fetch.rateDist::3 3361 21.12% 100.00% |
| system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% |
| system.cpu.fetch.rateDist::min_value 0 |
| system.cpu.fetch.rateDist::max_value 3 |
| system.cpu.fetch.rateDist::total 15914 |
| system.cpu.fetch.branchRate 0.060042 |
| system.cpu.fetch.rate 0.282231 |
| system.cpu.decode.IdleCycles 5816 |
| system.cpu.decode.BlockedCycles 4410 |
| system.cpu.decode.RunCycles 5171 |
| system.cpu.decode.UnblockCycles 132 |
| system.cpu.decode.SquashCycles 385 |
| system.cpu.decode.BranchResolved 538 |
| system.cpu.decode.BranchMispred 162 |
| system.cpu.decode.DecodedInsts 10171 |
| system.cpu.decode.SquashedInsts 1674 |
| system.cpu.rename.SquashCycles 385 |
| system.cpu.rename.IdleCycles 6927 |
| system.cpu.rename.BlockCycles 1165 |
| system.cpu.rename.serializeStallCycles 2515 |
| system.cpu.rename.RunCycles 4182 |
| system.cpu.rename.UnblockCycles 740 |
| system.cpu.rename.RenamedInsts 9091 |
| system.cpu.rename.SquashedInsts 462 |
| system.cpu.rename.ROBFullEvents 25 |
| system.cpu.rename.IQFullEvents 1 |
| system.cpu.rename.LQFullEvents 28 |
| system.cpu.rename.SQFullEvents 631 |
| system.cpu.rename.RenamedOperands 9449 |
| system.cpu.rename.RenameLookups 41113 |
| system.cpu.rename.int_rename_lookups 9997 |
| system.cpu.rename.fp_rename_lookups 17 |
| system.cpu.rename.CommittedMaps 5494 |
| system.cpu.rename.UndoneMaps 3955 |
| system.cpu.rename.serializingInsts 29 |
| system.cpu.rename.tempSerializingInsts 27 |
| system.cpu.rename.skidInsts 332 |
| system.cpu.memDep0.insertedLoads 1823 |
| system.cpu.memDep0.insertedStores 1287 |
| system.cpu.memDep0.conflictingLoads 1 |
| system.cpu.memDep0.conflictingStores 0 |
| system.cpu.iq.iqInstsAdded 8508 |
| system.cpu.iq.iqNonSpecInstsAdded 38 |
| system.cpu.iq.iqInstsIssued 7227 |
| system.cpu.iq.iqSquashedInstsIssued 183 |
| system.cpu.iq.iqSquashedInstsExamined 3167 |
| system.cpu.iq.iqSquashedOperandsExamined 8218 |
| system.cpu.iq.iqSquashedNonSpecRemoved 1 |
| system.cpu.iq.issued_per_cycle::samples 15914 |
| system.cpu.iq.issued_per_cycle::mean 0.454128 |
| system.cpu.iq.issued_per_cycle::stdev 0.844358 |
| system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% |
| system.cpu.iq.issued_per_cycle::0 11653 73.22% 73.22% |
| system.cpu.iq.issued_per_cycle::1 1987 12.49% 85.71% |
| system.cpu.iq.issued_per_cycle::2 1624 10.20% 95.92% |
| system.cpu.iq.issued_per_cycle::3 608 3.82% 99.74% |
| system.cpu.iq.issued_per_cycle::4 42 0.26% 100.00% |
| system.cpu.iq.issued_per_cycle::5 0 0.00% 100.00% |
| system.cpu.iq.issued_per_cycle::6 0 0.00% 100.00% |
| system.cpu.iq.issued_per_cycle::7 0 0.00% 100.00% |
| system.cpu.iq.issued_per_cycle::8 0 0.00% 100.00% |
| system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% |
| system.cpu.iq.issued_per_cycle::min_value 0 |
| system.cpu.iq.issued_per_cycle::max_value 4 |
| system.cpu.iq.issued_per_cycle::total 15914 |
| system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% |
| system.cpu.iq.fu_full::IntAlu 414 28.79% 28.79% |
| system.cpu.iq.fu_full::IntMult 0 0.00% 28.79% |
| system.cpu.iq.fu_full::IntDiv 0 0.00% 28.79% |
| system.cpu.iq.fu_full::FloatAdd 0 0.00% 28.79% |
| system.cpu.iq.fu_full::FloatCmp 0 0.00% 28.79% |
| system.cpu.iq.fu_full::FloatCvt 0 0.00% 28.79% |
| system.cpu.iq.fu_full::FloatMult 0 0.00% 28.79% |
| system.cpu.iq.fu_full::FloatMultAcc 0 0.00% 28.79% |
| system.cpu.iq.fu_full::FloatDiv 0 0.00% 28.79% |
| system.cpu.iq.fu_full::FloatMisc 0 0.00% 28.79% |
| system.cpu.iq.fu_full::FloatSqrt 0 0.00% 28.79% |
| system.cpu.iq.fu_full::SimdAdd 0 0.00% 28.79% |
| system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 28.79% |
| system.cpu.iq.fu_full::SimdAlu 0 0.00% 28.79% |
| system.cpu.iq.fu_full::SimdCmp 0 0.00% 28.79% |
| system.cpu.iq.fu_full::SimdCvt 0 0.00% 28.79% |
| system.cpu.iq.fu_full::SimdMisc 0 0.00% 28.79% |
| system.cpu.iq.fu_full::SimdMult 0 0.00% 28.79% |
| system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 28.79% |
| system.cpu.iq.fu_full::SimdShift 0 0.00% 28.79% |
| system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 28.79% |
| system.cpu.iq.fu_full::SimdSqrt 0 0.00% 28.79% |
| system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 28.79% |
| system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 28.79% |
| system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 28.79% |
| system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 28.79% |
| system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 28.79% |
| system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 28.79% |
| system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 28.79% |
| system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 28.79% |
| system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 28.79% |
| system.cpu.iq.fu_full::MemRead 469 32.61% 61.40% |
| system.cpu.iq.fu_full::MemWrite 538 37.41% 98.82% |
| system.cpu.iq.fu_full::FloatMemRead 0 0.00% 98.82% |
| system.cpu.iq.fu_full::FloatMemWrite 17 1.18% 100.00% |
| system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% |
| system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% |
| system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% |
| system.cpu.iq.FU_type_0::IntAlu 4537 62.78% 62.78% |
| system.cpu.iq.FU_type_0::IntMult 5 0.07% 62.85% |
| system.cpu.iq.FU_type_0::IntDiv 0 0.00% 62.85% |
| system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 62.85% |
| system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 62.85% |
| system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 62.85% |
| system.cpu.iq.FU_type_0::FloatMult 0 0.00% 62.85% |
| system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 62.85% |
| system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 62.85% |
| system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 62.85% |
| system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 62.85% |
| system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 62.85% |
| system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 62.85% |
| system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 62.85% |
| system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 62.85% |
| system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 62.85% |
| system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 62.85% |
| system.cpu.iq.FU_type_0::SimdMult 0 0.00% 62.85% |
| system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 62.85% |
| system.cpu.iq.FU_type_0::SimdShift 0 0.00% 62.85% |
| system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 62.85% |
| system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 62.85% |
| system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 62.85% |
| system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 62.85% |
| system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 62.85% |
| system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 62.85% |
| system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 62.85% |
| system.cpu.iq.FU_type_0::SimdFloatMisc 3 0.04% 62.89% |
| system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 62.89% |
| system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.89% |
| system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.89% |
| system.cpu.iq.FU_type_0::MemRead 1601 22.15% 85.04% |
| system.cpu.iq.FU_type_0::MemWrite 1065 14.74% 99.78% |
| system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 99.78% |
| system.cpu.iq.FU_type_0::FloatMemWrite 16 0.22% 100.00% |
| system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% |
| system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% |
| system.cpu.iq.FU_type_0::total 7227 |
| system.cpu.iq.rate 0.177983 |
| system.cpu.iq.fu_busy_cnt 1438 |
| system.cpu.iq.fu_busy_rate 0.198976 |
| system.cpu.iq.int_inst_queue_reads 31940 |
| system.cpu.iq.int_inst_queue_writes 11704 |
| system.cpu.iq.int_inst_queue_wakeup_accesses 6623 |
| system.cpu.iq.fp_inst_queue_reads 49 |
| system.cpu.iq.fp_inst_queue_writes 16 |
| system.cpu.iq.fp_inst_queue_wakeup_accesses 16 |
| system.cpu.iq.int_alu_accesses 8632 |
| system.cpu.iq.fp_alu_accesses 33 |
| system.cpu.iew.lsq.thread0.forwLoads 12 |
| system.cpu.iew.lsq.thread0.invAddrLoads 0 |
| system.cpu.iew.lsq.thread0.squashedLoads 796 |
| system.cpu.iew.lsq.thread0.ignoredResponses 0 |
| system.cpu.iew.lsq.thread0.memOrderViolation 7 |
| system.cpu.iew.lsq.thread0.squashedStores 349 |
| system.cpu.iew.lsq.thread0.invAddrSwpfs 0 |
| system.cpu.iew.lsq.thread0.blockedLoads 0 |
| system.cpu.iew.lsq.thread0.rescheduledLoads 7 |
| system.cpu.iew.lsq.thread0.cacheBlocked 18 |
| system.cpu.iew.iewIdleCycles 0 |
| system.cpu.iew.iewSquashCycles 385 |
| system.cpu.iew.iewBlockCycles 345 |
| system.cpu.iew.iewUnblockCycles 11 |
| system.cpu.iew.iewDispatchedInsts 8559 |
| system.cpu.iew.iewDispSquashedInsts 0 |
| system.cpu.iew.iewDispLoadInsts 1823 |
| system.cpu.iew.iewDispStoreInsts 1287 |
| system.cpu.iew.iewDispNonSpecInsts 26 |
| system.cpu.iew.iewIQFullEvents 3 |
| system.cpu.iew.iewLSQFullEvents 6 |
| system.cpu.iew.memOrderViolationEvents 7 |
| system.cpu.iew.predictedTakenIncorrect 60 |
| system.cpu.iew.predictedNotTakenIncorrect 320 |
| system.cpu.iew.branchMispredicts 380 |
| system.cpu.iew.iewExecutedInsts 6823 |
| system.cpu.iew.iewExecLoadInsts 1419 |
| system.cpu.iew.iewExecSquashedInsts 404 |
| system.cpu.iew.exec_swp 0 |
| system.cpu.iew.exec_nop 13 |
| system.cpu.iew.exec_refs 2443 |
| system.cpu.iew.exec_branches 1299 |
| system.cpu.iew.exec_stores 1024 |
| system.cpu.iew.exec_rate 0.168033 |
| system.cpu.iew.wb_sent 6684 |
| system.cpu.iew.wb_count 6639 |
| system.cpu.iew.wb_producers 2983 |
| system.cpu.iew.wb_consumers 5430 |
| system.cpu.iew.wb_rate 0.163502 |
| system.cpu.iew.wb_fanout 0.549355 |
| system.cpu.commit.commitSquashedInsts 2701 |
| system.cpu.commit.commitNonSpecStalls 37 |
| system.cpu.commit.branchMispredicts 364 |
| system.cpu.commit.committed_per_cycle::samples 15346 |
| system.cpu.commit.committed_per_cycle::mean 0.350450 |
| system.cpu.commit.committed_per_cycle::stdev 0.989791 |
| system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% |
| system.cpu.commit.committed_per_cycle::0 12681 82.63% 82.63% |
| system.cpu.commit.committed_per_cycle::1 1400 9.12% 91.76% |
| system.cpu.commit.committed_per_cycle::2 606 3.95% 95.71% |
| system.cpu.commit.committed_per_cycle::3 298 1.94% 97.65% |
| system.cpu.commit.committed_per_cycle::4 165 1.08% 98.72% |
| system.cpu.commit.committed_per_cycle::5 80 0.52% 99.24% |
| system.cpu.commit.committed_per_cycle::6 44 0.29% 99.53% |
| system.cpu.commit.committed_per_cycle::7 28 0.18% 99.71% |
| system.cpu.commit.committed_per_cycle::8 44 0.29% 100.00% |
| system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% |
| system.cpu.commit.committed_per_cycle::min_value 0 |
| system.cpu.commit.committed_per_cycle::max_value 8 |
| system.cpu.commit.committed_per_cycle::total 15346 |
| system.cpu.commit.committedInsts 4592 |
| system.cpu.commit.committedOps 5378 |
| system.cpu.commit.swp_count 0 |
| system.cpu.commit.refs 1965 |
| system.cpu.commit.loads 1027 |
| system.cpu.commit.membars 12 |
| system.cpu.commit.branches 1008 |
| system.cpu.commit.fp_insts 16 |
| system.cpu.commit.int_insts 4624 |
| system.cpu.commit.function_calls 82 |
| system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% |
| system.cpu.commit.op_class_0::IntAlu 3406 63.33% 63.33% |
| system.cpu.commit.op_class_0::IntMult 4 0.07% 63.41% |
| system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::FloatAdd 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::FloatMisc 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.41% |
| system.cpu.commit.op_class_0::SimdFloatMisc 3 0.06% 63.46% |
| system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.46% |
| system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.46% |
| system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.46% |
| system.cpu.commit.op_class_0::MemRead 1027 19.10% 82.56% |
| system.cpu.commit.op_class_0::MemWrite 922 17.14% 99.70% |
| system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 99.70% |
| system.cpu.commit.op_class_0::FloatMemWrite 16 0.30% 100.00% |
| system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% |
| system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% |
| system.cpu.commit.op_class_0::total 5378 |
| system.cpu.commit.bw_lim_events 44 |
| system.cpu.rob.rob_reads 23224 |
| system.cpu.rob.rob_writes 16730 |
| system.cpu.timesIdled 212 |
| system.cpu.idleCycles 24691 |
| system.cpu.committedInsts 4592 |
| system.cpu.committedOps 5378 |
| system.cpu.cpi 8.842552 |
| system.cpu.cpi_total 8.842552 |
| system.cpu.ipc 0.113090 |
| system.cpu.ipc_total 0.113090 |
| system.cpu.int_regfile_reads 6850 |
| system.cpu.int_regfile_writes 3795 |
| system.cpu.fp_regfile_reads 16 |
| system.cpu.cc_regfile_reads 24229 |
| system.cpu.cc_regfile_writes 2927 |
| system.cpu.misc_regfile_reads 2559 |
| system.cpu.misc_regfile_writes 24 |
| system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 20302000 |
| system.cpu.dcache.tags.replacements 1 |
| system.cpu.dcache.tags.tagsinuse 84.085192 |
| system.cpu.dcache.tags.total_refs 1923 |
| system.cpu.dcache.tags.sampled_refs 143 |
| system.cpu.dcache.tags.avg_refs 13.447552 |
| system.cpu.dcache.tags.warmup_cycle 0 |
| system.cpu.dcache.tags.occ_blocks::cpu.data 84.085192 |
| system.cpu.dcache.tags.occ_percent::cpu.data 0.164229 |
| system.cpu.dcache.tags.occ_percent::total 0.164229 |
| system.cpu.dcache.tags.occ_task_id_blocks::1024 142 |
| system.cpu.dcache.tags.age_task_id_blocks_1024::0 52 |
| system.cpu.dcache.tags.age_task_id_blocks_1024::1 90 |
| system.cpu.dcache.tags.occ_task_id_percent::1024 0.277344 |
| system.cpu.dcache.tags.tag_accesses 4715 |
| system.cpu.dcache.tags.data_accesses 4715 |
| system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 20302000 |
| system.cpu.dcache.ReadReq_hits::cpu.data 1181 |
| system.cpu.dcache.ReadReq_hits::total 1181 |
| system.cpu.dcache.WriteReq_hits::cpu.data 722 |
| system.cpu.dcache.WriteReq_hits::total 722 |
| system.cpu.dcache.LoadLockedReq_hits::cpu.data 9 |
| system.cpu.dcache.LoadLockedReq_hits::total 9 |
| system.cpu.dcache.StoreCondReq_hits::cpu.data 11 |
| system.cpu.dcache.StoreCondReq_hits::total 11 |
| system.cpu.dcache.demand_hits::cpu.data 1903 |
| system.cpu.dcache.demand_hits::total 1903 |
| system.cpu.dcache.overall_hits::cpu.data 1903 |
| system.cpu.dcache.overall_hits::total 1903 |
| system.cpu.dcache.ReadReq_misses::cpu.data 170 |
| system.cpu.dcache.ReadReq_misses::total 170 |
| system.cpu.dcache.WriteReq_misses::cpu.data 191 |
| system.cpu.dcache.WriteReq_misses::total 191 |
| system.cpu.dcache.LoadLockedReq_misses::cpu.data 2 |
| system.cpu.dcache.LoadLockedReq_misses::total 2 |
| system.cpu.dcache.demand_misses::cpu.data 361 |
| system.cpu.dcache.demand_misses::total 361 |
| system.cpu.dcache.overall_misses::cpu.data 361 |
| system.cpu.dcache.overall_misses::total 361 |
| system.cpu.dcache.ReadReq_miss_latency::cpu.data 12060000 |
| system.cpu.dcache.ReadReq_miss_latency::total 12060000 |
| system.cpu.dcache.WriteReq_miss_latency::cpu.data 8016500 |
| system.cpu.dcache.WriteReq_miss_latency::total 8016500 |
| system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 139000 |
| system.cpu.dcache.LoadLockedReq_miss_latency::total 139000 |
| system.cpu.dcache.demand_miss_latency::cpu.data 20076500 |
| system.cpu.dcache.demand_miss_latency::total 20076500 |
| system.cpu.dcache.overall_miss_latency::cpu.data 20076500 |
| system.cpu.dcache.overall_miss_latency::total 20076500 |
| system.cpu.dcache.ReadReq_accesses::cpu.data 1351 |
| system.cpu.dcache.ReadReq_accesses::total 1351 |
| system.cpu.dcache.WriteReq_accesses::cpu.data 913 |
| system.cpu.dcache.WriteReq_accesses::total 913 |
| system.cpu.dcache.LoadLockedReq_accesses::cpu.data 11 |
| system.cpu.dcache.LoadLockedReq_accesses::total 11 |
| system.cpu.dcache.StoreCondReq_accesses::cpu.data 11 |
| system.cpu.dcache.StoreCondReq_accesses::total 11 |
| system.cpu.dcache.demand_accesses::cpu.data 2264 |
| system.cpu.dcache.demand_accesses::total 2264 |
| system.cpu.dcache.overall_accesses::cpu.data 2264 |
| system.cpu.dcache.overall_accesses::total 2264 |
| system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.125833 |
| system.cpu.dcache.ReadReq_miss_rate::total 0.125833 |
| system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.209200 |
| system.cpu.dcache.WriteReq_miss_rate::total 0.209200 |
| system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.181818 |
| system.cpu.dcache.LoadLockedReq_miss_rate::total 0.181818 |
| system.cpu.dcache.demand_miss_rate::cpu.data 0.159452 |
| system.cpu.dcache.demand_miss_rate::total 0.159452 |
| system.cpu.dcache.overall_miss_rate::cpu.data 0.159452 |
| system.cpu.dcache.overall_miss_rate::total 0.159452 |
| system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 70941.176471 |
| system.cpu.dcache.ReadReq_avg_miss_latency::total 70941.176471 |
| system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 41971.204188 |
| system.cpu.dcache.WriteReq_avg_miss_latency::total 41971.204188 |
| system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 69500 |
| system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 69500 |
| system.cpu.dcache.demand_avg_miss_latency::cpu.data 55613.573407 |
| system.cpu.dcache.demand_avg_miss_latency::total 55613.573407 |
| system.cpu.dcache.overall_avg_miss_latency::cpu.data 55613.573407 |
| system.cpu.dcache.overall_avg_miss_latency::total 55613.573407 |
| system.cpu.dcache.blocked_cycles::no_mshrs 0 |
| system.cpu.dcache.blocked_cycles::no_targets 853 |
| system.cpu.dcache.blocked::no_mshrs 0 |
| system.cpu.dcache.blocked::no_targets 18 |
| system.cpu.dcache.avg_blocked_cycles::no_mshrs nan |
| system.cpu.dcache.avg_blocked_cycles::no_targets 47.388889 |
| system.cpu.dcache.writebacks::writebacks 1 |
| system.cpu.dcache.writebacks::total 1 |
| system.cpu.dcache.ReadReq_mshr_hits::cpu.data 67 |
| system.cpu.dcache.ReadReq_mshr_hits::total 67 |
| system.cpu.dcache.WriteReq_mshr_hits::cpu.data 150 |
| system.cpu.dcache.WriteReq_mshr_hits::total 150 |
| system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data 2 |
| system.cpu.dcache.LoadLockedReq_mshr_hits::total 2 |
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| system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 642 |
| system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 288 |
| system.cpu.toL2Bus.pkt_count::total 930 |
| system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21952 |
| system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9216 |
| system.cpu.toL2Bus.pkt_size::total 31168 |
| system.cpu.toL2Bus.snoops 69 |
| system.cpu.toL2Bus.snoopTraffic 0 |
| system.cpu.toL2Bus.snoop_fanout::samples 512 |
| system.cpu.toL2Bus.snoop_fanout::mean 0.134766 |
| system.cpu.toL2Bus.snoop_fanout::stdev 0.353072 |
| system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% |
| system.cpu.toL2Bus.snoop_fanout::0 445 86.91% 86.91% |
| system.cpu.toL2Bus.snoop_fanout::1 65 12.70% 99.61% |
| system.cpu.toL2Bus.snoop_fanout::2 2 0.39% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::min_value 0 |
| system.cpu.toL2Bus.snoop_fanout::max_value 2 |
| system.cpu.toL2Bus.snoop_fanout::total 512 |
| system.cpu.toL2Bus.reqLayer0.occupancy 289000 |
| system.cpu.toL2Bus.reqLayer0.utilization 1.4 |
| system.cpu.toL2Bus.respLayer0.occupancy 448999 |
| system.cpu.toL2Bus.respLayer0.utilization 2.2 |
| system.cpu.toL2Bus.respLayer1.occupancy 216995 |
| system.cpu.toL2Bus.respLayer1.utilization 1.1 |
| system.membus.snoop_filter.tot_requests 445 |
| system.membus.snoop_filter.hit_single_requests 35 |
| system.membus.snoop_filter.hit_multi_requests 0 |
| system.membus.snoop_filter.tot_snoops 0 |
| system.membus.snoop_filter.hit_single_snoops 0 |
| system.membus.snoop_filter.hit_multi_snoops 0 |
| system.membus.pwrStateResidencyTicks::UNDEFINED 20302000 |
| system.membus.trans_dist::ReadResp 414 |
| system.membus.trans_dist::ReadExReq 30 |
| system.membus.trans_dist::ReadExResp 30 |
| system.membus.trans_dist::ReadSharedReq 415 |
| system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 889 |
| system.membus.pkt_count::total 889 |
| system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 |
| system.membus.pkt_size::total 28416 |
| system.membus.snoops 0 |
| system.membus.snoopTraffic 0 |
| system.membus.snoop_fanout::samples 445 |
| system.membus.snoop_fanout::mean 0 |
| system.membus.snoop_fanout::stdev 0 |
| system.membus.snoop_fanout::underflows 0 0.00% 0.00% |
| system.membus.snoop_fanout::0 445 100.00% 100.00% |
| system.membus.snoop_fanout::1 0 0.00% 100.00% |
| system.membus.snoop_fanout::overflows 0 0.00% 100.00% |
| system.membus.snoop_fanout::min_value 0 |
| system.membus.snoop_fanout::max_value 0 |
| system.membus.snoop_fanout::total 445 |
| system.membus.reqLayer0.occupancy 554444 |
| system.membus.reqLayer0.utilization 2.7 |
| system.membus.respLayer1.occupancy 2338250 |
| system.membus.respLayer1.utilization 11.5 |
| |
| ---------- End Simulation Statistics ---------- |