commit b5e0a8f19ad5fa3d320b890d416d41f65de8707e
author Anouk Van Laer <anouk.vanlaer@arm.com> Thu Sep 27 16:49:30 2018 +0100
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Fri Jan 04 13:24:40 2019 +0000
tree e7da2945276e323cb778d20f414f3bedcfc85b47
parent 8a9e0079e7fc89c7abbf7d360cd1707d11cd3df0

dev-arm: Added unimplemented GICv2 GICC_DIR

This GICC CPU register is not implemented but just gives a warning.

Change-Id: I7630aa1df78dde5cf84a87e26cd580b00b283673
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15275
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

src/dev/arm/gic_v2.cc

diff --git a/src/dev/arm/gic_v2.cc b/src/dev/arm/gic_v2.cc
index 293c72f..1e58718 100644
--- a/src/dev/arm/gic_v2.cc
+++ b/src/dev/arm/gic_v2.cc
@@ -622,6 +622,9 @@
       case GICC_APR3:
         warn("GIC APRn write ignored because not implemented: %#x\n", daddr);
         break;
+      case GICC_DIR:
+        warn("GIC DIR write ignored because not implemented: %#x\n", daddr);
+        break;
       default:
         panic("Tried to write Gic cpu at offset %#x\n", daddr);
         break;

src/dev/arm/gic_v2.hh

diff --git a/src/dev/arm/gic_v2.hh b/src/dev/arm/gic_v2.hh
index 4afad89..49465ad 100644
--- a/src/dev/arm/gic_v2.hh
+++ b/src/dev/arm/gic_v2.hh
@@ -110,6 +110,7 @@
         GICC_APR2  = 0xd8, // active priority register 2
         GICC_APR3  = 0xdc, // active priority register 3
         GICC_IIDR  = 0xfc, // cpu interface id register
+        GICC_DIR   = 0x1000, // deactive interrupt register
     };
 
     static const int SGI_MAX = 16;  // Number of Software Gen Interrupts