| |
| ---------- Begin Simulation Statistics ---------- |
| global.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| global.BPredUnit.BTBHits 146 # Number of BTB hits |
| global.BPredUnit.BTBLookups 613 # Number of BTB lookups |
| global.BPredUnit.RASInCorrect 32 # Number of incorrect RAS predictions. |
| global.BPredUnit.condIncorrect 212 # Number of conditional branches incorrect |
| global.BPredUnit.condPredicted 393 # Number of conditional branches predicted |
| global.BPredUnit.lookups 777 # Number of BP lookups |
| global.BPredUnit.usedRAS 153 # Number of times the RAS was used to get a target. |
| host_inst_rate 24407 # Simulator instruction rate (inst/s) |
| host_mem_usage 153952 # Number of bytes of host memory used |
| host_seconds 0.10 # Real time elapsed on the host |
| host_tick_rate 19202153 # Simulator tick rate (ticks/s) |
| memdepunit.memDep.conflictingLoads 7 # Number of conflicting loads. |
| memdepunit.memDep.conflictingStores 7 # Number of conflicting stores. |
| memdepunit.memDep.insertedLoads 635 # Number of loads inserted to the mem dependence unit. |
| memdepunit.memDep.insertedStores 367 # Number of stores inserted to the mem dependence unit. |
| sim_freq 1000000000000 # Frequency of simulated ticks |
| sim_insts 2387 # Number of instructions simulated |
| sim_seconds 0.000002 # Number of seconds simulated |
| sim_ticks 1884000 # Number of ticks simulated |
| system.cpu.commit.COM:branches 396 # Number of branches committed |
| system.cpu.commit.COM:bw_lim_events 33 # number cycles where commit BW limit reached |
| system.cpu.commit.COM:bw_limited 0 # number of insts not committed due to BW limits |
| system.cpu.commit.COM:committed_per_cycle.start_dist # Number of insts commited each cycle |
| system.cpu.commit.COM:committed_per_cycle.samples 3543 |
| system.cpu.commit.COM:committed_per_cycle.min_value 0 |
| 0 2580 7281.96% |
| 1 265 747.95% |
| 2 337 951.17% |
| 3 138 389.50% |
| 4 67 189.11% |
| 5 69 194.75% |
| 6 32 90.32% |
| 7 22 62.09% |
| 8 33 93.14% |
| system.cpu.commit.COM:committed_per_cycle.max_value 8 |
| system.cpu.commit.COM:committed_per_cycle.end_dist |
| |
| system.cpu.commit.COM:count 2576 # Number of instructions committed |
| system.cpu.commit.COM:loads 415 # Number of loads committed |
| system.cpu.commit.COM:membars 0 # Number of memory barriers committed |
| system.cpu.commit.COM:refs 709 # Number of memory references committed |
| system.cpu.commit.COM:swp_count 0 # Number of s/w prefetches committed |
| system.cpu.commit.branchMispredicts 131 # The number of times a branch was mispredicted |
| system.cpu.commit.commitCommittedInsts 2576 # The number of committed instructions |
| system.cpu.commit.commitNonSpecStalls 4 # The number of times commit has been forced to stall to communicate backwards |
| system.cpu.commit.commitSquashedInsts 1118 # The number of squashed insts skipped by commit |
| system.cpu.committedInsts 2387 # Number of Instructions Simulated |
| system.cpu.committedInsts_total 2387 # Number of Instructions Simulated |
| system.cpu.cpi 1.578969 # CPI: Cycles Per Instruction |
| system.cpu.cpi_total 1.578969 # CPI: Total CPI of All Threads |
| system.cpu.dcache.ReadReq_accesses 518 # number of ReadReq accesses(hits+misses) |
| system.cpu.dcache.ReadReq_avg_miss_latency 6583.333333 # average ReadReq miss latency |
| system.cpu.dcache.ReadReq_avg_mshr_miss_latency 4891.666667 # average ReadReq mshr miss latency |
| system.cpu.dcache.ReadReq_hits 458 # number of ReadReq hits |
| system.cpu.dcache.ReadReq_miss_latency 395000 # number of ReadReq miss cycles |
| system.cpu.dcache.ReadReq_miss_rate 0.115830 # miss rate for ReadReq accesses |
| system.cpu.dcache.ReadReq_misses 60 # number of ReadReq misses |
| system.cpu.dcache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits |
| system.cpu.dcache.ReadReq_mshr_miss_latency 293500 # number of ReadReq MSHR miss cycles |
| system.cpu.dcache.ReadReq_mshr_miss_rate 0.115830 # mshr miss rate for ReadReq accesses |
| system.cpu.dcache.ReadReq_mshr_misses 60 # number of ReadReq MSHR misses |
| system.cpu.dcache.WriteReq_accesses 239 # number of WriteReq accesses(hits+misses) |
| system.cpu.dcache.WriteReq_avg_miss_latency 14216.216216 # average WriteReq miss latency |
| system.cpu.dcache.WriteReq_avg_mshr_miss_latency 5202.702703 # average WriteReq mshr miss latency |
| system.cpu.dcache.WriteReq_hits 202 # number of WriteReq hits |
| system.cpu.dcache.WriteReq_miss_latency 526000 # number of WriteReq miss cycles |
| system.cpu.dcache.WriteReq_miss_rate 0.154812 # miss rate for WriteReq accesses |
| system.cpu.dcache.WriteReq_misses 37 # number of WriteReq misses |
| system.cpu.dcache.WriteReq_mshr_hits 55 # number of WriteReq MSHR hits |
| system.cpu.dcache.WriteReq_mshr_miss_latency 192500 # number of WriteReq MSHR miss cycles |
| system.cpu.dcache.WriteReq_mshr_miss_rate 0.154812 # mshr miss rate for WriteReq accesses |
| system.cpu.dcache.WriteReq_mshr_misses 37 # number of WriteReq MSHR misses |
| system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked |
| system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked |
| system.cpu.dcache.avg_refs 7.905882 # Average number of references to valid blocks. |
| system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked |
| system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked |
| system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked |
| system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked |
| system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| system.cpu.dcache.demand_accesses 757 # number of demand (read+write) accesses |
| system.cpu.dcache.demand_avg_miss_latency 9494.845361 # average overall miss latency |
| system.cpu.dcache.demand_avg_mshr_miss_latency 5010.309278 # average overall mshr miss latency |
| system.cpu.dcache.demand_hits 660 # number of demand (read+write) hits |
| system.cpu.dcache.demand_miss_latency 921000 # number of demand (read+write) miss cycles |
| system.cpu.dcache.demand_miss_rate 0.128137 # miss rate for demand accesses |
| system.cpu.dcache.demand_misses 97 # number of demand (read+write) misses |
| system.cpu.dcache.demand_mshr_hits 65 # number of demand (read+write) MSHR hits |
| system.cpu.dcache.demand_mshr_miss_latency 486000 # number of demand (read+write) MSHR miss cycles |
| system.cpu.dcache.demand_mshr_miss_rate 0.128137 # mshr miss rate for demand accesses |
| system.cpu.dcache.demand_mshr_misses 97 # number of demand (read+write) MSHR misses |
| system.cpu.dcache.fast_writes 0 # number of fast writes performed |
| system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated |
| system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
| system.cpu.dcache.overall_accesses 757 # number of overall (read+write) accesses |
| system.cpu.dcache.overall_avg_miss_latency 9494.845361 # average overall miss latency |
| system.cpu.dcache.overall_avg_mshr_miss_latency 5010.309278 # average overall mshr miss latency |
| system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency |
| system.cpu.dcache.overall_hits 660 # number of overall hits |
| system.cpu.dcache.overall_miss_latency 921000 # number of overall miss cycles |
| system.cpu.dcache.overall_miss_rate 0.128137 # miss rate for overall accesses |
| system.cpu.dcache.overall_misses 97 # number of overall misses |
| system.cpu.dcache.overall_mshr_hits 65 # number of overall MSHR hits |
| system.cpu.dcache.overall_mshr_miss_latency 486000 # number of overall MSHR miss cycles |
| system.cpu.dcache.overall_mshr_miss_rate 0.128137 # mshr miss rate for overall accesses |
| system.cpu.dcache.overall_mshr_misses 97 # number of overall MSHR misses |
| system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles |
| system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses |
| system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache |
| system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr |
| system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue |
| system.cpu.dcache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left |
| system.cpu.dcache.prefetcher.num_hwpf_identified 0 # number of hwpf identified |
| system.cpu.dcache.prefetcher.num_hwpf_issued 0 # number of hwpf issued |
| system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated |
| system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page |
| system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| system.cpu.dcache.replacements 0 # number of replacements |
| system.cpu.dcache.sampled_refs 85 # Sample count of references to valid blocks. |
| system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |
| system.cpu.dcache.tagsinuse 51.399169 # Cycle average of tags in use |
| system.cpu.dcache.total_refs 672 # Total number of references to valid blocks. |
| system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| system.cpu.dcache.writebacks 0 # number of writebacks |
| system.cpu.decode.DECODE:BlockedCycles 87 # Number of cycles decode is blocked |
| system.cpu.decode.DECODE:BranchMispred 83 # Number of times decode detected a branch misprediction |
| system.cpu.decode.DECODE:BranchResolved 125 # Number of times decode resolved a branch |
| system.cpu.decode.DECODE:DecodedInsts 4218 # Number of instructions handled by decode |
| system.cpu.decode.DECODE:IdleCycles 2648 # Number of cycles decode is idle |
| system.cpu.decode.DECODE:RunCycles 808 # Number of cycles decode is running |
| system.cpu.decode.DECODE:SquashCycles 225 # Number of cycles decode is squashing |
| system.cpu.decode.DECODE:SquashedInsts 304 # Number of squashed instructions handled by decode |
| system.cpu.decode.DECODE:UnblockCycles 1 # Number of cycles decode is unblocking |
| system.cpu.fetch.Branches 777 # Number of branches that fetch encountered |
| system.cpu.fetch.CacheLines 686 # Number of cache lines fetched |
| system.cpu.fetch.Cycles 1528 # Number of cycles fetch has run and was not squashing or blocked |
| system.cpu.fetch.IcacheSquashes 107 # Number of outstanding Icache misses that were squashed |
| system.cpu.fetch.Insts 4951 # Number of instructions fetch has processed |
| system.cpu.fetch.SquashCycles 223 # Number of cycles fetch has spent squashing |
| system.cpu.fetch.branchRate 0.206155 # Number of branch fetches per cycle |
| system.cpu.fetch.icacheStallCycles 686 # Number of cycles fetch is stalled on an Icache miss |
| system.cpu.fetch.predictedBranches 299 # Number of branches that fetch has predicted taken |
| system.cpu.fetch.rate 1.313611 # Number of inst fetches per cycle |
| system.cpu.fetch.rateDist.start_dist # Number of instructions fetched each cycle (Total) |
| system.cpu.fetch.rateDist.samples 3769 |
| system.cpu.fetch.rateDist.min_value 0 |
| 0 2929 7771.29% |
| 1 36 95.52% |
| 2 88 233.48% |
| 3 54 143.27% |
| 4 108 286.55% |
| 5 55 145.93% |
| 6 40 106.13% |
| 7 42 111.44% |
| 8 417 1106.39% |
| system.cpu.fetch.rateDist.max_value 8 |
| system.cpu.fetch.rateDist.end_dist |
| |
| system.cpu.icache.ReadReq_accesses 676 # number of ReadReq accesses(hits+misses) |
| system.cpu.icache.ReadReq_avg_miss_latency 5629.032258 # average ReadReq miss latency |
| system.cpu.icache.ReadReq_avg_mshr_miss_latency 4489.247312 # average ReadReq mshr miss latency |
| system.cpu.icache.ReadReq_hits 490 # number of ReadReq hits |
| system.cpu.icache.ReadReq_miss_latency 1047000 # number of ReadReq miss cycles |
| system.cpu.icache.ReadReq_miss_rate 0.275148 # miss rate for ReadReq accesses |
| system.cpu.icache.ReadReq_misses 186 # number of ReadReq misses |
| system.cpu.icache.ReadReq_mshr_hits 10 # number of ReadReq MSHR hits |
| system.cpu.icache.ReadReq_mshr_miss_latency 835000 # number of ReadReq MSHR miss cycles |
| system.cpu.icache.ReadReq_mshr_miss_rate 0.275148 # mshr miss rate for ReadReq accesses |
| system.cpu.icache.ReadReq_mshr_misses 186 # number of ReadReq MSHR misses |
| system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked |
| system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked |
| system.cpu.icache.avg_refs 2.634409 # Average number of references to valid blocks. |
| system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked |
| system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked |
| system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked |
| system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked |
| system.cpu.icache.cache_copies 0 # number of cache copies performed |
| system.cpu.icache.demand_accesses 676 # number of demand (read+write) accesses |
| system.cpu.icache.demand_avg_miss_latency 5629.032258 # average overall miss latency |
| system.cpu.icache.demand_avg_mshr_miss_latency 4489.247312 # average overall mshr miss latency |
| system.cpu.icache.demand_hits 490 # number of demand (read+write) hits |
| system.cpu.icache.demand_miss_latency 1047000 # number of demand (read+write) miss cycles |
| system.cpu.icache.demand_miss_rate 0.275148 # miss rate for demand accesses |
| system.cpu.icache.demand_misses 186 # number of demand (read+write) misses |
| system.cpu.icache.demand_mshr_hits 10 # number of demand (read+write) MSHR hits |
| system.cpu.icache.demand_mshr_miss_latency 835000 # number of demand (read+write) MSHR miss cycles |
| system.cpu.icache.demand_mshr_miss_rate 0.275148 # mshr miss rate for demand accesses |
| system.cpu.icache.demand_mshr_misses 186 # number of demand (read+write) MSHR misses |
| system.cpu.icache.fast_writes 0 # number of fast writes performed |
| system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated |
| system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| system.cpu.icache.overall_accesses 676 # number of overall (read+write) accesses |
| system.cpu.icache.overall_avg_miss_latency 5629.032258 # average overall miss latency |
| system.cpu.icache.overall_avg_mshr_miss_latency 4489.247312 # average overall mshr miss latency |
| system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency |
| system.cpu.icache.overall_hits 490 # number of overall hits |
| system.cpu.icache.overall_miss_latency 1047000 # number of overall miss cycles |
| system.cpu.icache.overall_miss_rate 0.275148 # miss rate for overall accesses |
| system.cpu.icache.overall_misses 186 # number of overall misses |
| system.cpu.icache.overall_mshr_hits 10 # number of overall MSHR hits |
| system.cpu.icache.overall_mshr_miss_latency 835000 # number of overall MSHR miss cycles |
| system.cpu.icache.overall_mshr_miss_rate 0.275148 # mshr miss rate for overall accesses |
| system.cpu.icache.overall_mshr_misses 186 # number of overall MSHR misses |
| system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles |
| system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses |
| system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache |
| system.cpu.icache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr |
| system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue |
| system.cpu.icache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left |
| system.cpu.icache.prefetcher.num_hwpf_identified 0 # number of hwpf identified |
| system.cpu.icache.prefetcher.num_hwpf_issued 0 # number of hwpf issued |
| system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated |
| system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page |
| system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| system.cpu.icache.replacements 0 # number of replacements |
| system.cpu.icache.sampled_refs 186 # Sample count of references to valid blocks. |
| system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |
| system.cpu.icache.tagsinuse 104.691657 # Cycle average of tags in use |
| system.cpu.icache.total_refs 490 # Total number of references to valid blocks. |
| system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| system.cpu.icache.writebacks 0 # number of writebacks |
| system.cpu.idleCycles 998 # Total number of cycles that the CPU has spent unscheduled due to idling |
| system.cpu.iew.EXEC:branches 516 # Number of branches executed |
| system.cpu.iew.EXEC:nop 242 # number of nop insts executed |
| system.cpu.iew.EXEC:rate 0.810295 # Inst execution rate |
| system.cpu.iew.EXEC:refs 894 # number of memory reference insts executed |
| system.cpu.iew.EXEC:stores 334 # Number of stores executed |
| system.cpu.iew.EXEC:swp 0 # number of swp insts executed |
| system.cpu.iew.WB:consumers 1725 # num instructions consuming a value |
| system.cpu.iew.WB:count 2987 # cumulative count of insts written-back |
| system.cpu.iew.WB:fanout 0.794203 # average fanout of values written-back |
| system.cpu.iew.WB:penalized 0 # number of instrctions required to write to 'other' IQ |
| system.cpu.iew.WB:penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| system.cpu.iew.WB:producers 1370 # num instructions producing a value |
| system.cpu.iew.WB:rate 0.792518 # insts written-back per cycle |
| system.cpu.iew.WB:sent 3007 # cumulative count of insts sent to commit |
| system.cpu.iew.branchMispredicts 146 # Number of branch mispredicts detected at execute |
| system.cpu.iew.iewBlockCycles 0 # Number of cycles IEW is blocking |
| system.cpu.iew.iewDispLoadInsts 635 # Number of dispatched load instructions |
| system.cpu.iew.iewDispNonSpecInsts 6 # Number of dispatched non-speculative instructions |
| system.cpu.iew.iewDispSquashedInsts 92 # Number of squashed instructions skipped by dispatch |
| system.cpu.iew.iewDispStoreInsts 367 # Number of dispatched store instructions |
| system.cpu.iew.iewDispatchedInsts 3711 # Number of instructions dispatched to IQ |
| system.cpu.iew.iewExecLoadInsts 560 # Number of load instructions executed |
| system.cpu.iew.iewExecSquashedInsts 111 # Number of squashed instructions skipped in execute |
| system.cpu.iew.iewExecutedInsts 3054 # Number of executed instructions |
| system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall |
| system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall |
| system.cpu.iew.iewSquashCycles 225 # Number of cycles IEW is squashing |
| system.cpu.iew.iewUnblockCycles 0 # Number of cycles IEW is unblocking |
| system.cpu.iew.lsq.thread.0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding |
| system.cpu.iew.lsq.thread.0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked |
| system.cpu.iew.lsq.thread.0.forwLoads 24 # Number of loads that had data forwarded from stores |
| system.cpu.iew.lsq.thread.0.ignoredResponses 0 # Number of memory responses ignored because the instruction is squashed |
| system.cpu.iew.lsq.thread.0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| system.cpu.iew.lsq.thread.0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address |
| system.cpu.iew.lsq.thread.0.memOrderViolation 12 # Number of memory ordering violations |
| system.cpu.iew.lsq.thread.0.rescheduledLoads 0 # Number of loads that were rescheduled |
| system.cpu.iew.lsq.thread.0.squashedLoads 220 # Number of loads squashed |
| system.cpu.iew.lsq.thread.0.squashedStores 73 # Number of stores squashed |
| system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations |
| system.cpu.iew.predictedNotTakenIncorrect 98 # Number of branches that were predicted not taken incorrectly |
| system.cpu.iew.predictedTakenIncorrect 48 # Number of branches that were predicted taken incorrectly |
| system.cpu.ipc 0.633324 # IPC: Instructions Per Cycle |
| system.cpu.ipc_total 0.633324 # IPC: Total IPC of All Threads |
| system.cpu.iq.ISSUE:FU_type_0 3165 # Type of FU issued |
| system.cpu.iq.ISSUE:FU_type_0.start_dist |
| No_OpClass 0 0.00% # Type of FU issued |
| IntAlu 2243 70.87% # Type of FU issued |
| IntMult 1 0.03% # Type of FU issued |
| IntDiv 0 0.00% # Type of FU issued |
| FloatAdd 0 0.00% # Type of FU issued |
| FloatCmp 0 0.00% # Type of FU issued |
| FloatCvt 0 0.00% # Type of FU issued |
| FloatMult 0 0.00% # Type of FU issued |
| FloatDiv 0 0.00% # Type of FU issued |
| FloatSqrt 0 0.00% # Type of FU issued |
| MemRead 581 18.36% # Type of FU issued |
| MemWrite 340 10.74% # Type of FU issued |
| IprAccess 0 0.00% # Type of FU issued |
| InstPrefetch 0 0.00% # Type of FU issued |
| system.cpu.iq.ISSUE:FU_type_0.end_dist |
| system.cpu.iq.ISSUE:fu_busy_cnt 35 # FU busy when requested |
| system.cpu.iq.ISSUE:fu_busy_rate 0.011058 # FU busy rate (busy events/executed inst) |
| system.cpu.iq.ISSUE:fu_full.start_dist |
| No_OpClass 0 0.00% # attempts to use FU when none available |
| IntAlu 1 2.86% # attempts to use FU when none available |
| IntMult 0 0.00% # attempts to use FU when none available |
| IntDiv 0 0.00% # attempts to use FU when none available |
| FloatAdd 0 0.00% # attempts to use FU when none available |
| FloatCmp 0 0.00% # attempts to use FU when none available |
| FloatCvt 0 0.00% # attempts to use FU when none available |
| FloatMult 0 0.00% # attempts to use FU when none available |
| FloatDiv 0 0.00% # attempts to use FU when none available |
| FloatSqrt 0 0.00% # attempts to use FU when none available |
| MemRead 12 34.29% # attempts to use FU when none available |
| MemWrite 22 62.86% # attempts to use FU when none available |
| IprAccess 0 0.00% # attempts to use FU when none available |
| InstPrefetch 0 0.00% # attempts to use FU when none available |
| system.cpu.iq.ISSUE:fu_full.end_dist |
| system.cpu.iq.ISSUE:issued_per_cycle.start_dist # Number of insts issued each cycle |
| system.cpu.iq.ISSUE:issued_per_cycle.samples 3769 |
| system.cpu.iq.ISSUE:issued_per_cycle.min_value 0 |
| 0 2469 6550.81% |
| 1 494 1310.69% |
| 2 274 726.98% |
| 3 234 620.85% |
| 4 152 403.29% |
| 5 87 230.83% |
| 6 40 106.13% |
| 7 14 37.15% |
| 8 5 13.27% |
| system.cpu.iq.ISSUE:issued_per_cycle.max_value 8 |
| system.cpu.iq.ISSUE:issued_per_cycle.end_dist |
| |
| system.cpu.iq.ISSUE:rate 0.839745 # Inst issue rate |
| system.cpu.iq.iqInstsAdded 3463 # Number of instructions added to the IQ (excludes non-spec) |
| system.cpu.iq.iqInstsIssued 3165 # Number of instructions issued |
| system.cpu.iq.iqNonSpecInstsAdded 6 # Number of non-speculative instructions added to the IQ |
| system.cpu.iq.iqSquashedInstsExamined 947 # Number of squashed instructions iterated over during squash; mainly for profiling |
| system.cpu.iq.iqSquashedInstsIssued 1 # Number of squashed instructions issued |
| system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed |
| system.cpu.iq.iqSquashedOperandsExamined 468 # Number of squashed operands that are examined and possibly removed from graph |
| system.cpu.l2cache.ReadExReq_accesses 25 # number of ReadExReq accesses(hits+misses) |
| system.cpu.l2cache.ReadExReq_avg_miss_latency 3720 # average ReadExReq miss latency |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 2720 # average ReadExReq mshr miss latency |
| system.cpu.l2cache.ReadExReq_miss_latency 93000 # number of ReadExReq miss cycles |
| system.cpu.l2cache.ReadExReq_miss_rate 1 # miss rate for ReadExReq accesses |
| system.cpu.l2cache.ReadExReq_misses 25 # number of ReadExReq misses |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency 68000 # number of ReadExReq MSHR miss cycles |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 # mshr miss rate for ReadExReq accesses |
| system.cpu.l2cache.ReadExReq_mshr_misses 25 # number of ReadExReq MSHR misses |
| system.cpu.l2cache.ReadReq_accesses 246 # number of ReadReq accesses(hits+misses) |
| system.cpu.l2cache.ReadReq_avg_miss_latency 3357.723577 # average ReadReq miss latency |
| system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 2357.723577 # average ReadReq mshr miss latency |
| system.cpu.l2cache.ReadReq_miss_latency 826000 # number of ReadReq miss cycles |
| system.cpu.l2cache.ReadReq_miss_rate 1 # miss rate for ReadReq accesses |
| system.cpu.l2cache.ReadReq_misses 246 # number of ReadReq misses |
| system.cpu.l2cache.ReadReq_mshr_miss_latency 580000 # number of ReadReq MSHR miss cycles |
| system.cpu.l2cache.ReadReq_mshr_miss_rate 1 # mshr miss rate for ReadReq accesses |
| system.cpu.l2cache.ReadReq_mshr_misses 246 # number of ReadReq MSHR misses |
| system.cpu.l2cache.UpgradeReq_accesses 13 # number of UpgradeReq accesses(hits+misses) |
| system.cpu.l2cache.UpgradeReq_avg_miss_latency 3230.769231 # average UpgradeReq miss latency |
| system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency 2230.769231 # average UpgradeReq mshr miss latency |
| system.cpu.l2cache.UpgradeReq_miss_latency 42000 # number of UpgradeReq miss cycles |
| system.cpu.l2cache.UpgradeReq_miss_rate 1 # miss rate for UpgradeReq accesses |
| system.cpu.l2cache.UpgradeReq_misses 13 # number of UpgradeReq misses |
| system.cpu.l2cache.UpgradeReq_mshr_miss_latency 29000 # number of UpgradeReq MSHR miss cycles |
| system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 # mshr miss rate for UpgradeReq accesses |
| system.cpu.l2cache.UpgradeReq_mshr_misses 13 # number of UpgradeReq MSHR misses |
| system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked |
| system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked |
| system.cpu.l2cache.avg_refs 0 # Average number of references to valid blocks. |
| system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked |
| system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked |
| system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked |
| system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked |
| system.cpu.l2cache.cache_copies 0 # number of cache copies performed |
| system.cpu.l2cache.demand_accesses 271 # number of demand (read+write) accesses |
| system.cpu.l2cache.demand_avg_miss_latency 3391.143911 # average overall miss latency |
| system.cpu.l2cache.demand_avg_mshr_miss_latency 2391.143911 # average overall mshr miss latency |
| system.cpu.l2cache.demand_hits 0 # number of demand (read+write) hits |
| system.cpu.l2cache.demand_miss_latency 919000 # number of demand (read+write) miss cycles |
| system.cpu.l2cache.demand_miss_rate 1 # miss rate for demand accesses |
| system.cpu.l2cache.demand_misses 271 # number of demand (read+write) misses |
| system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits |
| system.cpu.l2cache.demand_mshr_miss_latency 648000 # number of demand (read+write) MSHR miss cycles |
| system.cpu.l2cache.demand_mshr_miss_rate 1 # mshr miss rate for demand accesses |
| system.cpu.l2cache.demand_mshr_misses 271 # number of demand (read+write) MSHR misses |
| system.cpu.l2cache.fast_writes 0 # number of fast writes performed |
| system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated |
| system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| system.cpu.l2cache.overall_accesses 271 # number of overall (read+write) accesses |
| system.cpu.l2cache.overall_avg_miss_latency 3391.143911 # average overall miss latency |
| system.cpu.l2cache.overall_avg_mshr_miss_latency 2391.143911 # average overall mshr miss latency |
| system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency |
| system.cpu.l2cache.overall_hits 0 # number of overall hits |
| system.cpu.l2cache.overall_miss_latency 919000 # number of overall miss cycles |
| system.cpu.l2cache.overall_miss_rate 1 # miss rate for overall accesses |
| system.cpu.l2cache.overall_misses 271 # number of overall misses |
| system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits |
| system.cpu.l2cache.overall_mshr_miss_latency 648000 # number of overall MSHR miss cycles |
| system.cpu.l2cache.overall_mshr_miss_rate 1 # mshr miss rate for overall accesses |
| system.cpu.l2cache.overall_mshr_misses 271 # number of overall MSHR misses |
| system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles |
| system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses |
| system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache |
| system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr 0 # number of hwpf that were already in mshr |
| system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher 0 # number of hwpf that were already in the prefetch queue |
| system.cpu.l2cache.prefetcher.num_hwpf_evicted 0 # number of hwpf removed due to no buffer left |
| system.cpu.l2cache.prefetcher.num_hwpf_identified 0 # number of hwpf identified |
| system.cpu.l2cache.prefetcher.num_hwpf_issued 0 # number of hwpf issued |
| system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated |
| system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page |
| system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time |
| system.cpu.l2cache.replacements 0 # number of replacements |
| system.cpu.l2cache.sampled_refs 233 # Sample count of references to valid blocks. |
| system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions |
| system.cpu.l2cache.tagsinuse 129.636467 # Cycle average of tags in use |
| system.cpu.l2cache.total_refs 0 # Total number of references to valid blocks. |
| system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| system.cpu.l2cache.writebacks 0 # number of writebacks |
| system.cpu.numCycles 3769 # number of cpu cycles simulated |
| system.cpu.rename.RENAME:CommittedMaps 1768 # Number of HB maps that are committed |
| system.cpu.rename.RENAME:IdleCycles 2724 # Number of cycles rename is idle |
| system.cpu.rename.RENAME:LSQFullEvents 1 # Number of times rename has blocked due to LSQ full |
| system.cpu.rename.RENAME:RenameLookups 4613 # Number of register rename lookups that rename has made |
| system.cpu.rename.RENAME:RenamedInsts 4068 # Number of instructions processed by rename |
| system.cpu.rename.RENAME:RenamedOperands 2909 # Number of destination operands rename has renamed |
| system.cpu.rename.RENAME:RunCycles 733 # Number of cycles rename is running |
| system.cpu.rename.RENAME:SquashCycles 225 # Number of cycles rename is squashing |
| system.cpu.rename.RENAME:UnblockCycles 7 # Number of cycles rename is unblocking |
| system.cpu.rename.RENAME:UndoneMaps 1141 # Number of HB maps that are undone due to squashing |
| system.cpu.rename.RENAME:serializeStallCycles 80 # count of cycles rename stalled for serializing inst |
| system.cpu.rename.RENAME:serializingInsts 8 # count of serializing insts renamed |
| system.cpu.rename.RENAME:skidInsts 52 # count of insts added to the skid buffer |
| system.cpu.rename.RENAME:tempSerializingInsts 6 # count of temporary serializing insts renamed |
| system.cpu.timesIdled 2 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| system.cpu.workload.PROG:num_syscalls 4 # Number of system calls |
| |
| ---------- End Simulation Statistics ---------- |
