commit c5baffb5303e9c49d9d475e38783cdcf3391a9a4
author Giacomo Travaglini <giacomo.travaglini@arm.com> Wed Dec 12 16:56:28 2018 +0000
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Tue Jan 15 17:09:53 2019 +0000
tree 9deba506bf3f975f9a1f27333c0e8419b0b3d783
parent f3ab99ef3ac16bd82b5eec4880e852fbbd31561f

cpu: Fix usage of setArchVecElem

setArchVecElem should create a VecElemClass RegId, and not a VecRegClass.
Initializing a VecRegClass with three arguments makes it panic

Change-Id: I6c398d67305bfe7bea12cb02edd4f4c3a202e69a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15655
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

src/cpu/o3/cpu.cc

diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index e5b8103..8f399e9 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -1466,7 +1466,7 @@
                                 const VecElem& val, ThreadID tid)
 {
     PhysRegIdPtr phys_reg = commitRenameMap[tid].lookup(
-                RegId(VecRegClass, reg_idx, ldx));
+                RegId(VecElemClass, reg_idx, ldx));
     setVecElem(phys_reg, val);
 }