alpha: Stop using architecture specific register types.
Change-Id: I4052000014c9f6f9ecefd3f37e58595c61599484
Reviewed-on: https://gem5-review.googlesource.com/c/14461
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index cc0c583..197bb16 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -107,7 +107,7 @@
tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
}
-MiscReg
+RegVal
ISA::readIpr(int idx, ThreadContext *tc)
{
uint64_t retval = 0; // return value, default 0
diff --git a/src/arch/alpha/idle_event.cc b/src/arch/alpha/idle_event.cc
index 85e1d44..080dcb2 100644
--- a/src/arch/alpha/idle_event.cc
+++ b/src/arch/alpha/idle_event.cc
@@ -40,7 +40,7 @@
IdleStartEvent::process(ThreadContext *tc)
{
if (tc->getKernelStats()) {
- MiscReg val = tc->readMiscRegNoEffect(IPR_PALtemp23);
+ RegVal val = tc->readMiscRegNoEffect(IPR_PALtemp23);
tc->getKernelStats()->setIdleProcess(val, tc);
}
remove();
diff --git a/src/arch/alpha/isa.cc b/src/arch/alpha/isa.cc
index 685ddd4..71cf298 100644
--- a/src/arch/alpha/isa.cc
+++ b/src/arch/alpha/isa.cc
@@ -74,7 +74,7 @@
}
-MiscReg
+RegVal
ISA::readMiscRegNoEffect(int misc_reg, ThreadID tid) const
{
switch (misc_reg) {
@@ -94,7 +94,7 @@
}
}
-MiscReg
+RegVal
ISA::readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid)
{
switch (misc_reg) {
@@ -114,7 +114,7 @@
}
void
-ISA::setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid)
+ISA::setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid)
{
switch (misc_reg) {
case MISCREG_FPCR:
@@ -140,7 +140,7 @@
}
void
-ISA::setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc, ThreadID tid)
+ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc, ThreadID tid)
{
switch (misc_reg) {
case MISCREG_FPCR:
diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh
index 2b183f0..f26031d 100644
--- a/src/arch/alpha/isa.hh
+++ b/src/arch/alpha/isa.hh
@@ -74,11 +74,11 @@
public:
- MiscReg readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
- MiscReg readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
+ RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid = 0) const;
+ RegVal readMiscReg(int misc_reg, ThreadContext *tc, ThreadID tid = 0);
- void setMiscRegNoEffect(int misc_reg, MiscReg val, ThreadID tid=0);
- void setMiscReg(int misc_reg, MiscReg val, ThreadContext *tc,
+ void setMiscRegNoEffect(int misc_reg, RegVal val, ThreadID tid=0);
+ void setMiscReg(int misc_reg, RegVal val, ThreadContext *tc,
ThreadID tid=0);
void
diff --git a/src/arch/alpha/process.cc b/src/arch/alpha/process.cc
index e8dad99..00468bb 100644
--- a/src/arch/alpha/process.cc
+++ b/src/arch/alpha/process.cc
@@ -222,7 +222,7 @@
tc->setMiscRegNoEffect(IPR_MCSR, 0);
}
-AlphaISA::IntReg
+RegVal
AlphaProcess::getSyscallArg(ThreadContext *tc, int &i)
{
assert(i < 6);
@@ -230,7 +230,7 @@
}
void
-AlphaProcess::setSyscallArg(ThreadContext *tc, int i, AlphaISA::IntReg val)
+AlphaProcess::setSyscallArg(ThreadContext *tc, int i, RegVal val)
{
assert(i < 6);
tc->setIntReg(FirstArgumentReg + i, val);
@@ -248,7 +248,7 @@
tc->setIntReg(ReturnValueReg, sysret.returnValue());
} else {
// got an error, return details
- tc->setIntReg(SyscallSuccessReg, (IntReg)-1);
+ tc->setIntReg(SyscallSuccessReg, (RegVal)-1);
tc->setIntReg(ReturnValueReg, sysret.errnoValue());
}
}
diff --git a/src/arch/alpha/process.hh b/src/arch/alpha/process.hh
index 28ecd68..5f22488 100644
--- a/src/arch/alpha/process.hh
+++ b/src/arch/alpha/process.hh
@@ -49,10 +49,10 @@
void argsInit(int intSize, int pageSize);
public:
- AlphaISA::IntReg getSyscallArg(ThreadContext *tc, int &i) override;
+ RegVal getSyscallArg(ThreadContext *tc, int &i) override;
/// Explicitly import the otherwise hidden getSyscallArg
using Process::getSyscallArg;
- void setSyscallArg(ThreadContext *tc, int i, AlphaISA::IntReg val) override;
+ void setSyscallArg(ThreadContext *tc, int i, RegVal val) override;
void setSyscallReturn(ThreadContext *tc,
SyscallReturn return_value) override;
diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh
index 07c0bee..e2e8fed 100644
--- a/src/arch/alpha/registers.hh
+++ b/src/arch/alpha/registers.hh
@@ -46,14 +46,6 @@
// Locked read/write flags are can't be detected by the ISA parser
const int MaxMiscDestRegs = AlphaISAInst::MaxMiscDestRegs + 1;
-typedef RegVal IntReg;
-
-// floating point register file entry type
-typedef RegVal FloatReg;
-
-// control register file contents
-typedef RegVal MiscReg;
-
// dummy typedef since we don't have CC regs
typedef uint8_t CCReg;