commit d65f3f9a846b65d6a1596aa143a555bd0d4287ab
author Gabe Black <gabeblack@google.com> Mon Nov 19 17:55:37 2018 -0800
committer Gabe Black <gabeblack@google.com> Thu Jan 24 23:42:22 2019 +0000
tree b99c41a0760a3ee1665dddc81b9e34c52702139d
parent 34064c4647ff4b9e1675fa94347dfc0f7ded9e7c

base: arch: Get rid of the now unused FloatRegVal type.

This type is no longer used since FP registers are accessed as integer
bit patterns.

Change-Id: I1070f9443d6247165fd64c6bc041811c28287e9f
Reviewed-on: https://gem5-review.googlesource.com/c/14459
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

src/arch/alpha/registers.hh

diff --git a/src/arch/alpha/registers.hh b/src/arch/alpha/registers.hh
index 2bff11b..6c71320 100644
--- a/src/arch/alpha/registers.hh
+++ b/src/arch/alpha/registers.hh
@@ -48,7 +48,6 @@
 typedef RegVal IntReg;
 
 // floating point register file entry type
-typedef FloatRegVal FloatReg;
 typedef RegVal FloatRegBits;
 
 // control register file contents

src/arch/mips/registers.hh

diff --git a/src/arch/mips/registers.hh b/src/arch/mips/registers.hh
index d2095d8..6f7097b 100644
--- a/src/arch/mips/registers.hh
+++ b/src/arch/mips/registers.hh
@@ -282,7 +282,6 @@
 
 // floating point register file entry type
 typedef RegVal FloatRegBits;
-typedef FloatRegVal FloatReg;
 
 // cop-0/cop-1 system control register
 typedef RegVal MiscReg;

src/arch/null/registers.hh

diff --git a/src/arch/null/registers.hh b/src/arch/null/registers.hh
index 527193c..fb815af 100644
--- a/src/arch/null/registers.hh
+++ b/src/arch/null/registers.hh
@@ -48,7 +48,6 @@
 
 typedef RegVal IntReg;
 typedef RegVal FloatRegBits;
-typedef FloatRegVal FloatReg;
 typedef uint8_t CCReg;
 typedef RegVal MiscReg;
 const RegIndex ZeroReg = 0;

src/arch/power/registers.hh

diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index 39f7d34..989b4c5 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -49,7 +49,6 @@
 
 // Floating point register file entry type
 typedef RegVal FloatRegBits;
-typedef FloatRegVal FloatReg;
 typedef RegVal MiscReg;
 
 // dummy typedef since we don't have CC regs

src/arch/riscv/registers.hh

diff --git a/src/arch/riscv/registers.hh b/src/arch/riscv/registers.hh
index 75f74ef..2de154e 100644
--- a/src/arch/riscv/registers.hh
+++ b/src/arch/riscv/registers.hh
@@ -65,7 +65,6 @@
 
 typedef RegVal IntReg;
 typedef RegVal FloatRegBits;
-typedef FloatRegVal FloatReg;
 typedef uint8_t CCReg; // Not applicable to Riscv
 typedef RegVal MiscReg;
 

src/arch/x86/registers.hh

diff --git a/src/arch/x86/registers.hh b/src/arch/x86/registers.hh
index a2a74cc..509f7a1 100644
--- a/src/arch/x86/registers.hh
+++ b/src/arch/x86/registers.hh
@@ -105,7 +105,6 @@
 
 //These floating point types are correct for mmx, but not
 //technically for x87 (80 bits) or at all for xmm (128 bits)
-typedef FloatRegVal FloatReg;
 typedef RegVal FloatRegBits;
 
 } // namespace X86ISA

src/base/types.hh

diff --git a/src/base/types.hh b/src/base/types.hh
index c02a606..d993845 100644
--- a/src/base/types.hh
+++ b/src/base/types.hh
@@ -166,7 +166,6 @@
 const Addr MaxAddr = (Addr)-1;
 
 typedef uint64_t RegVal;
-typedef double FloatRegVal;
 
 static inline uint32_t
 floatToBits32(float val)