dev-arm: Writing ICENABLER for non-SPIs is RAZ/WI (or RES0)
For SGIs and PPIs:
* When ARE is 1 (only value supported in gem5) for the Security state of
an interrupt, the field for that interrupt is RES0 and an implementation
is permitted to make the field RAZ/WI in this case.
Change-Id: I6da2a89b1c848d458f42540e0113e7139b910abb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17630
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
diff --git a/src/dev/arm/gic_v3_distributor.cc b/src/dev/arm/gic_v3_distributor.cc
index 148de5a..f261b29 100644
--- a/src/dev/arm/gic_v3_distributor.cc
+++ b/src/dev/arm/gic_v3_distributor.cc
@@ -578,6 +578,10 @@
// Interrupt Clear-Enable Registers
int first_intid = (addr - GICD_ICENABLER.start()) * 8;
+ if (isNotSPI(first_intid)) {
+ return;
+ }
+
for (int i = 0, int_id = first_intid; i < 8 * size && int_id < itLines;
i++, int_id++) {
