| [root] |
| type=Root |
| children=system |
| eventq_index=0 |
| full_system=false |
| sim_quantum=0 |
| time_sync_enable=false |
| time_sync_period=100000000000 |
| time_sync_spin_threshold=100000000 |
| |
| [system] |
| type=System |
| children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain |
| boot_osflags=a |
| cache_line_size=64 |
| clk_domain=system.clk_domain |
| eventq_index=0 |
| init_param=0 |
| kernel= |
| load_addr_mask=1099511627775 |
| mem_mode=timing |
| mem_ranges= |
| memories=system.physmem |
| num_work_ids=16 |
| readfile= |
| symbolfile= |
| work_begin_ckpt_count=0 |
| work_begin_cpu_id_exit=-1 |
| work_begin_exit_count=0 |
| work_cpus_ckpt_count=0 |
| work_end_ckpt_count=0 |
| work_end_exit_count=0 |
| work_item_id=-1 |
| system_port=system.membus.slave[0] |
| |
| [system.clk_domain] |
| type=SrcClockDomain |
| clock=1000 |
| eventq_index=0 |
| voltage_domain=system.voltage_domain |
| |
| [system.cpu] |
| type=TimingSimpleCPU |
| children=dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload |
| checker=Null |
| clk_domain=system.cpu_clk_domain |
| cpu_id=0 |
| do_checkpoint_insts=true |
| do_quiesce=true |
| do_statistics_insts=true |
| dtb=system.cpu.dtb |
| eventq_index=0 |
| function_trace=false |
| function_trace_start=0 |
| interrupts=system.cpu.interrupts |
| isa=system.cpu.isa |
| itb=system.cpu.itb |
| max_insts_all_threads=0 |
| max_insts_any_thread=0 |
| max_loads_all_threads=0 |
| max_loads_any_thread=0 |
| numThreads=1 |
| profile=0 |
| progress_interval=0 |
| simpoint_start_insts= |
| switched_out=false |
| system=system |
| tracer=system.cpu.tracer |
| workload=system.cpu.workload |
| dcache_port=system.cpu.dcache.cpu_side |
| icache_port=system.cpu.icache.cpu_side |
| |
| [system.cpu.dcache] |
| type=BaseCache |
| children=tags |
| addr_ranges=0:18446744073709551615 |
| assoc=2 |
| clk_domain=system.cpu_clk_domain |
| eventq_index=0 |
| forward_snoops=true |
| hit_latency=2 |
| is_top_level=true |
| max_miss_count=0 |
| mshrs=4 |
| prefetch_on_access=false |
| prefetcher=Null |
| response_latency=2 |
| sequential_access=false |
| size=262144 |
| system=system |
| tags=system.cpu.dcache.tags |
| tgts_per_mshr=20 |
| two_queue=false |
| write_buffers=8 |
| cpu_side=system.cpu.dcache_port |
| mem_side=system.cpu.toL2Bus.slave[1] |
| |
| [system.cpu.dcache.tags] |
| type=LRU |
| assoc=2 |
| block_size=64 |
| clk_domain=system.cpu_clk_domain |
| eventq_index=0 |
| hit_latency=2 |
| sequential_access=false |
| size=262144 |
| |
| [system.cpu.dtb] |
| type=ArmTLB |
| children=walker |
| eventq_index=0 |
| size=64 |
| walker=system.cpu.dtb.walker |
| |
| [system.cpu.dtb.walker] |
| type=ArmTableWalker |
| clk_domain=system.cpu_clk_domain |
| eventq_index=0 |
| num_squash_per_cycle=2 |
| sys=system |
| port=system.cpu.toL2Bus.slave[3] |
| |
| [system.cpu.icache] |
| type=BaseCache |
| children=tags |
| addr_ranges=0:18446744073709551615 |
| assoc=2 |
| clk_domain=system.cpu_clk_domain |
| eventq_index=0 |
| forward_snoops=true |
| hit_latency=2 |
| is_top_level=true |
| max_miss_count=0 |
| mshrs=4 |
| prefetch_on_access=false |
| prefetcher=Null |
| response_latency=2 |
| sequential_access=false |
| size=131072 |
| system=system |
| tags=system.cpu.icache.tags |
| tgts_per_mshr=20 |
| two_queue=false |
| write_buffers=8 |
| cpu_side=system.cpu.icache_port |
| mem_side=system.cpu.toL2Bus.slave[0] |
| |
| [system.cpu.icache.tags] |
| type=LRU |
| assoc=2 |
| block_size=64 |
| clk_domain=system.cpu_clk_domain |
| eventq_index=0 |
| hit_latency=2 |
| sequential_access=false |
| size=131072 |
| |
| [system.cpu.interrupts] |
| type=ArmInterrupts |
| eventq_index=0 |
| |
| [system.cpu.isa] |
| type=ArmISA |
| eventq_index=0 |
| fpsid=1090793632 |
| id_isar0=34607377 |
| id_isar1=34677009 |
| id_isar2=555950401 |
| id_isar3=17899825 |
| id_isar4=268501314 |
| id_isar5=0 |
| id_mmfr0=3 |
| id_mmfr1=0 |
| id_mmfr2=19070976 |
| id_mmfr3=4027589137 |
| id_pfr0=49 |
| id_pfr1=1 |
| midr=890224640 |
| |
| [system.cpu.itb] |
| type=ArmTLB |
| children=walker |
| eventq_index=0 |
| size=64 |
| walker=system.cpu.itb.walker |
| |
| [system.cpu.itb.walker] |
| type=ArmTableWalker |
| clk_domain=system.cpu_clk_domain |
| eventq_index=0 |
| num_squash_per_cycle=2 |
| sys=system |
| port=system.cpu.toL2Bus.slave[2] |
| |
| [system.cpu.l2cache] |
| type=BaseCache |
| children=tags |
| addr_ranges=0:18446744073709551615 |
| assoc=8 |
| clk_domain=system.cpu_clk_domain |
| eventq_index=0 |
| forward_snoops=true |
| hit_latency=20 |
| is_top_level=false |
| max_miss_count=0 |
| mshrs=20 |
| prefetch_on_access=false |
| prefetcher=Null |
| response_latency=20 |
| sequential_access=false |
| size=2097152 |
| system=system |
| tags=system.cpu.l2cache.tags |
| tgts_per_mshr=12 |
| two_queue=false |
| write_buffers=8 |
| cpu_side=system.cpu.toL2Bus.master[0] |
| mem_side=system.membus.slave[1] |
| |
| [system.cpu.l2cache.tags] |
| type=LRU |
| assoc=8 |
| block_size=64 |
| clk_domain=system.cpu_clk_domain |
| eventq_index=0 |
| hit_latency=20 |
| sequential_access=false |
| size=2097152 |
| |
| [system.cpu.toL2Bus] |
| type=CoherentBus |
| clk_domain=system.cpu_clk_domain |
| eventq_index=0 |
| header_cycles=1 |
| system=system |
| use_default_range=false |
| width=32 |
| master=system.cpu.l2cache.cpu_side |
| slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port |
| |
| [system.cpu.tracer] |
| type=ExeTracer |
| eventq_index=0 |
| |
| [system.cpu.workload] |
| type=LiveProcess |
| cmd=twolf smred |
| cwd=build/ARM/tests/opt/long/se/70.twolf/arm/linux/simple-timing |
| egid=100 |
| env= |
| errout=cerr |
| euid=100 |
| eventq_index=0 |
| executable=/dist/cpu2000/binaries/arm/linux/twolf |
| gid=100 |
| input=cin |
| max_stack_size=67108864 |
| output=cout |
| pid=100 |
| ppid=99 |
| simpoint=0 |
| system=system |
| uid=100 |
| |
| [system.cpu_clk_domain] |
| type=SrcClockDomain |
| clock=500 |
| eventq_index=0 |
| voltage_domain=system.voltage_domain |
| |
| [system.membus] |
| type=CoherentBus |
| clk_domain=system.clk_domain |
| eventq_index=0 |
| header_cycles=1 |
| system=system |
| use_default_range=false |
| width=8 |
| master=system.physmem.port |
| slave=system.system_port system.cpu.l2cache.mem_side |
| |
| [system.physmem] |
| type=SimpleMemory |
| bandwidth=73.000000 |
| clk_domain=system.clk_domain |
| conf_table_reported=true |
| eventq_index=0 |
| in_addr_map=true |
| latency=30000 |
| latency_var=0 |
| null=false |
| range=0:134217727 |
| port=system.membus.master[0] |
| |
| [system.voltage_domain] |
| type=VoltageDomain |
| eventq_index=0 |
| voltage=1.000000 |
| |