| [root] |
| type=Root |
| children=system |
| eventq_index=0 |
| full_system=false |
| sim_quantum=0 |
| time_sync_enable=false |
| time_sync_period=100000000000 |
| time_sync_spin_threshold=100000000 |
| |
| [system] |
| type=System |
| children=clk_domain cpu membus monitor physmem |
| boot_osflags=a |
| cache_line_size=64 |
| clk_domain=system.clk_domain |
| eventq_index=0 |
| init_param=0 |
| kernel= |
| load_addr_mask=1099511627775 |
| mem_mode=timing |
| mem_ranges= |
| memories=system.physmem |
| num_work_ids=16 |
| readfile= |
| symbolfile= |
| work_begin_ckpt_count=0 |
| work_begin_cpu_id_exit=-1 |
| work_begin_exit_count=0 |
| work_cpus_ckpt_count=0 |
| work_end_ckpt_count=0 |
| work_end_exit_count=0 |
| work_item_id=-1 |
| system_port=system.membus.slave[1] |
| |
| [system.clk_domain] |
| type=SrcClockDomain |
| children=voltage_domain |
| clock=1000 |
| eventq_index=0 |
| voltage_domain=system.clk_domain.voltage_domain |
| |
| [system.clk_domain.voltage_domain] |
| type=VoltageDomain |
| eventq_index=0 |
| voltage=1.000000 |
| |
| [system.cpu] |
| type=TrafficGen |
| clk_domain=system.clk_domain |
| config_file=tests/quick/se/70.tgen/tgen-simple-mem.cfg |
| elastic_req=false |
| eventq_index=0 |
| system=system |
| port=system.monitor.slave |
| |
| [system.membus] |
| type=NoncoherentBus |
| clk_domain=system.clk_domain |
| eventq_index=0 |
| header_cycles=1 |
| use_default_range=false |
| width=16 |
| master=system.physmem.port |
| slave=system.monitor.master system.system_port |
| |
| [system.monitor] |
| type=CommMonitor |
| bandwidth_bins=20 |
| burst_length_bins=20 |
| clk_domain=system.clk_domain |
| disable_addr_dists=true |
| disable_bandwidth_hists=false |
| disable_burst_length_hists=false |
| disable_itt_dists=false |
| disable_latency_hists=false |
| disable_outstanding_hists=false |
| disable_transaction_hists=false |
| eventq_index=0 |
| itt_bins=20 |
| itt_max_bin=100000 |
| latency_bins=20 |
| outstanding_bins=20 |
| read_addr_mask=18446744073709551615 |
| sample_period=1000000000 |
| trace_file=monitor.ptrc.gz |
| transaction_bins=20 |
| write_addr_mask=18446744073709551615 |
| master=system.membus.slave[0] |
| slave=system.cpu.port |
| |
| [system.physmem] |
| type=SimpleMemory |
| bandwidth=73.000000 |
| clk_domain=system.clk_domain |
| conf_table_reported=true |
| eventq_index=0 |
| in_addr_map=true |
| latency=30000 |
| latency_var=0 |
| null=false |
| range=0:134217727 |
| port=system.membus.master[0] |
| |
