commit f3e17ca77a167ece1972ba73af1c63a85acf9ee8
author Gabe Black <gabeblack@google.com> Fri Oct 12 17:48:48 2018 -0700
committer Gabe Black <gabeblack@google.com> Mon Nov 05 23:42:51 2018 +0000
tree 63cee0bf28ff00c85e5bc0bec5a3aa4dbe0f7ea6
parent 9dbc9bb4f2b49cfa0d9f1cf844929896c27a2d27

sparc: Switch the FloatReg and FloatRegBits types to be 64 bit.

These types aren't used by the ISA itself since they're defined to be
particular primitive types in the ISA description. This just affects
code outside of the ISA which work with those types of registers.

Change-Id: I4f62ab8fe04184cc23845090c82b250145a71747
Reviewed-on: https://gem5-review.googlesource.com/c/13616
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

src/arch/sparc/registers.hh

diff --git a/src/arch/sparc/registers.hh b/src/arch/sparc/registers.hh
index a7f4d2a..b5acaef 100644
--- a/src/arch/sparc/registers.hh
+++ b/src/arch/sparc/registers.hh
@@ -47,8 +47,8 @@
 
 typedef uint64_t IntReg;
 typedef uint64_t MiscReg;
-typedef float FloatReg;
-typedef uint32_t FloatRegBits;
+typedef double FloatReg;
+typedef uint64_t FloatRegBits;
 
 // dummy typedef since we don't have CC regs
 typedef uint8_t CCReg;