| October 6, 2008: m5_2.0_beta6 |
| -------------------- |
| New Features |
| 1. Support for gcc 4.3 |
| 2. Core m5 code in libm5 for integration with other simulators |
| 3. Preliminary support for X86 SE mode |
| 4. Additional system calls emulated |
| 5. m5term updated to work on OS X |
| 6. Ability to disable listen sockets |
| 7. Event queue performance improvements and rewrite |
| 8. Better errors for unconnected memory ports |
| |
| Bug fixes |
| 1. ALPHA_SE O3 perlbmk benchmark |
| 2. Translation bug where O3 could fetch from uncachable memory |
| 3. Many minor bugs |
| |
| Outstanding issues for 2.0 release: |
| -------------------- |
| 1. Statistics cleanup |
| 2. Improve regression system |
| 3. Testing |
| 4. Validation |
| |
| March 1, 2008: m5_2.0_beta5 |
| -------------------- |
| New Features |
| 1. Rick Strong's Simpoints config changes |
| 2. Support for FSU ARM port |
| 3. EXTRAS= option allow architectures to be specified |
| |
| Bug fixes |
| 1. Bus timing more realistic |
| 2. Cache writeback, LL/SC fixes |
| 3. Minor IGbE NIC fixes |
| 4. O3 op latency fix |
| 5. SPARC TLB demap fixes |
| 6. SPARC SE memory layout fixes |
| 7. Variety of MIPS fixes |
| |
| Nov 4, 2007: m5_2.0_beta4 |
| -------------------- |
| New Features |
| 1. New cache model |
| 2. Use of a I/O cache between devices and memory |
| 3. Ability to include compiled code with EXTRAS= |
| 4. Python creation of params structures for initialization |
| 5. Ability to remotely debug in SE |
| |
| Bug fixes: |
| 1. Fix SE serialization |
| 2. SPARC_FS booting with TimingSimpleCPU |
| 3. Rename cycles() to ticks() |
| 4. Various SPARC ISA fixes |
| 5. Draining code for checkpointing |
| 6. Various performance improvements |
| |
| Possible Incompatibilities: |
| 1. Real TLBs are now used in SE mode. This is more accurate however it could |
| cause some problems if you've modified the way page handling is done in |
| SE mode. |
| 2. There have been many changes to the way the SCons files work. SimObjects, |
| sources files, and trace flags are all specified in the SConscript files. |
| To see how to add your sources take a look at one of them. |
| 3. Python is now used to created the parameter structs that were created |
| manually before. The parameters listed in a py file are turned into |
| a header file with the same name (e.g. BadDevice.py -> BadDevice.hh). |
| With this change the structs can be populated automatically and the |
| ugly macros to define and create SimObjects at the bottem of source |
| files are gone. The parameter structs also automatically inherit |
| parameters from their parents. |
| |
| May 16, 2007: m5_2.0_beta3 |
| -------------------- |
| New Features |
| 1. Some support for SPARC full-system simulation |
| 2. Reworking of trace facitities (parameter names changed, variadic macros |
| removed) |
| 3. Scons script cleanups |
| 4. Some support for compiling with Intel CC |
| |
| Bug fixes since beta 2: |
| 1. Many SPARC linux syscall emulation support fixes |
| 2. Multiprocessor linux boot using the detailed O3 CPU module |
| 3. Workaround for DMA bug (final solution to be released with 2.0f) |
| 4. Simulator performance and memory leak fixes |
| 5. Fixed issue where console could stop printing in ALPHA_FS |
| 6. Fix issues with remote debugging |
| 7. Several compile fixes, including gcc 4.1 |
| 8. Many other minor fixes and enhancements |
| |
| Nov. 28, 2006: m5_2.0_beta2 |
| -------------------- |
| Bug fixes since beta 1: |
| 1. Many cache issues resolved |
| 2. Uni-coherence fixes in full-system |
| 3. LL/SC Support |
| 4. Draining/Switchover |
| 5. Functional Accesses |
| 6. Bus now has real timing |
| 7. Single config file for all SpecCPU2000 benchmarks |
| 8. Several other minor bug fixes and enhancements |
| |
| Aug. 25, 2006: m5_2.0_beta patch 1 |
| -------------------- |
| Handful of minor bug fixes for m5_2.0_beta, |
| along with a few new regression tests. |
| |
| Aug. 15, 2006: m5_2.0_beta |
| -------------------- |
| Major update to M5 including: |
| - New CPU model |
| - New memory system |
| - More extensive python integration |
| - Preliminary syscall emulation support for MIPS and SPARC |
| This is a *beta* release, meaning that some features are not complete, |
| and some features from M5 1.X aren't currently supported (e.g., MP |
| coherence). We are working to address these limitations and hope to |
| have a complete 2.0 release soon. |
| |
| Oct. 8, 2005: m5_1.1 |
| -------------------- |
| Update release for IOSCA workshop mini-tutorial. New features include: |
| - Preliminary FreeBSD support |
| - Integration of regression tests into scons build framework |
| - Several bug fixes and better compatibility for Cygwin hosts |
| - Major cleanup of Alpha system code (console, PAL, etc.) to make |
| it easier for others to build/modify |
| - Fixes to enable compilation under g++ 4.0 |
| - Numerous minor bug fixes |
| |
| June 10, 2005: m5_1.0_web |
| ------------------------- |
| The 1.0 release posted on Sourceforge after the ISCA tutorial contains |
| just a few very minor fixes relative to the CD. |
| |
| June 5, 2005: m5_1.0_tutorial |
| ----------------------------- |
| First non-beta release. This release was on the CD distributed at the |
| ISCA tutorial. Major enhancements relative to beta releases include |
| Linux support and Python-based configuration language. |
| |
| June 17, 2004: m5_1.0_beta2 |
| --------------------------- |
| Stealth-mode beta bug-fix update, not widely advertised. |
| |
| Oct. 17, 2003: m5_1.0_beta1 |
| --------------------------- |
| Early beta release. |
