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Lisa Hsu48e6ed42004-03-12 11:04:58 -05001/*
Steve Reinhardtad8b9632005-06-05 05:16:00 -04002 * Copyright (c) 2004-2005 The Regents of The University of Michigan
Lisa Hsu48e6ed42004-03-12 11:04:58 -05003 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Ali Saidicb0cf2d2006-05-31 19:26:56 -040027 *
28 * Authors: Lisa Hsu
Lisa Hsu48e6ed42004-03-12 11:04:58 -050029 */
30
Ali Saidiadce6162005-06-05 01:22:21 -040031/** @file
Lisa Hsu48e6ed42004-03-12 11:04:58 -050032 * Ethernet device register definitions for the National
33 * Semiconductor DP83820 Ethernet controller
34 */
35
Nathan Binkert40174f12004-08-11 10:14:26 -040036#ifndef __DEV_NS_GIGE_REG_H__
37#define __DEV_NS_GIGE_REG_H__
Lisa Hsu48e6ed42004-03-12 11:04:58 -050038
Lisa Hsu0b88d522005-05-28 21:54:32 -040039/* Device Register Address Map */
Gabe Black418ddf42007-09-24 17:39:56 -070040enum DeviceRegisterAddress {
41 CR = 0x00,
42 CFGR = 0x04,
43 MEAR = 0x08,
44 PTSCR = 0x0c,
45 ISR = 0x10,
46 IMR = 0x14,
47 IER = 0x18,
48 IHR = 0x1c,
49 TXDP = 0x20,
50 TXDP_HI = 0x24,
51 TX_CFG = 0x28,
52 GPIOR = 0x2c,
53 RXDP = 0x30,
54 RXDP_HI = 0x34,
55 RX_CFG = 0x38,
56 PQCR = 0x3c,
57 WCSR = 0x40,
58 PCR = 0x44,
59 RFCR = 0x48,
60 RFDR = 0x4c,
61 BRAR = 0x50,
62 BRDR = 0x54,
63 SRR = 0x58,
64 MIBC = 0x5c,
65 MIB_START = 0x60,
66 MIB_END = 0x88,
67 VRCR = 0xbc,
68 VTCR = 0xc0,
69 VDR = 0xc4,
70 CCSR = 0xcc,
71 TBICR = 0xe0,
72 TBISR = 0xe4,
73 TANAR = 0xe8,
74 TANLPAR = 0xec,
75 TANER = 0xf0,
76 TESR = 0xf4,
77 M5REG = 0xf8,
78 LAST = 0xf8,
79 RESERVED = 0xfc
80};
Lisa Hsu48e6ed42004-03-12 11:04:58 -050081
Lisa Hsu0b88d522005-05-28 21:54:32 -040082/* Chip Command Register */
Gabe Black418ddf42007-09-24 17:39:56 -070083enum ChipCommandRegister {
84 CR_TXE = 0x00000001,
85 CR_TXD = 0x00000002,
86 CR_RXE = 0x00000004,
87 CR_RXD = 0x00000008,
88 CR_TXR = 0x00000010,
89 CR_RXR = 0x00000020,
90 CR_SWI = 0x00000080,
91 CR_RST = 0x00000100
92};
Lisa Hsu48e6ed42004-03-12 11:04:58 -050093
94/* configuration register */
Gabe Black418ddf42007-09-24 17:39:56 -070095enum ConfigurationRegisters {
Andreas Hansson12eb0342016-01-11 05:52:20 -050096 CFGR_ZERO = 0x00000000,
Gabe Black418ddf42007-09-24 17:39:56 -070097 CFGR_LNKSTS = 0x80000000,
98 CFGR_SPDSTS = 0x60000000,
99 CFGR_SPDSTS1 = 0x40000000,
100 CFGR_SPDSTS0 = 0x20000000,
101 CFGR_DUPSTS = 0x10000000,
102 CFGR_TBI_EN = 0x01000000,
103 CFGR_RESERVED = 0x0e000000,
104 CFGR_MODE_1000 = 0x00400000,
105 CFGR_AUTO_1000 = 0x00200000,
106 CFGR_PINT_CTL = 0x001c0000,
107 CFGR_PINT_DUPSTS = 0x00100000,
108 CFGR_PINT_LNKSTS = 0x00080000,
109 CFGR_PINT_SPDSTS = 0x00040000,
110 CFGR_TMRTEST = 0x00020000,
111 CFGR_MRM_DIS = 0x00010000,
112 CFGR_MWI_DIS = 0x00008000,
113 CFGR_T64ADDR = 0x00004000,
114 CFGR_PCI64_DET = 0x00002000,
115 CFGR_DATA64_EN = 0x00001000,
116 CFGR_M64ADDR = 0x00000800,
117 CFGR_PHY_RST = 0x00000400,
118 CFGR_PHY_DIS = 0x00000200,
119 CFGR_EXTSTS_EN = 0x00000100,
120 CFGR_REQALG = 0x00000080,
121 CFGR_SB = 0x00000040,
122 CFGR_POW = 0x00000020,
123 CFGR_EXD = 0x00000010,
124 CFGR_PESEL = 0x00000008,
125 CFGR_BROM_DIS = 0x00000004,
126 CFGR_EXT_125 = 0x00000002,
127 CFGR_BEM = 0x00000001
128};
Lisa Hsu48e6ed42004-03-12 11:04:58 -0500129
130/* EEPROM access register */
Gabe Black418ddf42007-09-24 17:39:56 -0700131enum EEPROMAccessRegister {
132 MEAR_EEDI = 0x00000001,
133 MEAR_EEDO = 0x00000002,
134 MEAR_EECLK = 0x00000004,
135 MEAR_EESEL = 0x00000008,
136 MEAR_MDIO = 0x00000010,
137 MEAR_MDDIR = 0x00000020,
138 MEAR_MDC = 0x00000040,
139};
Lisa Hsu48e6ed42004-03-12 11:04:58 -0500140
141/* PCI test control register */
Gabe Black418ddf42007-09-24 17:39:56 -0700142enum PCITestControlRegister {
143 PTSCR_EEBIST_FAIL = 0x00000001,
144 PTSCR_EEBIST_EN = 0x00000002,
145 PTSCR_EELOAD_EN = 0x00000004,
146 PTSCR_RBIST_FAIL = 0x000001b8,
147 PTSCR_RBIST_DONE = 0x00000200,
148 PTSCR_RBIST_EN = 0x00000400,
149 PTSCR_RBIST_RST = 0x00002000,
150 PTSCR_RBIST_RDONLY = 0x000003f9
151};
Lisa Hsu48e6ed42004-03-12 11:04:58 -0500152
153/* interrupt status register */
Gabe Black418ddf42007-09-24 17:39:56 -0700154enum InterruptStatusRegister {
155 ISR_RESERVE = 0x80000000,
156 ISR_TXDESC3 = 0x40000000,
157 ISR_TXDESC2 = 0x20000000,
158 ISR_TXDESC1 = 0x10000000,
159 ISR_TXDESC0 = 0x08000000,
160 ISR_RXDESC3 = 0x04000000,
161 ISR_RXDESC2 = 0x02000000,
162 ISR_RXDESC1 = 0x01000000,
163 ISR_RXDESC0 = 0x00800000,
164 ISR_TXRCMP = 0x00400000,
165 ISR_RXRCMP = 0x00200000,
166 ISR_DPERR = 0x00100000,
167 ISR_SSERR = 0x00080000,
168 ISR_RMABT = 0x00040000,
169 ISR_RTAB = 0x00020000,
170 ISR_RXSOVR = 0x00010000,
171 ISR_HIBINT = 0x00008000,
172 ISR_PHY = 0x00004000,
173 ISR_PME = 0x00002000,
174 ISR_SWI = 0x00001000,
175 ISR_MIB = 0x00000800,
176 ISR_TXURN = 0x00000400,
177 ISR_TXIDLE = 0x00000200,
178 ISR_TXERR = 0x00000100,
179 ISR_TXDESC = 0x00000080,
180 ISR_TXOK = 0x00000040,
181 ISR_RXORN = 0x00000020,
182 ISR_RXIDLE = 0x00000010,
183 ISR_RXEARLY = 0x00000008,
184 ISR_RXERR = 0x00000004,
185 ISR_RXDESC = 0x00000002,
186 ISR_RXOK = 0x00000001,
187 ISR_ALL = 0x7FFFFFFF,
188 ISR_DELAY = (ISR_TXIDLE|ISR_TXDESC|ISR_TXOK|
189 ISR_RXIDLE|ISR_RXDESC|ISR_RXOK),
190 ISR_NODELAY = (ISR_ALL & ~ISR_DELAY),
191 ISR_IMPL = (ISR_SWI|ISR_TXIDLE|ISR_TXDESC|ISR_TXOK|ISR_RXORN|
192 ISR_RXIDLE|ISR_RXDESC|ISR_RXOK),
193 ISR_NOIMPL = (ISR_ALL & ~ISR_IMPL)
194};
Lisa Hsu48e6ed42004-03-12 11:04:58 -0500195
196/* transmit configuration register */
Gabe Black418ddf42007-09-24 17:39:56 -0700197enum TransmitConfigurationRegister {
198 TX_CFG_CSI = 0x80000000,
199 TX_CFG_HBI = 0x40000000,
200 TX_CFG_MLB = 0x20000000,
201 TX_CFG_ATP = 0x10000000,
202 TX_CFG_ECRETRY = 0x00800000,
203 TX_CFG_BRST_DIS = 0x00080000,
204 TX_CFG_MXDMA1024 = 0x00000000,
205 TX_CFG_MXDMA512 = 0x00700000,
206 TX_CFG_MXDMA256 = 0x00600000,
207 TX_CFG_MXDMA128 = 0x00500000,
208 TX_CFG_MXDMA64 = 0x00400000,
209 TX_CFG_MXDMA32 = 0x00300000,
210 TX_CFG_MXDMA16 = 0x00200000,
211 TX_CFG_MXDMA8 = 0x00100000,
212 TX_CFG_MXDMA = 0x00700000,
Lisa Hsu48e6ed42004-03-12 11:04:58 -0500213
Gabe Black418ddf42007-09-24 17:39:56 -0700214 TX_CFG_FLTH_MASK = 0x0000ff00,
215 TX_CFG_DRTH_MASK = 0x000000ff
216};
Lisa Hsu48e6ed42004-03-12 11:04:58 -0500217
218/*general purpose I/O control register */
Gabe Black418ddf42007-09-24 17:39:56 -0700219enum GeneralPurposeIOControlRegister {
220 GPIOR_UNUSED = 0xffff8000,
221 GPIOR_GP5_IN = 0x00004000,
222 GPIOR_GP4_IN = 0x00002000,
223 GPIOR_GP3_IN = 0x00001000,
224 GPIOR_GP2_IN = 0x00000800,
225 GPIOR_GP1_IN = 0x00000400,
226 GPIOR_GP5_OE = 0x00000200,
227 GPIOR_GP4_OE = 0x00000100,
228 GPIOR_GP3_OE = 0x00000080,
229 GPIOR_GP2_OE = 0x00000040,
230 GPIOR_GP1_OE = 0x00000020,
231 GPIOR_GP5_OUT = 0x00000010,
232 GPIOR_GP4_OUT = 0x00000008,
233 GPIOR_GP3_OUT = 0x00000004,
234 GPIOR_GP2_OUT = 0x00000002,
235 GPIOR_GP1_OUT = 0x00000001
236};
Lisa Hsu48e6ed42004-03-12 11:04:58 -0500237
238/* receive configuration register */
Gabe Black418ddf42007-09-24 17:39:56 -0700239enum ReceiveConfigurationRegister {
240 RX_CFG_AEP = 0x80000000,
241 RX_CFG_ARP = 0x40000000,
242 RX_CFG_STRIPCRC = 0x20000000,
243 RX_CFG_RX_FD = 0x10000000,
244 RX_CFG_ALP = 0x08000000,
245 RX_CFG_AIRL = 0x04000000,
246 RX_CFG_MXDMA512 = 0x00700000,
247 RX_CFG_MXDMA = 0x00700000,
248 RX_CFG_DRTH = 0x0000003e,
249 RX_CFG_DRTH0 = 0x00000002
250};
Lisa Hsu48e6ed42004-03-12 11:04:58 -0500251
252/* pause control status register */
Gabe Black418ddf42007-09-24 17:39:56 -0700253enum PauseControlStatusRegister {
254 PCR_PSEN = (1 << 31),
255 PCR_PS_MCAST = (1 << 30),
256 PCR_PS_DA = (1 << 29),
257 PCR_STHI_8 = (3 << 23),
258 PCR_STLO_4 = (1 << 23),
259 PCR_FFHI_8K = (3 << 21),
260 PCR_FFLO_4K = (1 << 21),
261 PCR_PAUSE_CNT = 0xFFFE
262};
Lisa Hsu48e6ed42004-03-12 11:04:58 -0500263
264/*receive filter/match control register */
Gabe Black418ddf42007-09-24 17:39:56 -0700265enum ReceiveFilterMatchControlRegister {
266 RFCR_RFEN = 0x80000000,
267 RFCR_AAB = 0x40000000,
268 RFCR_AAM = 0x20000000,
269 RFCR_AAU = 0x10000000,
270 RFCR_APM = 0x08000000,
271 RFCR_APAT = 0x07800000,
272 RFCR_APAT3 = 0x04000000,
273 RFCR_APAT2 = 0x02000000,
274 RFCR_APAT1 = 0x01000000,
275 RFCR_APAT0 = 0x00800000,
276 RFCR_AARP = 0x00400000,
277 RFCR_MHEN = 0x00200000,
278 RFCR_UHEN = 0x00100000,
279 RFCR_ULM = 0x00080000,
280 RFCR_RFADDR = 0x000003ff
281};
Lisa Hsu48e6ed42004-03-12 11:04:58 -0500282
283/* receive filter/match data register */
Gabe Black418ddf42007-09-24 17:39:56 -0700284enum ReceiveFilterMatchDataRegister {
285 RFDR_BMASK = 0x00030000,
286 RFDR_RFDATA0 = 0x000000ff,
287 RFDR_RFDATA1 = 0x0000ff00
288};
Lisa Hsu48e6ed42004-03-12 11:04:58 -0500289
290/* management information base control register */
Gabe Black418ddf42007-09-24 17:39:56 -0700291enum ManagementInformationBaseControlRegister {
292 MIBC_MIBS = 0x00000008,
293 MIBC_ACLR = 0x00000004,
294 MIBC_FRZ = 0x00000002,
295 MIBC_WRN = 0x00000001
296};
Lisa Hsu48e6ed42004-03-12 11:04:58 -0500297
298/* VLAN/IP receive control register */
Gabe Black418ddf42007-09-24 17:39:56 -0700299enum VLANIPReceiveControlRegister {
300 VRCR_RUDPE = 0x00000080,
301 VRCR_RTCPE = 0x00000040,
302 VRCR_RIPE = 0x00000020,
303 VRCR_IPEN = 0x00000010,
304 VRCR_DUTF = 0x00000008,
305 VRCR_DVTF = 0x00000004,
306 VRCR_VTREN = 0x00000002,
307 VRCR_VTDEN = 0x00000001
308};
Lisa Hsu48e6ed42004-03-12 11:04:58 -0500309
310/* VLAN/IP transmit control register */
Gabe Black418ddf42007-09-24 17:39:56 -0700311enum VLANIPTransmitControlRegister {
312 VTCR_PPCHK = 0x00000008,
313 VTCR_GCHK = 0x00000004,
314 VTCR_VPPTI = 0x00000002,
315 VTCR_VGTI = 0x00000001
316};
Lisa Hsu48e6ed42004-03-12 11:04:58 -0500317
318/* Clockrun Control/Status Register */
Gabe Black418ddf42007-09-24 17:39:56 -0700319enum ClockrunControlStatusRegister {
320 CCSR_CLKRUN_EN = 0x00000001
321};
Lisa Hsu48e6ed42004-03-12 11:04:58 -0500322
323/* TBI control register */
Gabe Black418ddf42007-09-24 17:39:56 -0700324enum TBIControlRegister {
325 TBICR_MR_LOOPBACK = 0x00004000,
326 TBICR_MR_AN_ENABLE = 0x00001000,
327 TBICR_MR_RESTART_AN = 0x00000200
328};
Lisa Hsu48e6ed42004-03-12 11:04:58 -0500329
330/* TBI status register */
Gabe Black418ddf42007-09-24 17:39:56 -0700331enum TBIStatusRegister {
332 TBISR_MR_LINK_STATUS = 0x00000020,
333 TBISR_MR_AN_COMPLETE = 0x00000004
334};
Lisa Hsu48e6ed42004-03-12 11:04:58 -0500335
336/* TBI auto-negotiation advertisement register */
Gabe Black418ddf42007-09-24 17:39:56 -0700337enum TBIAutoNegotiationAdvertisementRegister {
338 TANAR_NP = 0x00008000,
339 TANAR_RF2 = 0x00002000,
340 TANAR_RF1 = 0x00001000,
341 TANAR_PS2 = 0x00000100,
342 TANAR_PS1 = 0x00000080,
343 TANAR_HALF_DUP = 0x00000040,
344 TANAR_FULL_DUP = 0x00000020,
345 TANAR_UNUSED = 0x00000E1F
346};
Lisa Hsu48e6ed42004-03-12 11:04:58 -0500347
Nathan Binkert4f43bc62005-10-18 21:01:05 -0400348/* M5 control register */
Gabe Black418ddf42007-09-24 17:39:56 -0700349enum M5ControlRegister {
350 M5REG_RESERVED = 0xfffffffc,
351 M5REG_RSS = 0x00000004,
352 M5REG_RX_THREAD = 0x00000002,
353 M5REG_TX_THREAD = 0x00000001
354};
Nathan Binkert4f43bc62005-10-18 21:01:05 -0400355
Nathan Binkert80a5c932005-10-12 13:39:40 -0400356struct ns_desc32 {
357 uint32_t link; /* link field to next descriptor in linked list */
358 uint32_t bufptr; /* pointer to the first fragment or buffer */
359 uint32_t cmdsts; /* command/status field */
360 uint32_t extsts; /* extended status field for VLAN and IP info */
361};
362
363struct ns_desc64 {
364 uint64_t link; /* link field to next descriptor in linked list */
365 uint64_t bufptr; /* pointer to the first fragment or buffer */
366 uint32_t cmdsts; /* command/status field */
367 uint32_t extsts; /* extended status field for VLAN and IP info */
Lisa Hsu48e6ed42004-03-12 11:04:58 -0500368};
369
Lisa Hsu48e6ed42004-03-12 11:04:58 -0500370/* cmdsts flags for descriptors */
Gabe Black418ddf42007-09-24 17:39:56 -0700371enum CMDSTSFlatsForDescriptors {
372 CMDSTS_OWN = 0x80000000,
373 CMDSTS_MORE = 0x40000000,
374 CMDSTS_INTR = 0x20000000,
375 CMDSTS_ERR = 0x10000000,
376 CMDSTS_OK = 0x08000000,
377 CMDSTS_LEN_MASK = 0x0000ffff,
Lisa Hsu48e6ed42004-03-12 11:04:58 -0500378
Gabe Black418ddf42007-09-24 17:39:56 -0700379 CMDSTS_DEST_MASK = 0x01800000,
380 CMDSTS_DEST_SELF = 0x00800000,
381 CMDSTS_DEST_MULTI = 0x01000000
382};
Lisa Hsu48e6ed42004-03-12 11:04:58 -0500383
384/* extended flags for descriptors */
Gabe Black418ddf42007-09-24 17:39:56 -0700385enum ExtendedFlagsForDescriptors {
386 EXTSTS_UDPERR = 0x00400000,
387 EXTSTS_UDPPKT = 0x00200000,
388 EXTSTS_TCPERR = 0x00100000,
389 EXTSTS_TCPPKT = 0x00080000,
390 EXTSTS_IPERR = 0x00040000,
391 EXTSTS_IPPKT = 0x00020000
392};
Lisa Hsu48e6ed42004-03-12 11:04:58 -0500393
394/* speed status */
Gabe Black418ddf42007-09-24 17:39:56 -0700395static inline int
396SPDSTS_POLARITY(int lnksts)
397{
398 return (CFGR_SPDSTS1 | CFGR_SPDSTS0 | CFGR_DUPSTS |
Andreas Hansson12eb0342016-01-11 05:52:20 -0500399 (lnksts ? CFGR_LNKSTS : CFGR_ZERO));
Gabe Black418ddf42007-09-24 17:39:56 -0700400}
Lisa Hsu48e6ed42004-03-12 11:04:58 -0500401
Nathan Binkert40174f12004-08-11 10:14:26 -0400402#endif /* __DEV_NS_GIGE_REG_H__ */