Steve Reinhardt | 6df61e1 | 2009-05-11 10:38:46 -0700 | [diff] [blame] | 1 | # Copyright (c) 2006-2007 The Regents of The University of Michigan |
| 2 | # All rights reserved. |
| 3 | # |
| 4 | # Redistribution and use in source and binary forms, with or without |
| 5 | # modification, are permitted provided that the following conditions are |
| 6 | # met: redistributions of source code must retain the above copyright |
| 7 | # notice, this list of conditions and the following disclaimer; |
| 8 | # redistributions in binary form must reproduce the above copyright |
| 9 | # notice, this list of conditions and the following disclaimer in the |
| 10 | # documentation and/or other materials provided with the distribution; |
| 11 | # neither the name of the copyright holders nor the names of its |
| 12 | # contributors may be used to endorse or promote products derived from |
| 13 | # this software without specific prior written permission. |
| 14 | # |
| 15 | # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 16 | # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 17 | # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 18 | # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 19 | # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 20 | # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 21 | # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 22 | # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 23 | # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 24 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 25 | # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 26 | # |
| 27 | # Authors: Ron Dreslinski |
| 28 | |
| 29 | import m5 |
| 30 | from m5.objects import * |
Steve Reinhardt | 6df61e1 | 2009-05-11 10:38:46 -0700 | [diff] [blame] | 31 | |
| 32 | nb_cores = 4 |
| 33 | cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ] |
| 34 | |
Nathan Binkert | da704f5 | 2009-07-06 15:49:47 -0700 | [diff] [blame] | 35 | import ruby_config |
Derek Hower | 5a4ebd6 | 2010-01-25 11:51:16 -0600 | [diff] [blame] | 36 | ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores) |
Nathan Binkert | da704f5 | 2009-07-06 15:49:47 -0700 | [diff] [blame] | 37 | |
Steve Reinhardt | 6df61e1 | 2009-05-11 10:38:46 -0700 | [diff] [blame] | 38 | # system simulated |
Andreas Hansson | 36dc93a | 2015-03-02 04:00:47 -0500 | [diff] [blame] | 39 | system = System(cpu = cpus, physmem = ruby_memory, membus = SystemXBar(), |
Akash Bagdia | 7d7ab73 | 2013-06-27 05:49:49 -0400 | [diff] [blame] | 40 | mem_mode = "timing", |
| 41 | clk_domain = SrcClockDomain(clock = '1GHz')) |
| 42 | |
| 43 | # Create a seperate clock domain for components that should run at |
| 44 | # CPUs frequency |
| 45 | system.cpu_clk_domain = SrcClockDomain(clock = '2GHz') |
Steve Reinhardt | 6df61e1 | 2009-05-11 10:38:46 -0700 | [diff] [blame] | 46 | |
| 47 | for cpu in cpus: |
Andreas Hansson | 32eae80 | 2012-03-02 09:21:48 -0500 | [diff] [blame] | 48 | # create the interrupt controller |
| 49 | cpu.createInterruptController() |
Gabe Black | 00f24ae | 2011-02-03 20:23:00 -0800 | [diff] [blame] | 50 | cpu.connectAllPorts(system.membus) |
Akash Bagdia | 7d7ab73 | 2013-06-27 05:49:49 -0400 | [diff] [blame] | 51 | # All cpus are associated with cpu_clk_domain |
| 52 | cpu.clk_domain = system.cpu_clk_domain |
Steve Reinhardt | 6df61e1 | 2009-05-11 10:38:46 -0700 | [diff] [blame] | 53 | |
| 54 | # connect memory to membus |
Andreas Hansson | 5a9a743 | 2012-02-13 06:43:09 -0500 | [diff] [blame] | 55 | system.physmem.port = system.membus.master |
Steve Reinhardt | 6df61e1 | 2009-05-11 10:38:46 -0700 | [diff] [blame] | 56 | |
Andreas Hansson | ade53de | 2012-01-30 09:37:06 -0500 | [diff] [blame] | 57 | # Connect the system port for loading of binaries etc |
Andreas Hansson | 5a9a743 | 2012-02-13 06:43:09 -0500 | [diff] [blame] | 58 | system.system_port = system.membus.slave |
Steve Reinhardt | 6df61e1 | 2009-05-11 10:38:46 -0700 | [diff] [blame] | 59 | |
| 60 | # ----------------------- |
| 61 | # run simulation |
| 62 | # ----------------------- |
| 63 | |
Gabe Black | ec20ee2 | 2012-01-28 07:24:34 -0800 | [diff] [blame] | 64 | root = Root(full_system = False, system = system) |
Steve Reinhardt | 6df61e1 | 2009-05-11 10:38:46 -0700 | [diff] [blame] | 65 | root.system.mem_mode = 'timing' |