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Steve Reinhardt6df61e12009-05-11 10:38:46 -07001# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
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27# Authors: Ron Dreslinski
28
29import m5
30from m5.objects import *
Steve Reinhardt6df61e12009-05-11 10:38:46 -070031
32nb_cores = 4
33cpus = [ DerivO3CPU(cpu_id=i) for i in xrange(nb_cores) ]
34
Nathan Binkertda704f52009-07-06 15:49:47 -070035import ruby_config
Derek Hower5a4ebd62010-01-25 11:51:16 -060036ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
Nathan Binkertda704f52009-07-06 15:49:47 -070037
Steve Reinhardt6df61e12009-05-11 10:38:46 -070038# system simulated
Andreas Hansson36dc93a2015-03-02 04:00:47 -050039system = System(cpu = cpus, physmem = ruby_memory, membus = SystemXBar(),
Akash Bagdia7d7ab732013-06-27 05:49:49 -040040 mem_mode = "timing",
41 clk_domain = SrcClockDomain(clock = '1GHz'))
42
43# Create a seperate clock domain for components that should run at
44# CPUs frequency
45system.cpu_clk_domain = SrcClockDomain(clock = '2GHz')
Steve Reinhardt6df61e12009-05-11 10:38:46 -070046
47for cpu in cpus:
Andreas Hansson32eae802012-03-02 09:21:48 -050048 # create the interrupt controller
49 cpu.createInterruptController()
Gabe Black00f24ae2011-02-03 20:23:00 -080050 cpu.connectAllPorts(system.membus)
Akash Bagdia7d7ab732013-06-27 05:49:49 -040051 # All cpus are associated with cpu_clk_domain
52 cpu.clk_domain = system.cpu_clk_domain
Steve Reinhardt6df61e12009-05-11 10:38:46 -070053
54# connect memory to membus
Andreas Hansson5a9a7432012-02-13 06:43:09 -050055system.physmem.port = system.membus.master
Steve Reinhardt6df61e12009-05-11 10:38:46 -070056
Andreas Hanssonade53de2012-01-30 09:37:06 -050057# Connect the system port for loading of binaries etc
Andreas Hansson5a9a7432012-02-13 06:43:09 -050058system.system_port = system.membus.slave
Steve Reinhardt6df61e12009-05-11 10:38:46 -070059
60# -----------------------
61# run simulation
62# -----------------------
63
Gabe Blackec20ee22012-01-28 07:24:34 -080064root = Root(full_system = False, system = system)
Steve Reinhardt6df61e12009-05-11 10:38:46 -070065root.system.mem_mode = 'timing'