Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 1 | [root] |
| 2 | type=Root |
| 3 | children=system |
| 4 | full_system=true |
| 5 | time_sync_enable=false |
| 6 | time_sync_period=100000000000 |
| 7 | time_sync_spin_threshold=100000000 |
| 8 | |
| 9 | [system] |
| 10 | type=LinuxAlphaSystem |
| 11 | children=bridge cpu0 cpu1 cpu2 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami |
| 12 | boot_cpu_frequency=500 |
| 13 | boot_osflags=root=/dev/hda1 console=ttyS0 |
| 14 | clock=1000 |
Ali Saidi | d69f904 | 2013-04-22 13:20:33 -0400 | [diff] [blame^] | 15 | console=/dist/m5/system/binaries/console |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 16 | init_param=0 |
Ali Saidi | d69f904 | 2013-04-22 13:20:33 -0400 | [diff] [blame^] | 17 | kernel=/dist/m5/system/binaries/vmlinux |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 18 | load_addr_mask=1099511627775 |
| 19 | mem_mode=atomic |
| 20 | mem_ranges=0:134217727 |
| 21 | memories=system.physmem |
| 22 | num_work_ids=16 |
Ali Saidi | d69f904 | 2013-04-22 13:20:33 -0400 | [diff] [blame^] | 23 | pal=/dist/m5/system/binaries/ts_osfpal |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 24 | readfile=tests/halt.sh |
| 25 | symbolfile= |
| 26 | system_rev=1024 |
| 27 | system_type=34 |
| 28 | work_begin_ckpt_count=0 |
| 29 | work_begin_cpu_id_exit=-1 |
| 30 | work_begin_exit_count=0 |
| 31 | work_cpus_ckpt_count=0 |
| 32 | work_end_ckpt_count=0 |
| 33 | work_end_exit_count=0 |
| 34 | work_item_id=-1 |
| 35 | system_port=system.membus.slave[0] |
| 36 | |
| 37 | [system.bridge] |
| 38 | type=Bridge |
| 39 | clock=1000 |
| 40 | delay=50000 |
| 41 | ranges=8796093022208:18446744073709551615 |
| 42 | req_size=16 |
| 43 | resp_size=16 |
| 44 | master=system.iobus.slave[0] |
| 45 | slave=system.membus.master[0] |
| 46 | |
| 47 | [system.cpu0] |
| 48 | type=AtomicSimpleCPU |
| 49 | children=dcache dtb icache interrupts isa itb tracer |
Nilay Vaish | 9bc132e | 2013-01-24 12:29:00 -0600 | [diff] [blame] | 50 | branchPred=Null |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 51 | checker=Null |
| 52 | clock=500 |
| 53 | cpu_id=0 |
| 54 | do_checkpoint_insts=true |
| 55 | do_quiesce=true |
| 56 | do_statistics_insts=true |
| 57 | dtb=system.cpu0.dtb |
| 58 | fastmem=false |
| 59 | function_trace=false |
| 60 | function_trace_start=0 |
| 61 | interrupts=system.cpu0.interrupts |
| 62 | isa=system.cpu0.isa |
| 63 | itb=system.cpu0.itb |
| 64 | max_insts_all_threads=0 |
| 65 | max_insts_any_thread=0 |
| 66 | max_loads_all_threads=0 |
| 67 | max_loads_any_thread=0 |
| 68 | numThreads=1 |
| 69 | profile=0 |
| 70 | progress_interval=0 |
Ali Saidi | d69f904 | 2013-04-22 13:20:33 -0400 | [diff] [blame^] | 71 | simpoint_interval=100000000 |
| 72 | simpoint_profile=false |
| 73 | simpoint_profile_file=simpoint.bb.gz |
| 74 | simpoint_start_insts= |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 75 | simulate_data_stalls=false |
| 76 | simulate_inst_stalls=false |
| 77 | switched_out=false |
| 78 | system=system |
| 79 | tracer=system.cpu0.tracer |
| 80 | width=1 |
| 81 | workload= |
| 82 | dcache_port=system.cpu0.dcache.cpu_side |
| 83 | icache_port=system.cpu0.icache.cpu_side |
| 84 | |
| 85 | [system.cpu0.dcache] |
| 86 | type=BaseCache |
| 87 | addr_ranges=0:18446744073709551615 |
| 88 | assoc=4 |
| 89 | block_size=64 |
| 90 | clock=500 |
| 91 | forward_snoops=true |
| 92 | hit_latency=2 |
| 93 | is_top_level=true |
| 94 | max_miss_count=0 |
| 95 | mshrs=4 |
| 96 | prefetch_on_access=false |
| 97 | prefetcher=Null |
| 98 | response_latency=2 |
| 99 | size=32768 |
| 100 | system=system |
| 101 | tgts_per_mshr=20 |
| 102 | two_queue=false |
| 103 | write_buffers=8 |
| 104 | cpu_side=system.cpu0.dcache_port |
| 105 | mem_side=system.toL2Bus.slave[1] |
| 106 | |
| 107 | [system.cpu0.dtb] |
| 108 | type=AlphaTLB |
| 109 | size=64 |
| 110 | |
| 111 | [system.cpu0.icache] |
| 112 | type=BaseCache |
| 113 | addr_ranges=0:18446744073709551615 |
| 114 | assoc=1 |
| 115 | block_size=64 |
| 116 | clock=500 |
| 117 | forward_snoops=true |
| 118 | hit_latency=2 |
| 119 | is_top_level=true |
| 120 | max_miss_count=0 |
| 121 | mshrs=4 |
| 122 | prefetch_on_access=false |
| 123 | prefetcher=Null |
| 124 | response_latency=2 |
| 125 | size=32768 |
| 126 | system=system |
| 127 | tgts_per_mshr=20 |
| 128 | two_queue=false |
| 129 | write_buffers=8 |
| 130 | cpu_side=system.cpu0.icache_port |
| 131 | mem_side=system.toL2Bus.slave[0] |
| 132 | |
| 133 | [system.cpu0.interrupts] |
| 134 | type=AlphaInterrupts |
| 135 | |
| 136 | [system.cpu0.isa] |
| 137 | type=AlphaISA |
| 138 | |
| 139 | [system.cpu0.itb] |
| 140 | type=AlphaTLB |
| 141 | size=48 |
| 142 | |
| 143 | [system.cpu0.tracer] |
| 144 | type=ExeTracer |
| 145 | |
| 146 | [system.cpu1] |
| 147 | type=TimingSimpleCPU |
| 148 | children=dtb interrupts isa itb tracer |
Nilay Vaish | 9bc132e | 2013-01-24 12:29:00 -0600 | [diff] [blame] | 149 | branchPred=Null |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 150 | checker=Null |
| 151 | clock=500 |
| 152 | cpu_id=0 |
| 153 | do_checkpoint_insts=true |
| 154 | do_quiesce=true |
| 155 | do_statistics_insts=true |
| 156 | dtb=system.cpu1.dtb |
| 157 | function_trace=false |
| 158 | function_trace_start=0 |
| 159 | interrupts=system.cpu1.interrupts |
| 160 | isa=system.cpu1.isa |
| 161 | itb=system.cpu1.itb |
| 162 | max_insts_all_threads=0 |
| 163 | max_insts_any_thread=0 |
| 164 | max_loads_all_threads=0 |
| 165 | max_loads_any_thread=0 |
| 166 | numThreads=1 |
| 167 | profile=0 |
| 168 | progress_interval=0 |
Ali Saidi | d69f904 | 2013-04-22 13:20:33 -0400 | [diff] [blame^] | 169 | simpoint_start_insts= |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 170 | switched_out=true |
| 171 | system=system |
| 172 | tracer=system.cpu1.tracer |
| 173 | workload= |
| 174 | |
| 175 | [system.cpu1.dtb] |
| 176 | type=AlphaTLB |
| 177 | size=64 |
| 178 | |
| 179 | [system.cpu1.interrupts] |
| 180 | type=AlphaInterrupts |
| 181 | |
| 182 | [system.cpu1.isa] |
| 183 | type=AlphaISA |
| 184 | |
| 185 | [system.cpu1.itb] |
| 186 | type=AlphaTLB |
| 187 | size=48 |
| 188 | |
| 189 | [system.cpu1.tracer] |
| 190 | type=ExeTracer |
| 191 | |
| 192 | [system.cpu2] |
| 193 | type=DerivO3CPU |
Nilay Vaish | 9bc132e | 2013-01-24 12:29:00 -0600 | [diff] [blame] | 194 | children=branchPred dtb fuPool interrupts isa itb tracer |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 195 | LFSTSize=1024 |
| 196 | LQEntries=32 |
| 197 | LSQCheckLoads=true |
| 198 | LSQDepCheckShift=4 |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 199 | SQEntries=32 |
| 200 | SSITSize=1024 |
| 201 | activity=0 |
| 202 | backComSize=5 |
Nilay Vaish | 9bc132e | 2013-01-24 12:29:00 -0600 | [diff] [blame] | 203 | branchPred=system.cpu2.branchPred |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 204 | cachePorts=200 |
| 205 | checker=Null |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 206 | clock=500 |
| 207 | commitToDecodeDelay=1 |
| 208 | commitToFetchDelay=1 |
| 209 | commitToIEWDelay=1 |
| 210 | commitToRenameDelay=1 |
| 211 | commitWidth=8 |
| 212 | cpu_id=0 |
| 213 | decodeToFetchDelay=1 |
| 214 | decodeToRenameDelay=1 |
| 215 | decodeWidth=8 |
| 216 | dispatchWidth=8 |
| 217 | do_checkpoint_insts=true |
| 218 | do_quiesce=true |
| 219 | do_statistics_insts=true |
| 220 | dtb=system.cpu2.dtb |
| 221 | fetchToDecodeDelay=1 |
| 222 | fetchTrapLatency=1 |
| 223 | fetchWidth=8 |
| 224 | forwardComSize=5 |
| 225 | fuPool=system.cpu2.fuPool |
| 226 | function_trace=false |
| 227 | function_trace_start=0 |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 228 | iewToCommitDelay=1 |
| 229 | iewToDecodeDelay=1 |
| 230 | iewToFetchDelay=1 |
| 231 | iewToRenameDelay=1 |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 232 | interrupts=system.cpu2.interrupts |
| 233 | isa=system.cpu2.isa |
| 234 | issueToExecuteDelay=1 |
| 235 | issueWidth=8 |
| 236 | itb=system.cpu2.itb |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 237 | max_insts_all_threads=0 |
| 238 | max_insts_any_thread=0 |
| 239 | max_loads_all_threads=0 |
| 240 | max_loads_any_thread=0 |
| 241 | needsTSO=false |
| 242 | numIQEntries=64 |
| 243 | numPhysFloatRegs=256 |
| 244 | numPhysIntRegs=256 |
| 245 | numROBEntries=192 |
| 246 | numRobs=1 |
| 247 | numThreads=1 |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 248 | profile=0 |
| 249 | progress_interval=0 |
| 250 | renameToDecodeDelay=1 |
| 251 | renameToFetchDelay=1 |
| 252 | renameToIEWDelay=2 |
| 253 | renameToROBDelay=1 |
| 254 | renameWidth=8 |
Ali Saidi | d69f904 | 2013-04-22 13:20:33 -0400 | [diff] [blame^] | 255 | simpoint_start_insts= |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 256 | smtCommitPolicy=RoundRobin |
| 257 | smtFetchPolicy=SingleThread |
| 258 | smtIQPolicy=Partitioned |
| 259 | smtIQThreshold=100 |
| 260 | smtLSQPolicy=Partitioned |
| 261 | smtLSQThreshold=100 |
| 262 | smtNumFetchingThreads=1 |
| 263 | smtROBPolicy=Partitioned |
| 264 | smtROBThreshold=100 |
| 265 | squashWidth=8 |
| 266 | store_set_clear_period=250000 |
| 267 | switched_out=true |
| 268 | system=system |
| 269 | tracer=system.cpu2.tracer |
| 270 | trapLatency=13 |
| 271 | wbDepth=1 |
| 272 | wbWidth=8 |
| 273 | workload= |
| 274 | |
Nilay Vaish | 9bc132e | 2013-01-24 12:29:00 -0600 | [diff] [blame] | 275 | [system.cpu2.branchPred] |
| 276 | type=BranchPredictor |
| 277 | BTBEntries=4096 |
| 278 | BTBTagSize=16 |
| 279 | RASSize=16 |
| 280 | choiceCtrBits=2 |
| 281 | choicePredictorSize=8192 |
| 282 | globalCtrBits=2 |
| 283 | globalHistoryBits=13 |
| 284 | globalPredictorSize=8192 |
| 285 | instShiftAmt=2 |
| 286 | localCtrBits=2 |
| 287 | localHistoryBits=11 |
| 288 | localHistoryTableSize=2048 |
| 289 | localPredictorSize=2048 |
| 290 | numThreads=1 |
| 291 | predType=tournament |
| 292 | |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 293 | [system.cpu2.dtb] |
| 294 | type=AlphaTLB |
| 295 | size=64 |
| 296 | |
| 297 | [system.cpu2.fuPool] |
| 298 | type=FUPool |
| 299 | children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 |
| 300 | FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8 |
| 301 | |
| 302 | [system.cpu2.fuPool.FUList0] |
| 303 | type=FUDesc |
| 304 | children=opList |
| 305 | count=6 |
| 306 | opList=system.cpu2.fuPool.FUList0.opList |
| 307 | |
| 308 | [system.cpu2.fuPool.FUList0.opList] |
| 309 | type=OpDesc |
| 310 | issueLat=1 |
| 311 | opClass=IntAlu |
| 312 | opLat=1 |
| 313 | |
| 314 | [system.cpu2.fuPool.FUList1] |
| 315 | type=FUDesc |
| 316 | children=opList0 opList1 |
| 317 | count=2 |
| 318 | opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1 |
| 319 | |
| 320 | [system.cpu2.fuPool.FUList1.opList0] |
| 321 | type=OpDesc |
| 322 | issueLat=1 |
| 323 | opClass=IntMult |
| 324 | opLat=3 |
| 325 | |
| 326 | [system.cpu2.fuPool.FUList1.opList1] |
| 327 | type=OpDesc |
| 328 | issueLat=19 |
| 329 | opClass=IntDiv |
| 330 | opLat=20 |
| 331 | |
| 332 | [system.cpu2.fuPool.FUList2] |
| 333 | type=FUDesc |
| 334 | children=opList0 opList1 opList2 |
| 335 | count=4 |
| 336 | opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2 |
| 337 | |
| 338 | [system.cpu2.fuPool.FUList2.opList0] |
| 339 | type=OpDesc |
| 340 | issueLat=1 |
| 341 | opClass=FloatAdd |
| 342 | opLat=2 |
| 343 | |
| 344 | [system.cpu2.fuPool.FUList2.opList1] |
| 345 | type=OpDesc |
| 346 | issueLat=1 |
| 347 | opClass=FloatCmp |
| 348 | opLat=2 |
| 349 | |
| 350 | [system.cpu2.fuPool.FUList2.opList2] |
| 351 | type=OpDesc |
| 352 | issueLat=1 |
| 353 | opClass=FloatCvt |
| 354 | opLat=2 |
| 355 | |
| 356 | [system.cpu2.fuPool.FUList3] |
| 357 | type=FUDesc |
| 358 | children=opList0 opList1 opList2 |
| 359 | count=2 |
| 360 | opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 |
| 361 | |
| 362 | [system.cpu2.fuPool.FUList3.opList0] |
| 363 | type=OpDesc |
| 364 | issueLat=1 |
| 365 | opClass=FloatMult |
| 366 | opLat=4 |
| 367 | |
| 368 | [system.cpu2.fuPool.FUList3.opList1] |
| 369 | type=OpDesc |
| 370 | issueLat=12 |
| 371 | opClass=FloatDiv |
| 372 | opLat=12 |
| 373 | |
| 374 | [system.cpu2.fuPool.FUList3.opList2] |
| 375 | type=OpDesc |
| 376 | issueLat=24 |
| 377 | opClass=FloatSqrt |
| 378 | opLat=24 |
| 379 | |
| 380 | [system.cpu2.fuPool.FUList4] |
| 381 | type=FUDesc |
| 382 | children=opList |
| 383 | count=0 |
| 384 | opList=system.cpu2.fuPool.FUList4.opList |
| 385 | |
| 386 | [system.cpu2.fuPool.FUList4.opList] |
| 387 | type=OpDesc |
| 388 | issueLat=1 |
| 389 | opClass=MemRead |
| 390 | opLat=1 |
| 391 | |
| 392 | [system.cpu2.fuPool.FUList5] |
| 393 | type=FUDesc |
| 394 | children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 |
| 395 | count=4 |
| 396 | opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19 |
| 397 | |
| 398 | [system.cpu2.fuPool.FUList5.opList00] |
| 399 | type=OpDesc |
| 400 | issueLat=1 |
| 401 | opClass=SimdAdd |
| 402 | opLat=1 |
| 403 | |
| 404 | [system.cpu2.fuPool.FUList5.opList01] |
| 405 | type=OpDesc |
| 406 | issueLat=1 |
| 407 | opClass=SimdAddAcc |
| 408 | opLat=1 |
| 409 | |
| 410 | [system.cpu2.fuPool.FUList5.opList02] |
| 411 | type=OpDesc |
| 412 | issueLat=1 |
| 413 | opClass=SimdAlu |
| 414 | opLat=1 |
| 415 | |
| 416 | [system.cpu2.fuPool.FUList5.opList03] |
| 417 | type=OpDesc |
| 418 | issueLat=1 |
| 419 | opClass=SimdCmp |
| 420 | opLat=1 |
| 421 | |
| 422 | [system.cpu2.fuPool.FUList5.opList04] |
| 423 | type=OpDesc |
| 424 | issueLat=1 |
| 425 | opClass=SimdCvt |
| 426 | opLat=1 |
| 427 | |
| 428 | [system.cpu2.fuPool.FUList5.opList05] |
| 429 | type=OpDesc |
| 430 | issueLat=1 |
| 431 | opClass=SimdMisc |
| 432 | opLat=1 |
| 433 | |
| 434 | [system.cpu2.fuPool.FUList5.opList06] |
| 435 | type=OpDesc |
| 436 | issueLat=1 |
| 437 | opClass=SimdMult |
| 438 | opLat=1 |
| 439 | |
| 440 | [system.cpu2.fuPool.FUList5.opList07] |
| 441 | type=OpDesc |
| 442 | issueLat=1 |
| 443 | opClass=SimdMultAcc |
| 444 | opLat=1 |
| 445 | |
| 446 | [system.cpu2.fuPool.FUList5.opList08] |
| 447 | type=OpDesc |
| 448 | issueLat=1 |
| 449 | opClass=SimdShift |
| 450 | opLat=1 |
| 451 | |
| 452 | [system.cpu2.fuPool.FUList5.opList09] |
| 453 | type=OpDesc |
| 454 | issueLat=1 |
| 455 | opClass=SimdShiftAcc |
| 456 | opLat=1 |
| 457 | |
| 458 | [system.cpu2.fuPool.FUList5.opList10] |
| 459 | type=OpDesc |
| 460 | issueLat=1 |
| 461 | opClass=SimdSqrt |
| 462 | opLat=1 |
| 463 | |
| 464 | [system.cpu2.fuPool.FUList5.opList11] |
| 465 | type=OpDesc |
| 466 | issueLat=1 |
| 467 | opClass=SimdFloatAdd |
| 468 | opLat=1 |
| 469 | |
| 470 | [system.cpu2.fuPool.FUList5.opList12] |
| 471 | type=OpDesc |
| 472 | issueLat=1 |
| 473 | opClass=SimdFloatAlu |
| 474 | opLat=1 |
| 475 | |
| 476 | [system.cpu2.fuPool.FUList5.opList13] |
| 477 | type=OpDesc |
| 478 | issueLat=1 |
| 479 | opClass=SimdFloatCmp |
| 480 | opLat=1 |
| 481 | |
| 482 | [system.cpu2.fuPool.FUList5.opList14] |
| 483 | type=OpDesc |
| 484 | issueLat=1 |
| 485 | opClass=SimdFloatCvt |
| 486 | opLat=1 |
| 487 | |
| 488 | [system.cpu2.fuPool.FUList5.opList15] |
| 489 | type=OpDesc |
| 490 | issueLat=1 |
| 491 | opClass=SimdFloatDiv |
| 492 | opLat=1 |
| 493 | |
| 494 | [system.cpu2.fuPool.FUList5.opList16] |
| 495 | type=OpDesc |
| 496 | issueLat=1 |
| 497 | opClass=SimdFloatMisc |
| 498 | opLat=1 |
| 499 | |
| 500 | [system.cpu2.fuPool.FUList5.opList17] |
| 501 | type=OpDesc |
| 502 | issueLat=1 |
| 503 | opClass=SimdFloatMult |
| 504 | opLat=1 |
| 505 | |
| 506 | [system.cpu2.fuPool.FUList5.opList18] |
| 507 | type=OpDesc |
| 508 | issueLat=1 |
| 509 | opClass=SimdFloatMultAcc |
| 510 | opLat=1 |
| 511 | |
| 512 | [system.cpu2.fuPool.FUList5.opList19] |
| 513 | type=OpDesc |
| 514 | issueLat=1 |
| 515 | opClass=SimdFloatSqrt |
| 516 | opLat=1 |
| 517 | |
| 518 | [system.cpu2.fuPool.FUList6] |
| 519 | type=FUDesc |
| 520 | children=opList |
| 521 | count=0 |
| 522 | opList=system.cpu2.fuPool.FUList6.opList |
| 523 | |
| 524 | [system.cpu2.fuPool.FUList6.opList] |
| 525 | type=OpDesc |
| 526 | issueLat=1 |
| 527 | opClass=MemWrite |
| 528 | opLat=1 |
| 529 | |
| 530 | [system.cpu2.fuPool.FUList7] |
| 531 | type=FUDesc |
| 532 | children=opList0 opList1 |
| 533 | count=4 |
| 534 | opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1 |
| 535 | |
| 536 | [system.cpu2.fuPool.FUList7.opList0] |
| 537 | type=OpDesc |
| 538 | issueLat=1 |
| 539 | opClass=MemRead |
| 540 | opLat=1 |
| 541 | |
| 542 | [system.cpu2.fuPool.FUList7.opList1] |
| 543 | type=OpDesc |
| 544 | issueLat=1 |
| 545 | opClass=MemWrite |
| 546 | opLat=1 |
| 547 | |
| 548 | [system.cpu2.fuPool.FUList8] |
| 549 | type=FUDesc |
| 550 | children=opList |
| 551 | count=1 |
| 552 | opList=system.cpu2.fuPool.FUList8.opList |
| 553 | |
| 554 | [system.cpu2.fuPool.FUList8.opList] |
| 555 | type=OpDesc |
| 556 | issueLat=3 |
| 557 | opClass=IprAccess |
| 558 | opLat=3 |
| 559 | |
| 560 | [system.cpu2.interrupts] |
| 561 | type=AlphaInterrupts |
| 562 | |
| 563 | [system.cpu2.isa] |
| 564 | type=AlphaISA |
| 565 | |
| 566 | [system.cpu2.itb] |
| 567 | type=AlphaTLB |
| 568 | size=48 |
| 569 | |
| 570 | [system.cpu2.tracer] |
| 571 | type=ExeTracer |
| 572 | |
| 573 | [system.disk0] |
| 574 | type=IdeDisk |
| 575 | children=image |
| 576 | delay=1000000 |
| 577 | driveID=master |
| 578 | image=system.disk0.image |
| 579 | |
| 580 | [system.disk0.image] |
| 581 | type=CowDiskImage |
| 582 | children=child |
| 583 | child=system.disk0.image.child |
| 584 | image_file= |
| 585 | read_only=false |
| 586 | table_size=65536 |
| 587 | |
| 588 | [system.disk0.image.child] |
| 589 | type=RawDiskImage |
Ali Saidi | d69f904 | 2013-04-22 13:20:33 -0400 | [diff] [blame^] | 590 | image_file=/dist/m5/system/disks/linux-latest.img |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 591 | read_only=true |
| 592 | |
| 593 | [system.disk2] |
| 594 | type=IdeDisk |
| 595 | children=image |
| 596 | delay=1000000 |
| 597 | driveID=master |
| 598 | image=system.disk2.image |
| 599 | |
| 600 | [system.disk2.image] |
| 601 | type=CowDiskImage |
| 602 | children=child |
| 603 | child=system.disk2.image.child |
| 604 | image_file= |
| 605 | read_only=false |
| 606 | table_size=65536 |
| 607 | |
| 608 | [system.disk2.image.child] |
| 609 | type=RawDiskImage |
Ali Saidi | d69f904 | 2013-04-22 13:20:33 -0400 | [diff] [blame^] | 610 | image_file=/dist/m5/system/disks/linux-bigswap2.img |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 611 | read_only=true |
| 612 | |
| 613 | [system.intrctrl] |
| 614 | type=IntrControl |
| 615 | sys=system |
| 616 | |
| 617 | [system.iobus] |
| 618 | type=NoncoherentBus |
| 619 | block_size=64 |
| 620 | clock=1000 |
| 621 | header_cycles=1 |
| 622 | use_default_range=true |
| 623 | width=8 |
| 624 | default=system.tsunami.pciconfig.pio |
| 625 | master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side |
| 626 | slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma |
| 627 | |
| 628 | [system.iocache] |
| 629 | type=BaseCache |
| 630 | addr_ranges=0:134217727 |
| 631 | assoc=8 |
| 632 | block_size=64 |
| 633 | clock=1000 |
| 634 | forward_snoops=false |
| 635 | hit_latency=50 |
| 636 | is_top_level=true |
| 637 | max_miss_count=0 |
| 638 | mshrs=20 |
| 639 | prefetch_on_access=false |
| 640 | prefetcher=Null |
| 641 | response_latency=50 |
| 642 | size=1024 |
| 643 | system=system |
| 644 | tgts_per_mshr=12 |
| 645 | two_queue=false |
| 646 | write_buffers=8 |
| 647 | cpu_side=system.iobus.master[29] |
| 648 | mem_side=system.membus.slave[2] |
| 649 | |
| 650 | [system.l2c] |
| 651 | type=BaseCache |
| 652 | addr_ranges=0:18446744073709551615 |
| 653 | assoc=8 |
| 654 | block_size=64 |
| 655 | clock=500 |
| 656 | forward_snoops=true |
| 657 | hit_latency=20 |
| 658 | is_top_level=false |
| 659 | max_miss_count=0 |
| 660 | mshrs=20 |
| 661 | prefetch_on_access=false |
| 662 | prefetcher=Null |
| 663 | response_latency=20 |
| 664 | size=4194304 |
| 665 | system=system |
| 666 | tgts_per_mshr=12 |
| 667 | two_queue=false |
| 668 | write_buffers=8 |
| 669 | cpu_side=system.toL2Bus.master[0] |
| 670 | mem_side=system.membus.slave[1] |
| 671 | |
| 672 | [system.membus] |
| 673 | type=CoherentBus |
| 674 | children=badaddr_responder |
| 675 | block_size=64 |
| 676 | clock=1000 |
| 677 | header_cycles=1 |
Ali Saidi | bd31a5d | 2013-02-15 17:40:14 -0500 | [diff] [blame] | 678 | system=system |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 679 | use_default_range=false |
| 680 | width=8 |
| 681 | default=system.membus.badaddr_responder.pio |
| 682 | master=system.bridge.slave system.physmem.port |
| 683 | slave=system.system_port system.l2c.mem_side system.iocache.mem_side |
| 684 | |
| 685 | [system.membus.badaddr_responder] |
| 686 | type=IsaFake |
| 687 | clock=1000 |
| 688 | fake_mem=false |
| 689 | pio_addr=0 |
| 690 | pio_latency=100000 |
| 691 | pio_size=8 |
| 692 | ret_bad_addr=true |
| 693 | ret_data16=65535 |
| 694 | ret_data32=4294967295 |
| 695 | ret_data64=18446744073709551615 |
| 696 | ret_data8=255 |
| 697 | system=system |
| 698 | update_data=false |
| 699 | warn_access= |
| 700 | pio=system.membus.default |
| 701 | |
| 702 | [system.physmem] |
| 703 | type=SimpleDRAM |
Ali Saidi | bd31a5d | 2013-02-15 17:40:14 -0500 | [diff] [blame] | 704 | activation_limit=4 |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 705 | addr_mapping=openmap |
| 706 | banks_per_rank=8 |
Nilay Vaish | 4646369 | 2013-03-27 18:36:21 -0500 | [diff] [blame] | 707 | channels=1 |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 708 | clock=1000 |
| 709 | conf_table_reported=false |
| 710 | in_addr_map=true |
Ali Saidi | bd31a5d | 2013-02-15 17:40:14 -0500 | [diff] [blame] | 711 | lines_per_rowbuffer=32 |
| 712 | mem_sched_policy=frfcfs |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 713 | null=false |
| 714 | page_policy=open |
| 715 | range=0:134217727 |
| 716 | ranks_per_channel=2 |
| 717 | read_buffer_size=32 |
Ali Saidi | bd31a5d | 2013-02-15 17:40:14 -0500 | [diff] [blame] | 718 | tBURST=5000 |
| 719 | tCL=13750 |
| 720 | tRCD=13750 |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 721 | tREFI=7800000 |
| 722 | tRFC=300000 |
Ali Saidi | bd31a5d | 2013-02-15 17:40:14 -0500 | [diff] [blame] | 723 | tRP=13750 |
| 724 | tWTR=7500 |
| 725 | tXAW=40000 |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 726 | write_buffer_size=32 |
| 727 | write_thresh_perc=70 |
| 728 | zero=false |
| 729 | port=system.membus.master[1] |
| 730 | |
| 731 | [system.simple_disk] |
| 732 | type=SimpleDisk |
| 733 | children=disk |
| 734 | disk=system.simple_disk.disk |
| 735 | system=system |
| 736 | |
| 737 | [system.simple_disk.disk] |
| 738 | type=RawDiskImage |
Ali Saidi | d69f904 | 2013-04-22 13:20:33 -0400 | [diff] [blame^] | 739 | image_file=/dist/m5/system/disks/linux-latest.img |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 740 | read_only=true |
| 741 | |
| 742 | [system.terminal] |
| 743 | type=Terminal |
| 744 | intr_control=system.intrctrl |
| 745 | number=0 |
| 746 | output=true |
| 747 | port=3456 |
| 748 | |
| 749 | [system.toL2Bus] |
| 750 | type=CoherentBus |
| 751 | block_size=64 |
| 752 | clock=500 |
| 753 | header_cycles=1 |
Ali Saidi | bd31a5d | 2013-02-15 17:40:14 -0500 | [diff] [blame] | 754 | system=system |
Andreas Sandberg | 5fb00e1 | 2013-01-07 13:05:52 -0500 | [diff] [blame] | 755 | use_default_range=false |
| 756 | width=8 |
| 757 | master=system.l2c.cpu_side |
| 758 | slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side |
| 759 | |
| 760 | [system.tsunami] |
| 761 | type=Tsunami |
| 762 | children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart |
| 763 | intrctrl=system.intrctrl |
| 764 | system=system |
| 765 | |
| 766 | [system.tsunami.backdoor] |
| 767 | type=AlphaBackdoor |
| 768 | clock=1000 |
| 769 | cpu=system.cpu0 |
| 770 | disk=system.simple_disk |
| 771 | pio_addr=8804682956800 |
| 772 | pio_latency=100000 |
| 773 | platform=system.tsunami |
| 774 | system=system |
| 775 | terminal=system.terminal |
| 776 | pio=system.iobus.master[24] |
| 777 | |
| 778 | [system.tsunami.cchip] |
| 779 | type=TsunamiCChip |
| 780 | clock=1000 |
| 781 | pio_addr=8803072344064 |
| 782 | pio_latency=100000 |
| 783 | system=system |
| 784 | tsunami=system.tsunami |
| 785 | pio=system.iobus.master[0] |
| 786 | |
| 787 | [system.tsunami.ethernet] |
| 788 | type=NSGigE |
| 789 | BAR0=1 |
| 790 | BAR0LegacyIO=false |
| 791 | BAR0Size=256 |
| 792 | BAR1=0 |
| 793 | BAR1LegacyIO=false |
| 794 | BAR1Size=4096 |
| 795 | BAR2=0 |
| 796 | BAR2LegacyIO=false |
| 797 | BAR2Size=0 |
| 798 | BAR3=0 |
| 799 | BAR3LegacyIO=false |
| 800 | BAR3Size=0 |
| 801 | BAR4=0 |
| 802 | BAR4LegacyIO=false |
| 803 | BAR4Size=0 |
| 804 | BAR5=0 |
| 805 | BAR5LegacyIO=false |
| 806 | BAR5Size=0 |
| 807 | BIST=0 |
| 808 | CacheLineSize=0 |
| 809 | CardbusCIS=0 |
| 810 | ClassCode=2 |
| 811 | Command=0 |
| 812 | DeviceID=34 |
| 813 | ExpansionROM=0 |
| 814 | HeaderType=0 |
| 815 | InterruptLine=30 |
| 816 | InterruptPin=1 |
| 817 | LatencyTimer=0 |
| 818 | MaximumLatency=52 |
| 819 | MinimumGrant=176 |
| 820 | ProgIF=0 |
| 821 | Revision=0 |
| 822 | Status=656 |
| 823 | SubClassCode=0 |
| 824 | SubsystemID=0 |
| 825 | SubsystemVendorID=0 |
| 826 | VendorID=4107 |
| 827 | clock=2000 |
| 828 | config_latency=20000 |
| 829 | dma_data_free=false |
| 830 | dma_desc_free=false |
| 831 | dma_no_allocate=true |
| 832 | dma_read_delay=0 |
| 833 | dma_read_factor=0 |
| 834 | dma_write_delay=0 |
| 835 | dma_write_factor=0 |
| 836 | hardware_address=00:90:00:00:00:01 |
| 837 | intr_delay=10000000 |
| 838 | pci_bus=0 |
| 839 | pci_dev=1 |
| 840 | pci_func=0 |
| 841 | pio_latency=30000 |
| 842 | platform=system.tsunami |
| 843 | rss=false |
| 844 | rx_delay=1000000 |
| 845 | rx_fifo_size=524288 |
| 846 | rx_filter=true |
| 847 | rx_thread=false |
| 848 | system=system |
| 849 | tx_delay=1000000 |
| 850 | tx_fifo_size=524288 |
| 851 | tx_thread=false |
| 852 | config=system.iobus.master[28] |
| 853 | dma=system.iobus.slave[2] |
| 854 | pio=system.iobus.master[27] |
| 855 | |
| 856 | [system.tsunami.fake_OROM] |
| 857 | type=IsaFake |
| 858 | clock=1000 |
| 859 | fake_mem=false |
| 860 | pio_addr=8796093677568 |
| 861 | pio_latency=100000 |
| 862 | pio_size=393216 |
| 863 | ret_bad_addr=false |
| 864 | ret_data16=65535 |
| 865 | ret_data32=4294967295 |
| 866 | ret_data64=18446744073709551615 |
| 867 | ret_data8=255 |
| 868 | system=system |
| 869 | update_data=false |
| 870 | warn_access= |
| 871 | pio=system.iobus.master[8] |
| 872 | |
| 873 | [system.tsunami.fake_ata0] |
| 874 | type=IsaFake |
| 875 | clock=1000 |
| 876 | fake_mem=false |
| 877 | pio_addr=8804615848432 |
| 878 | pio_latency=100000 |
| 879 | pio_size=8 |
| 880 | ret_bad_addr=false |
| 881 | ret_data16=65535 |
| 882 | ret_data32=4294967295 |
| 883 | ret_data64=18446744073709551615 |
| 884 | ret_data8=255 |
| 885 | system=system |
| 886 | update_data=false |
| 887 | warn_access= |
| 888 | pio=system.iobus.master[19] |
| 889 | |
| 890 | [system.tsunami.fake_ata1] |
| 891 | type=IsaFake |
| 892 | clock=1000 |
| 893 | fake_mem=false |
| 894 | pio_addr=8804615848304 |
| 895 | pio_latency=100000 |
| 896 | pio_size=8 |
| 897 | ret_bad_addr=false |
| 898 | ret_data16=65535 |
| 899 | ret_data32=4294967295 |
| 900 | ret_data64=18446744073709551615 |
| 901 | ret_data8=255 |
| 902 | system=system |
| 903 | update_data=false |
| 904 | warn_access= |
| 905 | pio=system.iobus.master[20] |
| 906 | |
| 907 | [system.tsunami.fake_pnp_addr] |
| 908 | type=IsaFake |
| 909 | clock=1000 |
| 910 | fake_mem=false |
| 911 | pio_addr=8804615848569 |
| 912 | pio_latency=100000 |
| 913 | pio_size=8 |
| 914 | ret_bad_addr=false |
| 915 | ret_data16=65535 |
| 916 | ret_data32=4294967295 |
| 917 | ret_data64=18446744073709551615 |
| 918 | ret_data8=255 |
| 919 | system=system |
| 920 | update_data=false |
| 921 | warn_access= |
| 922 | pio=system.iobus.master[9] |
| 923 | |
| 924 | [system.tsunami.fake_pnp_read0] |
| 925 | type=IsaFake |
| 926 | clock=1000 |
| 927 | fake_mem=false |
| 928 | pio_addr=8804615848451 |
| 929 | pio_latency=100000 |
| 930 | pio_size=8 |
| 931 | ret_bad_addr=false |
| 932 | ret_data16=65535 |
| 933 | ret_data32=4294967295 |
| 934 | ret_data64=18446744073709551615 |
| 935 | ret_data8=255 |
| 936 | system=system |
| 937 | update_data=false |
| 938 | warn_access= |
| 939 | pio=system.iobus.master[11] |
| 940 | |
| 941 | [system.tsunami.fake_pnp_read1] |
| 942 | type=IsaFake |
| 943 | clock=1000 |
| 944 | fake_mem=false |
| 945 | pio_addr=8804615848515 |
| 946 | pio_latency=100000 |
| 947 | pio_size=8 |
| 948 | ret_bad_addr=false |
| 949 | ret_data16=65535 |
| 950 | ret_data32=4294967295 |
| 951 | ret_data64=18446744073709551615 |
| 952 | ret_data8=255 |
| 953 | system=system |
| 954 | update_data=false |
| 955 | warn_access= |
| 956 | pio=system.iobus.master[12] |
| 957 | |
| 958 | [system.tsunami.fake_pnp_read2] |
| 959 | type=IsaFake |
| 960 | clock=1000 |
| 961 | fake_mem=false |
| 962 | pio_addr=8804615848579 |
| 963 | pio_latency=100000 |
| 964 | pio_size=8 |
| 965 | ret_bad_addr=false |
| 966 | ret_data16=65535 |
| 967 | ret_data32=4294967295 |
| 968 | ret_data64=18446744073709551615 |
| 969 | ret_data8=255 |
| 970 | system=system |
| 971 | update_data=false |
| 972 | warn_access= |
| 973 | pio=system.iobus.master[13] |
| 974 | |
| 975 | [system.tsunami.fake_pnp_read3] |
| 976 | type=IsaFake |
| 977 | clock=1000 |
| 978 | fake_mem=false |
| 979 | pio_addr=8804615848643 |
| 980 | pio_latency=100000 |
| 981 | pio_size=8 |
| 982 | ret_bad_addr=false |
| 983 | ret_data16=65535 |
| 984 | ret_data32=4294967295 |
| 985 | ret_data64=18446744073709551615 |
| 986 | ret_data8=255 |
| 987 | system=system |
| 988 | update_data=false |
| 989 | warn_access= |
| 990 | pio=system.iobus.master[14] |
| 991 | |
| 992 | [system.tsunami.fake_pnp_read4] |
| 993 | type=IsaFake |
| 994 | clock=1000 |
| 995 | fake_mem=false |
| 996 | pio_addr=8804615848707 |
| 997 | pio_latency=100000 |
| 998 | pio_size=8 |
| 999 | ret_bad_addr=false |
| 1000 | ret_data16=65535 |
| 1001 | ret_data32=4294967295 |
| 1002 | ret_data64=18446744073709551615 |
| 1003 | ret_data8=255 |
| 1004 | system=system |
| 1005 | update_data=false |
| 1006 | warn_access= |
| 1007 | pio=system.iobus.master[15] |
| 1008 | |
| 1009 | [system.tsunami.fake_pnp_read5] |
| 1010 | type=IsaFake |
| 1011 | clock=1000 |
| 1012 | fake_mem=false |
| 1013 | pio_addr=8804615848771 |
| 1014 | pio_latency=100000 |
| 1015 | pio_size=8 |
| 1016 | ret_bad_addr=false |
| 1017 | ret_data16=65535 |
| 1018 | ret_data32=4294967295 |
| 1019 | ret_data64=18446744073709551615 |
| 1020 | ret_data8=255 |
| 1021 | system=system |
| 1022 | update_data=false |
| 1023 | warn_access= |
| 1024 | pio=system.iobus.master[16] |
| 1025 | |
| 1026 | [system.tsunami.fake_pnp_read6] |
| 1027 | type=IsaFake |
| 1028 | clock=1000 |
| 1029 | fake_mem=false |
| 1030 | pio_addr=8804615848835 |
| 1031 | pio_latency=100000 |
| 1032 | pio_size=8 |
| 1033 | ret_bad_addr=false |
| 1034 | ret_data16=65535 |
| 1035 | ret_data32=4294967295 |
| 1036 | ret_data64=18446744073709551615 |
| 1037 | ret_data8=255 |
| 1038 | system=system |
| 1039 | update_data=false |
| 1040 | warn_access= |
| 1041 | pio=system.iobus.master[17] |
| 1042 | |
| 1043 | [system.tsunami.fake_pnp_read7] |
| 1044 | type=IsaFake |
| 1045 | clock=1000 |
| 1046 | fake_mem=false |
| 1047 | pio_addr=8804615848899 |
| 1048 | pio_latency=100000 |
| 1049 | pio_size=8 |
| 1050 | ret_bad_addr=false |
| 1051 | ret_data16=65535 |
| 1052 | ret_data32=4294967295 |
| 1053 | ret_data64=18446744073709551615 |
| 1054 | ret_data8=255 |
| 1055 | system=system |
| 1056 | update_data=false |
| 1057 | warn_access= |
| 1058 | pio=system.iobus.master[18] |
| 1059 | |
| 1060 | [system.tsunami.fake_pnp_write] |
| 1061 | type=IsaFake |
| 1062 | clock=1000 |
| 1063 | fake_mem=false |
| 1064 | pio_addr=8804615850617 |
| 1065 | pio_latency=100000 |
| 1066 | pio_size=8 |
| 1067 | ret_bad_addr=false |
| 1068 | ret_data16=65535 |
| 1069 | ret_data32=4294967295 |
| 1070 | ret_data64=18446744073709551615 |
| 1071 | ret_data8=255 |
| 1072 | system=system |
| 1073 | update_data=false |
| 1074 | warn_access= |
| 1075 | pio=system.iobus.master[10] |
| 1076 | |
| 1077 | [system.tsunami.fake_ppc] |
| 1078 | type=IsaFake |
| 1079 | clock=1000 |
| 1080 | fake_mem=false |
| 1081 | pio_addr=8804615848891 |
| 1082 | pio_latency=100000 |
| 1083 | pio_size=8 |
| 1084 | ret_bad_addr=false |
| 1085 | ret_data16=65535 |
| 1086 | ret_data32=4294967295 |
| 1087 | ret_data64=18446744073709551615 |
| 1088 | ret_data8=255 |
| 1089 | system=system |
| 1090 | update_data=false |
| 1091 | warn_access= |
| 1092 | pio=system.iobus.master[7] |
| 1093 | |
| 1094 | [system.tsunami.fake_sm_chip] |
| 1095 | type=IsaFake |
| 1096 | clock=1000 |
| 1097 | fake_mem=false |
| 1098 | pio_addr=8804615848816 |
| 1099 | pio_latency=100000 |
| 1100 | pio_size=8 |
| 1101 | ret_bad_addr=false |
| 1102 | ret_data16=65535 |
| 1103 | ret_data32=4294967295 |
| 1104 | ret_data64=18446744073709551615 |
| 1105 | ret_data8=255 |
| 1106 | system=system |
| 1107 | update_data=false |
| 1108 | warn_access= |
| 1109 | pio=system.iobus.master[2] |
| 1110 | |
| 1111 | [system.tsunami.fake_uart1] |
| 1112 | type=IsaFake |
| 1113 | clock=1000 |
| 1114 | fake_mem=false |
| 1115 | pio_addr=8804615848696 |
| 1116 | pio_latency=100000 |
| 1117 | pio_size=8 |
| 1118 | ret_bad_addr=false |
| 1119 | ret_data16=65535 |
| 1120 | ret_data32=4294967295 |
| 1121 | ret_data64=18446744073709551615 |
| 1122 | ret_data8=255 |
| 1123 | system=system |
| 1124 | update_data=false |
| 1125 | warn_access= |
| 1126 | pio=system.iobus.master[3] |
| 1127 | |
| 1128 | [system.tsunami.fake_uart2] |
| 1129 | type=IsaFake |
| 1130 | clock=1000 |
| 1131 | fake_mem=false |
| 1132 | pio_addr=8804615848936 |
| 1133 | pio_latency=100000 |
| 1134 | pio_size=8 |
| 1135 | ret_bad_addr=false |
| 1136 | ret_data16=65535 |
| 1137 | ret_data32=4294967295 |
| 1138 | ret_data64=18446744073709551615 |
| 1139 | ret_data8=255 |
| 1140 | system=system |
| 1141 | update_data=false |
| 1142 | warn_access= |
| 1143 | pio=system.iobus.master[4] |
| 1144 | |
| 1145 | [system.tsunami.fake_uart3] |
| 1146 | type=IsaFake |
| 1147 | clock=1000 |
| 1148 | fake_mem=false |
| 1149 | pio_addr=8804615848680 |
| 1150 | pio_latency=100000 |
| 1151 | pio_size=8 |
| 1152 | ret_bad_addr=false |
| 1153 | ret_data16=65535 |
| 1154 | ret_data32=4294967295 |
| 1155 | ret_data64=18446744073709551615 |
| 1156 | ret_data8=255 |
| 1157 | system=system |
| 1158 | update_data=false |
| 1159 | warn_access= |
| 1160 | pio=system.iobus.master[5] |
| 1161 | |
| 1162 | [system.tsunami.fake_uart4] |
| 1163 | type=IsaFake |
| 1164 | clock=1000 |
| 1165 | fake_mem=false |
| 1166 | pio_addr=8804615848944 |
| 1167 | pio_latency=100000 |
| 1168 | pio_size=8 |
| 1169 | ret_bad_addr=false |
| 1170 | ret_data16=65535 |
| 1171 | ret_data32=4294967295 |
| 1172 | ret_data64=18446744073709551615 |
| 1173 | ret_data8=255 |
| 1174 | system=system |
| 1175 | update_data=false |
| 1176 | warn_access= |
| 1177 | pio=system.iobus.master[6] |
| 1178 | |
| 1179 | [system.tsunami.fb] |
| 1180 | type=BadDevice |
| 1181 | clock=1000 |
| 1182 | devicename=FrameBuffer |
| 1183 | pio_addr=8804615848912 |
| 1184 | pio_latency=100000 |
| 1185 | system=system |
| 1186 | pio=system.iobus.master[21] |
| 1187 | |
| 1188 | [system.tsunami.ide] |
| 1189 | type=IdeController |
| 1190 | BAR0=1 |
| 1191 | BAR0LegacyIO=false |
| 1192 | BAR0Size=8 |
| 1193 | BAR1=1 |
| 1194 | BAR1LegacyIO=false |
| 1195 | BAR1Size=4 |
| 1196 | BAR2=1 |
| 1197 | BAR2LegacyIO=false |
| 1198 | BAR2Size=8 |
| 1199 | BAR3=1 |
| 1200 | BAR3LegacyIO=false |
| 1201 | BAR3Size=4 |
| 1202 | BAR4=1 |
| 1203 | BAR4LegacyIO=false |
| 1204 | BAR4Size=16 |
| 1205 | BAR5=1 |
| 1206 | BAR5LegacyIO=false |
| 1207 | BAR5Size=0 |
| 1208 | BIST=0 |
| 1209 | CacheLineSize=0 |
| 1210 | CardbusCIS=0 |
| 1211 | ClassCode=1 |
| 1212 | Command=0 |
| 1213 | DeviceID=28945 |
| 1214 | ExpansionROM=0 |
| 1215 | HeaderType=0 |
| 1216 | InterruptLine=31 |
| 1217 | InterruptPin=1 |
| 1218 | LatencyTimer=0 |
| 1219 | MaximumLatency=0 |
| 1220 | MinimumGrant=0 |
| 1221 | ProgIF=133 |
| 1222 | Revision=0 |
| 1223 | Status=640 |
| 1224 | SubClassCode=1 |
| 1225 | SubsystemID=0 |
| 1226 | SubsystemVendorID=0 |
| 1227 | VendorID=32902 |
| 1228 | clock=1000 |
| 1229 | config_latency=20000 |
| 1230 | ctrl_offset=0 |
| 1231 | disks=system.disk0 system.disk2 |
| 1232 | io_shift=0 |
| 1233 | pci_bus=0 |
| 1234 | pci_dev=0 |
| 1235 | pci_func=0 |
| 1236 | pio_latency=30000 |
| 1237 | platform=system.tsunami |
| 1238 | system=system |
| 1239 | config=system.iobus.master[26] |
| 1240 | dma=system.iobus.slave[1] |
| 1241 | pio=system.iobus.master[25] |
| 1242 | |
| 1243 | [system.tsunami.io] |
| 1244 | type=TsunamiIO |
| 1245 | clock=1000 |
| 1246 | frequency=976562500 |
| 1247 | pio_addr=8804615847936 |
| 1248 | pio_latency=100000 |
| 1249 | system=system |
| 1250 | time=Thu Jan 1 00:00:00 2009 |
| 1251 | tsunami=system.tsunami |
| 1252 | year_is_bcd=false |
| 1253 | pio=system.iobus.master[22] |
| 1254 | |
| 1255 | [system.tsunami.pchip] |
| 1256 | type=TsunamiPChip |
| 1257 | clock=1000 |
| 1258 | pio_addr=8802535473152 |
| 1259 | pio_latency=100000 |
| 1260 | system=system |
| 1261 | tsunami=system.tsunami |
| 1262 | pio=system.iobus.master[1] |
| 1263 | |
| 1264 | [system.tsunami.pciconfig] |
| 1265 | type=PciConfigAll |
| 1266 | bus=0 |
| 1267 | clock=1000 |
| 1268 | pio_latency=30000 |
| 1269 | platform=system.tsunami |
| 1270 | size=16777216 |
| 1271 | system=system |
| 1272 | pio=system.iobus.default |
| 1273 | |
| 1274 | [system.tsunami.uart] |
| 1275 | type=Uart8250 |
| 1276 | clock=1000 |
| 1277 | pio_addr=8804615848952 |
| 1278 | pio_latency=100000 |
| 1279 | platform=system.tsunami |
| 1280 | system=system |
| 1281 | terminal=system.terminal |
| 1282 | pio=system.iobus.master[23] |
| 1283 | |