blob: 84c3aa0cef54b0bbf5555d0924b27d5d85dfc2a4 [file] [log] [blame]
Andreas Sandberg5fb00e12013-01-07 13:05:52 -05001[root]
2type=Root
3children=system
4full_system=true
5time_sync_enable=false
6time_sync_period=100000000000
7time_sync_spin_threshold=100000000
8
9[system]
10type=LinuxAlphaSystem
11children=bridge cpu0 cpu1 cpu2 disk0 disk2 intrctrl iobus iocache l2c membus physmem simple_disk terminal toL2Bus tsunami
12boot_cpu_frequency=500
13boot_osflags=root=/dev/hda1 console=ttyS0
14clock=1000
Ali Saidid69f9042013-04-22 13:20:33 -040015console=/dist/m5/system/binaries/console
Andreas Sandberg5fb00e12013-01-07 13:05:52 -050016init_param=0
Ali Saidid69f9042013-04-22 13:20:33 -040017kernel=/dist/m5/system/binaries/vmlinux
Andreas Sandberg5fb00e12013-01-07 13:05:52 -050018load_addr_mask=1099511627775
19mem_mode=atomic
20mem_ranges=0:134217727
21memories=system.physmem
22num_work_ids=16
Ali Saidid69f9042013-04-22 13:20:33 -040023pal=/dist/m5/system/binaries/ts_osfpal
Andreas Sandberg5fb00e12013-01-07 13:05:52 -050024readfile=tests/halt.sh
25symbolfile=
26system_rev=1024
27system_type=34
28work_begin_ckpt_count=0
29work_begin_cpu_id_exit=-1
30work_begin_exit_count=0
31work_cpus_ckpt_count=0
32work_end_ckpt_count=0
33work_end_exit_count=0
34work_item_id=-1
35system_port=system.membus.slave[0]
36
37[system.bridge]
38type=Bridge
39clock=1000
40delay=50000
41ranges=8796093022208:18446744073709551615
42req_size=16
43resp_size=16
44master=system.iobus.slave[0]
45slave=system.membus.master[0]
46
47[system.cpu0]
48type=AtomicSimpleCPU
49children=dcache dtb icache interrupts isa itb tracer
Nilay Vaish9bc132e2013-01-24 12:29:00 -060050branchPred=Null
Andreas Sandberg5fb00e12013-01-07 13:05:52 -050051checker=Null
52clock=500
53cpu_id=0
54do_checkpoint_insts=true
55do_quiesce=true
56do_statistics_insts=true
57dtb=system.cpu0.dtb
58fastmem=false
59function_trace=false
60function_trace_start=0
61interrupts=system.cpu0.interrupts
62isa=system.cpu0.isa
63itb=system.cpu0.itb
64max_insts_all_threads=0
65max_insts_any_thread=0
66max_loads_all_threads=0
67max_loads_any_thread=0
68numThreads=1
69profile=0
70progress_interval=0
Ali Saidid69f9042013-04-22 13:20:33 -040071simpoint_interval=100000000
72simpoint_profile=false
73simpoint_profile_file=simpoint.bb.gz
74simpoint_start_insts=
Andreas Sandberg5fb00e12013-01-07 13:05:52 -050075simulate_data_stalls=false
76simulate_inst_stalls=false
77switched_out=false
78system=system
79tracer=system.cpu0.tracer
80width=1
81workload=
82dcache_port=system.cpu0.dcache.cpu_side
83icache_port=system.cpu0.icache.cpu_side
84
85[system.cpu0.dcache]
86type=BaseCache
87addr_ranges=0:18446744073709551615
88assoc=4
89block_size=64
90clock=500
91forward_snoops=true
92hit_latency=2
93is_top_level=true
94max_miss_count=0
95mshrs=4
96prefetch_on_access=false
97prefetcher=Null
98response_latency=2
99size=32768
100system=system
101tgts_per_mshr=20
102two_queue=false
103write_buffers=8
104cpu_side=system.cpu0.dcache_port
105mem_side=system.toL2Bus.slave[1]
106
107[system.cpu0.dtb]
108type=AlphaTLB
109size=64
110
111[system.cpu0.icache]
112type=BaseCache
113addr_ranges=0:18446744073709551615
114assoc=1
115block_size=64
116clock=500
117forward_snoops=true
118hit_latency=2
119is_top_level=true
120max_miss_count=0
121mshrs=4
122prefetch_on_access=false
123prefetcher=Null
124response_latency=2
125size=32768
126system=system
127tgts_per_mshr=20
128two_queue=false
129write_buffers=8
130cpu_side=system.cpu0.icache_port
131mem_side=system.toL2Bus.slave[0]
132
133[system.cpu0.interrupts]
134type=AlphaInterrupts
135
136[system.cpu0.isa]
137type=AlphaISA
138
139[system.cpu0.itb]
140type=AlphaTLB
141size=48
142
143[system.cpu0.tracer]
144type=ExeTracer
145
146[system.cpu1]
147type=TimingSimpleCPU
148children=dtb interrupts isa itb tracer
Nilay Vaish9bc132e2013-01-24 12:29:00 -0600149branchPred=Null
Andreas Sandberg5fb00e12013-01-07 13:05:52 -0500150checker=Null
151clock=500
152cpu_id=0
153do_checkpoint_insts=true
154do_quiesce=true
155do_statistics_insts=true
156dtb=system.cpu1.dtb
157function_trace=false
158function_trace_start=0
159interrupts=system.cpu1.interrupts
160isa=system.cpu1.isa
161itb=system.cpu1.itb
162max_insts_all_threads=0
163max_insts_any_thread=0
164max_loads_all_threads=0
165max_loads_any_thread=0
166numThreads=1
167profile=0
168progress_interval=0
Ali Saidid69f9042013-04-22 13:20:33 -0400169simpoint_start_insts=
Andreas Sandberg5fb00e12013-01-07 13:05:52 -0500170switched_out=true
171system=system
172tracer=system.cpu1.tracer
173workload=
174
175[system.cpu1.dtb]
176type=AlphaTLB
177size=64
178
179[system.cpu1.interrupts]
180type=AlphaInterrupts
181
182[system.cpu1.isa]
183type=AlphaISA
184
185[system.cpu1.itb]
186type=AlphaTLB
187size=48
188
189[system.cpu1.tracer]
190type=ExeTracer
191
192[system.cpu2]
193type=DerivO3CPU
Nilay Vaish9bc132e2013-01-24 12:29:00 -0600194children=branchPred dtb fuPool interrupts isa itb tracer
Andreas Sandberg5fb00e12013-01-07 13:05:52 -0500195LFSTSize=1024
196LQEntries=32
197LSQCheckLoads=true
198LSQDepCheckShift=4
Andreas Sandberg5fb00e12013-01-07 13:05:52 -0500199SQEntries=32
200SSITSize=1024
201activity=0
202backComSize=5
Nilay Vaish9bc132e2013-01-24 12:29:00 -0600203branchPred=system.cpu2.branchPred
Andreas Sandberg5fb00e12013-01-07 13:05:52 -0500204cachePorts=200
205checker=Null
Andreas Sandberg5fb00e12013-01-07 13:05:52 -0500206clock=500
207commitToDecodeDelay=1
208commitToFetchDelay=1
209commitToIEWDelay=1
210commitToRenameDelay=1
211commitWidth=8
212cpu_id=0
213decodeToFetchDelay=1
214decodeToRenameDelay=1
215decodeWidth=8
216dispatchWidth=8
217do_checkpoint_insts=true
218do_quiesce=true
219do_statistics_insts=true
220dtb=system.cpu2.dtb
221fetchToDecodeDelay=1
222fetchTrapLatency=1
223fetchWidth=8
224forwardComSize=5
225fuPool=system.cpu2.fuPool
226function_trace=false
227function_trace_start=0
Andreas Sandberg5fb00e12013-01-07 13:05:52 -0500228iewToCommitDelay=1
229iewToDecodeDelay=1
230iewToFetchDelay=1
231iewToRenameDelay=1
Andreas Sandberg5fb00e12013-01-07 13:05:52 -0500232interrupts=system.cpu2.interrupts
233isa=system.cpu2.isa
234issueToExecuteDelay=1
235issueWidth=8
236itb=system.cpu2.itb
Andreas Sandberg5fb00e12013-01-07 13:05:52 -0500237max_insts_all_threads=0
238max_insts_any_thread=0
239max_loads_all_threads=0
240max_loads_any_thread=0
241needsTSO=false
242numIQEntries=64
243numPhysFloatRegs=256
244numPhysIntRegs=256
245numROBEntries=192
246numRobs=1
247numThreads=1
Andreas Sandberg5fb00e12013-01-07 13:05:52 -0500248profile=0
249progress_interval=0
250renameToDecodeDelay=1
251renameToFetchDelay=1
252renameToIEWDelay=2
253renameToROBDelay=1
254renameWidth=8
Ali Saidid69f9042013-04-22 13:20:33 -0400255simpoint_start_insts=
Andreas Sandberg5fb00e12013-01-07 13:05:52 -0500256smtCommitPolicy=RoundRobin
257smtFetchPolicy=SingleThread
258smtIQPolicy=Partitioned
259smtIQThreshold=100
260smtLSQPolicy=Partitioned
261smtLSQThreshold=100
262smtNumFetchingThreads=1
263smtROBPolicy=Partitioned
264smtROBThreshold=100
265squashWidth=8
266store_set_clear_period=250000
267switched_out=true
268system=system
269tracer=system.cpu2.tracer
270trapLatency=13
271wbDepth=1
272wbWidth=8
273workload=
274
Nilay Vaish9bc132e2013-01-24 12:29:00 -0600275[system.cpu2.branchPred]
276type=BranchPredictor
277BTBEntries=4096
278BTBTagSize=16
279RASSize=16
280choiceCtrBits=2
281choicePredictorSize=8192
282globalCtrBits=2
283globalHistoryBits=13
284globalPredictorSize=8192
285instShiftAmt=2
286localCtrBits=2
287localHistoryBits=11
288localHistoryTableSize=2048
289localPredictorSize=2048
290numThreads=1
291predType=tournament
292
Andreas Sandberg5fb00e12013-01-07 13:05:52 -0500293[system.cpu2.dtb]
294type=AlphaTLB
295size=64
296
297[system.cpu2.fuPool]
298type=FUPool
299children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
300FUList=system.cpu2.fuPool.FUList0 system.cpu2.fuPool.FUList1 system.cpu2.fuPool.FUList2 system.cpu2.fuPool.FUList3 system.cpu2.fuPool.FUList4 system.cpu2.fuPool.FUList5 system.cpu2.fuPool.FUList6 system.cpu2.fuPool.FUList7 system.cpu2.fuPool.FUList8
301
302[system.cpu2.fuPool.FUList0]
303type=FUDesc
304children=opList
305count=6
306opList=system.cpu2.fuPool.FUList0.opList
307
308[system.cpu2.fuPool.FUList0.opList]
309type=OpDesc
310issueLat=1
311opClass=IntAlu
312opLat=1
313
314[system.cpu2.fuPool.FUList1]
315type=FUDesc
316children=opList0 opList1
317count=2
318opList=system.cpu2.fuPool.FUList1.opList0 system.cpu2.fuPool.FUList1.opList1
319
320[system.cpu2.fuPool.FUList1.opList0]
321type=OpDesc
322issueLat=1
323opClass=IntMult
324opLat=3
325
326[system.cpu2.fuPool.FUList1.opList1]
327type=OpDesc
328issueLat=19
329opClass=IntDiv
330opLat=20
331
332[system.cpu2.fuPool.FUList2]
333type=FUDesc
334children=opList0 opList1 opList2
335count=4
336opList=system.cpu2.fuPool.FUList2.opList0 system.cpu2.fuPool.FUList2.opList1 system.cpu2.fuPool.FUList2.opList2
337
338[system.cpu2.fuPool.FUList2.opList0]
339type=OpDesc
340issueLat=1
341opClass=FloatAdd
342opLat=2
343
344[system.cpu2.fuPool.FUList2.opList1]
345type=OpDesc
346issueLat=1
347opClass=FloatCmp
348opLat=2
349
350[system.cpu2.fuPool.FUList2.opList2]
351type=OpDesc
352issueLat=1
353opClass=FloatCvt
354opLat=2
355
356[system.cpu2.fuPool.FUList3]
357type=FUDesc
358children=opList0 opList1 opList2
359count=2
360opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2
361
362[system.cpu2.fuPool.FUList3.opList0]
363type=OpDesc
364issueLat=1
365opClass=FloatMult
366opLat=4
367
368[system.cpu2.fuPool.FUList3.opList1]
369type=OpDesc
370issueLat=12
371opClass=FloatDiv
372opLat=12
373
374[system.cpu2.fuPool.FUList3.opList2]
375type=OpDesc
376issueLat=24
377opClass=FloatSqrt
378opLat=24
379
380[system.cpu2.fuPool.FUList4]
381type=FUDesc
382children=opList
383count=0
384opList=system.cpu2.fuPool.FUList4.opList
385
386[system.cpu2.fuPool.FUList4.opList]
387type=OpDesc
388issueLat=1
389opClass=MemRead
390opLat=1
391
392[system.cpu2.fuPool.FUList5]
393type=FUDesc
394children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
395count=4
396opList=system.cpu2.fuPool.FUList5.opList00 system.cpu2.fuPool.FUList5.opList01 system.cpu2.fuPool.FUList5.opList02 system.cpu2.fuPool.FUList5.opList03 system.cpu2.fuPool.FUList5.opList04 system.cpu2.fuPool.FUList5.opList05 system.cpu2.fuPool.FUList5.opList06 system.cpu2.fuPool.FUList5.opList07 system.cpu2.fuPool.FUList5.opList08 system.cpu2.fuPool.FUList5.opList09 system.cpu2.fuPool.FUList5.opList10 system.cpu2.fuPool.FUList5.opList11 system.cpu2.fuPool.FUList5.opList12 system.cpu2.fuPool.FUList5.opList13 system.cpu2.fuPool.FUList5.opList14 system.cpu2.fuPool.FUList5.opList15 system.cpu2.fuPool.FUList5.opList16 system.cpu2.fuPool.FUList5.opList17 system.cpu2.fuPool.FUList5.opList18 system.cpu2.fuPool.FUList5.opList19
397
398[system.cpu2.fuPool.FUList5.opList00]
399type=OpDesc
400issueLat=1
401opClass=SimdAdd
402opLat=1
403
404[system.cpu2.fuPool.FUList5.opList01]
405type=OpDesc
406issueLat=1
407opClass=SimdAddAcc
408opLat=1
409
410[system.cpu2.fuPool.FUList5.opList02]
411type=OpDesc
412issueLat=1
413opClass=SimdAlu
414opLat=1
415
416[system.cpu2.fuPool.FUList5.opList03]
417type=OpDesc
418issueLat=1
419opClass=SimdCmp
420opLat=1
421
422[system.cpu2.fuPool.FUList5.opList04]
423type=OpDesc
424issueLat=1
425opClass=SimdCvt
426opLat=1
427
428[system.cpu2.fuPool.FUList5.opList05]
429type=OpDesc
430issueLat=1
431opClass=SimdMisc
432opLat=1
433
434[system.cpu2.fuPool.FUList5.opList06]
435type=OpDesc
436issueLat=1
437opClass=SimdMult
438opLat=1
439
440[system.cpu2.fuPool.FUList5.opList07]
441type=OpDesc
442issueLat=1
443opClass=SimdMultAcc
444opLat=1
445
446[system.cpu2.fuPool.FUList5.opList08]
447type=OpDesc
448issueLat=1
449opClass=SimdShift
450opLat=1
451
452[system.cpu2.fuPool.FUList5.opList09]
453type=OpDesc
454issueLat=1
455opClass=SimdShiftAcc
456opLat=1
457
458[system.cpu2.fuPool.FUList5.opList10]
459type=OpDesc
460issueLat=1
461opClass=SimdSqrt
462opLat=1
463
464[system.cpu2.fuPool.FUList5.opList11]
465type=OpDesc
466issueLat=1
467opClass=SimdFloatAdd
468opLat=1
469
470[system.cpu2.fuPool.FUList5.opList12]
471type=OpDesc
472issueLat=1
473opClass=SimdFloatAlu
474opLat=1
475
476[system.cpu2.fuPool.FUList5.opList13]
477type=OpDesc
478issueLat=1
479opClass=SimdFloatCmp
480opLat=1
481
482[system.cpu2.fuPool.FUList5.opList14]
483type=OpDesc
484issueLat=1
485opClass=SimdFloatCvt
486opLat=1
487
488[system.cpu2.fuPool.FUList5.opList15]
489type=OpDesc
490issueLat=1
491opClass=SimdFloatDiv
492opLat=1
493
494[system.cpu2.fuPool.FUList5.opList16]
495type=OpDesc
496issueLat=1
497opClass=SimdFloatMisc
498opLat=1
499
500[system.cpu2.fuPool.FUList5.opList17]
501type=OpDesc
502issueLat=1
503opClass=SimdFloatMult
504opLat=1
505
506[system.cpu2.fuPool.FUList5.opList18]
507type=OpDesc
508issueLat=1
509opClass=SimdFloatMultAcc
510opLat=1
511
512[system.cpu2.fuPool.FUList5.opList19]
513type=OpDesc
514issueLat=1
515opClass=SimdFloatSqrt
516opLat=1
517
518[system.cpu2.fuPool.FUList6]
519type=FUDesc
520children=opList
521count=0
522opList=system.cpu2.fuPool.FUList6.opList
523
524[system.cpu2.fuPool.FUList6.opList]
525type=OpDesc
526issueLat=1
527opClass=MemWrite
528opLat=1
529
530[system.cpu2.fuPool.FUList7]
531type=FUDesc
532children=opList0 opList1
533count=4
534opList=system.cpu2.fuPool.FUList7.opList0 system.cpu2.fuPool.FUList7.opList1
535
536[system.cpu2.fuPool.FUList7.opList0]
537type=OpDesc
538issueLat=1
539opClass=MemRead
540opLat=1
541
542[system.cpu2.fuPool.FUList7.opList1]
543type=OpDesc
544issueLat=1
545opClass=MemWrite
546opLat=1
547
548[system.cpu2.fuPool.FUList8]
549type=FUDesc
550children=opList
551count=1
552opList=system.cpu2.fuPool.FUList8.opList
553
554[system.cpu2.fuPool.FUList8.opList]
555type=OpDesc
556issueLat=3
557opClass=IprAccess
558opLat=3
559
560[system.cpu2.interrupts]
561type=AlphaInterrupts
562
563[system.cpu2.isa]
564type=AlphaISA
565
566[system.cpu2.itb]
567type=AlphaTLB
568size=48
569
570[system.cpu2.tracer]
571type=ExeTracer
572
573[system.disk0]
574type=IdeDisk
575children=image
576delay=1000000
577driveID=master
578image=system.disk0.image
579
580[system.disk0.image]
581type=CowDiskImage
582children=child
583child=system.disk0.image.child
584image_file=
585read_only=false
586table_size=65536
587
588[system.disk0.image.child]
589type=RawDiskImage
Ali Saidid69f9042013-04-22 13:20:33 -0400590image_file=/dist/m5/system/disks/linux-latest.img
Andreas Sandberg5fb00e12013-01-07 13:05:52 -0500591read_only=true
592
593[system.disk2]
594type=IdeDisk
595children=image
596delay=1000000
597driveID=master
598image=system.disk2.image
599
600[system.disk2.image]
601type=CowDiskImage
602children=child
603child=system.disk2.image.child
604image_file=
605read_only=false
606table_size=65536
607
608[system.disk2.image.child]
609type=RawDiskImage
Ali Saidid69f9042013-04-22 13:20:33 -0400610image_file=/dist/m5/system/disks/linux-bigswap2.img
Andreas Sandberg5fb00e12013-01-07 13:05:52 -0500611read_only=true
612
613[system.intrctrl]
614type=IntrControl
615sys=system
616
617[system.iobus]
618type=NoncoherentBus
619block_size=64
620clock=1000
621header_cycles=1
622use_default_range=true
623width=8
624default=system.tsunami.pciconfig.pio
625master=system.tsunami.cchip.pio system.tsunami.pchip.pio system.tsunami.fake_sm_chip.pio system.tsunami.fake_uart1.pio system.tsunami.fake_uart2.pio system.tsunami.fake_uart3.pio system.tsunami.fake_uart4.pio system.tsunami.fake_ppc.pio system.tsunami.fake_OROM.pio system.tsunami.fake_pnp_addr.pio system.tsunami.fake_pnp_write.pio system.tsunami.fake_pnp_read0.pio system.tsunami.fake_pnp_read1.pio system.tsunami.fake_pnp_read2.pio system.tsunami.fake_pnp_read3.pio system.tsunami.fake_pnp_read4.pio system.tsunami.fake_pnp_read5.pio system.tsunami.fake_pnp_read6.pio system.tsunami.fake_pnp_read7.pio system.tsunami.fake_ata0.pio system.tsunami.fake_ata1.pio system.tsunami.fb.pio system.tsunami.io.pio system.tsunami.uart.pio system.tsunami.backdoor.pio system.tsunami.ide.pio system.tsunami.ide.config system.tsunami.ethernet.pio system.tsunami.ethernet.config system.iocache.cpu_side
626slave=system.bridge.master system.tsunami.ide.dma system.tsunami.ethernet.dma
627
628[system.iocache]
629type=BaseCache
630addr_ranges=0:134217727
631assoc=8
632block_size=64
633clock=1000
634forward_snoops=false
635hit_latency=50
636is_top_level=true
637max_miss_count=0
638mshrs=20
639prefetch_on_access=false
640prefetcher=Null
641response_latency=50
642size=1024
643system=system
644tgts_per_mshr=12
645two_queue=false
646write_buffers=8
647cpu_side=system.iobus.master[29]
648mem_side=system.membus.slave[2]
649
650[system.l2c]
651type=BaseCache
652addr_ranges=0:18446744073709551615
653assoc=8
654block_size=64
655clock=500
656forward_snoops=true
657hit_latency=20
658is_top_level=false
659max_miss_count=0
660mshrs=20
661prefetch_on_access=false
662prefetcher=Null
663response_latency=20
664size=4194304
665system=system
666tgts_per_mshr=12
667two_queue=false
668write_buffers=8
669cpu_side=system.toL2Bus.master[0]
670mem_side=system.membus.slave[1]
671
672[system.membus]
673type=CoherentBus
674children=badaddr_responder
675block_size=64
676clock=1000
677header_cycles=1
Ali Saidibd31a5d2013-02-15 17:40:14 -0500678system=system
Andreas Sandberg5fb00e12013-01-07 13:05:52 -0500679use_default_range=false
680width=8
681default=system.membus.badaddr_responder.pio
682master=system.bridge.slave system.physmem.port
683slave=system.system_port system.l2c.mem_side system.iocache.mem_side
684
685[system.membus.badaddr_responder]
686type=IsaFake
687clock=1000
688fake_mem=false
689pio_addr=0
690pio_latency=100000
691pio_size=8
692ret_bad_addr=true
693ret_data16=65535
694ret_data32=4294967295
695ret_data64=18446744073709551615
696ret_data8=255
697system=system
698update_data=false
699warn_access=
700pio=system.membus.default
701
702[system.physmem]
703type=SimpleDRAM
Ali Saidibd31a5d2013-02-15 17:40:14 -0500704activation_limit=4
Andreas Sandberg5fb00e12013-01-07 13:05:52 -0500705addr_mapping=openmap
706banks_per_rank=8
Nilay Vaish46463692013-03-27 18:36:21 -0500707channels=1
Andreas Sandberg5fb00e12013-01-07 13:05:52 -0500708clock=1000
709conf_table_reported=false
710in_addr_map=true
Ali Saidibd31a5d2013-02-15 17:40:14 -0500711lines_per_rowbuffer=32
712mem_sched_policy=frfcfs
Andreas Sandberg5fb00e12013-01-07 13:05:52 -0500713null=false
714page_policy=open
715range=0:134217727
716ranks_per_channel=2
717read_buffer_size=32
Ali Saidibd31a5d2013-02-15 17:40:14 -0500718tBURST=5000
719tCL=13750
720tRCD=13750
Andreas Sandberg5fb00e12013-01-07 13:05:52 -0500721tREFI=7800000
722tRFC=300000
Ali Saidibd31a5d2013-02-15 17:40:14 -0500723tRP=13750
724tWTR=7500
725tXAW=40000
Andreas Sandberg5fb00e12013-01-07 13:05:52 -0500726write_buffer_size=32
727write_thresh_perc=70
728zero=false
729port=system.membus.master[1]
730
731[system.simple_disk]
732type=SimpleDisk
733children=disk
734disk=system.simple_disk.disk
735system=system
736
737[system.simple_disk.disk]
738type=RawDiskImage
Ali Saidid69f9042013-04-22 13:20:33 -0400739image_file=/dist/m5/system/disks/linux-latest.img
Andreas Sandberg5fb00e12013-01-07 13:05:52 -0500740read_only=true
741
742[system.terminal]
743type=Terminal
744intr_control=system.intrctrl
745number=0
746output=true
747port=3456
748
749[system.toL2Bus]
750type=CoherentBus
751block_size=64
752clock=500
753header_cycles=1
Ali Saidibd31a5d2013-02-15 17:40:14 -0500754system=system
Andreas Sandberg5fb00e12013-01-07 13:05:52 -0500755use_default_range=false
756width=8
757master=system.l2c.cpu_side
758slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side
759
760[system.tsunami]
761type=Tsunami
762children=backdoor cchip ethernet fake_OROM fake_ata0 fake_ata1 fake_pnp_addr fake_pnp_read0 fake_pnp_read1 fake_pnp_read2 fake_pnp_read3 fake_pnp_read4 fake_pnp_read5 fake_pnp_read6 fake_pnp_read7 fake_pnp_write fake_ppc fake_sm_chip fake_uart1 fake_uart2 fake_uart3 fake_uart4 fb ide io pchip pciconfig uart
763intrctrl=system.intrctrl
764system=system
765
766[system.tsunami.backdoor]
767type=AlphaBackdoor
768clock=1000
769cpu=system.cpu0
770disk=system.simple_disk
771pio_addr=8804682956800
772pio_latency=100000
773platform=system.tsunami
774system=system
775terminal=system.terminal
776pio=system.iobus.master[24]
777
778[system.tsunami.cchip]
779type=TsunamiCChip
780clock=1000
781pio_addr=8803072344064
782pio_latency=100000
783system=system
784tsunami=system.tsunami
785pio=system.iobus.master[0]
786
787[system.tsunami.ethernet]
788type=NSGigE
789BAR0=1
790BAR0LegacyIO=false
791BAR0Size=256
792BAR1=0
793BAR1LegacyIO=false
794BAR1Size=4096
795BAR2=0
796BAR2LegacyIO=false
797BAR2Size=0
798BAR3=0
799BAR3LegacyIO=false
800BAR3Size=0
801BAR4=0
802BAR4LegacyIO=false
803BAR4Size=0
804BAR5=0
805BAR5LegacyIO=false
806BAR5Size=0
807BIST=0
808CacheLineSize=0
809CardbusCIS=0
810ClassCode=2
811Command=0
812DeviceID=34
813ExpansionROM=0
814HeaderType=0
815InterruptLine=30
816InterruptPin=1
817LatencyTimer=0
818MaximumLatency=52
819MinimumGrant=176
820ProgIF=0
821Revision=0
822Status=656
823SubClassCode=0
824SubsystemID=0
825SubsystemVendorID=0
826VendorID=4107
827clock=2000
828config_latency=20000
829dma_data_free=false
830dma_desc_free=false
831dma_no_allocate=true
832dma_read_delay=0
833dma_read_factor=0
834dma_write_delay=0
835dma_write_factor=0
836hardware_address=00:90:00:00:00:01
837intr_delay=10000000
838pci_bus=0
839pci_dev=1
840pci_func=0
841pio_latency=30000
842platform=system.tsunami
843rss=false
844rx_delay=1000000
845rx_fifo_size=524288
846rx_filter=true
847rx_thread=false
848system=system
849tx_delay=1000000
850tx_fifo_size=524288
851tx_thread=false
852config=system.iobus.master[28]
853dma=system.iobus.slave[2]
854pio=system.iobus.master[27]
855
856[system.tsunami.fake_OROM]
857type=IsaFake
858clock=1000
859fake_mem=false
860pio_addr=8796093677568
861pio_latency=100000
862pio_size=393216
863ret_bad_addr=false
864ret_data16=65535
865ret_data32=4294967295
866ret_data64=18446744073709551615
867ret_data8=255
868system=system
869update_data=false
870warn_access=
871pio=system.iobus.master[8]
872
873[system.tsunami.fake_ata0]
874type=IsaFake
875clock=1000
876fake_mem=false
877pio_addr=8804615848432
878pio_latency=100000
879pio_size=8
880ret_bad_addr=false
881ret_data16=65535
882ret_data32=4294967295
883ret_data64=18446744073709551615
884ret_data8=255
885system=system
886update_data=false
887warn_access=
888pio=system.iobus.master[19]
889
890[system.tsunami.fake_ata1]
891type=IsaFake
892clock=1000
893fake_mem=false
894pio_addr=8804615848304
895pio_latency=100000
896pio_size=8
897ret_bad_addr=false
898ret_data16=65535
899ret_data32=4294967295
900ret_data64=18446744073709551615
901ret_data8=255
902system=system
903update_data=false
904warn_access=
905pio=system.iobus.master[20]
906
907[system.tsunami.fake_pnp_addr]
908type=IsaFake
909clock=1000
910fake_mem=false
911pio_addr=8804615848569
912pio_latency=100000
913pio_size=8
914ret_bad_addr=false
915ret_data16=65535
916ret_data32=4294967295
917ret_data64=18446744073709551615
918ret_data8=255
919system=system
920update_data=false
921warn_access=
922pio=system.iobus.master[9]
923
924[system.tsunami.fake_pnp_read0]
925type=IsaFake
926clock=1000
927fake_mem=false
928pio_addr=8804615848451
929pio_latency=100000
930pio_size=8
931ret_bad_addr=false
932ret_data16=65535
933ret_data32=4294967295
934ret_data64=18446744073709551615
935ret_data8=255
936system=system
937update_data=false
938warn_access=
939pio=system.iobus.master[11]
940
941[system.tsunami.fake_pnp_read1]
942type=IsaFake
943clock=1000
944fake_mem=false
945pio_addr=8804615848515
946pio_latency=100000
947pio_size=8
948ret_bad_addr=false
949ret_data16=65535
950ret_data32=4294967295
951ret_data64=18446744073709551615
952ret_data8=255
953system=system
954update_data=false
955warn_access=
956pio=system.iobus.master[12]
957
958[system.tsunami.fake_pnp_read2]
959type=IsaFake
960clock=1000
961fake_mem=false
962pio_addr=8804615848579
963pio_latency=100000
964pio_size=8
965ret_bad_addr=false
966ret_data16=65535
967ret_data32=4294967295
968ret_data64=18446744073709551615
969ret_data8=255
970system=system
971update_data=false
972warn_access=
973pio=system.iobus.master[13]
974
975[system.tsunami.fake_pnp_read3]
976type=IsaFake
977clock=1000
978fake_mem=false
979pio_addr=8804615848643
980pio_latency=100000
981pio_size=8
982ret_bad_addr=false
983ret_data16=65535
984ret_data32=4294967295
985ret_data64=18446744073709551615
986ret_data8=255
987system=system
988update_data=false
989warn_access=
990pio=system.iobus.master[14]
991
992[system.tsunami.fake_pnp_read4]
993type=IsaFake
994clock=1000
995fake_mem=false
996pio_addr=8804615848707
997pio_latency=100000
998pio_size=8
999ret_bad_addr=false
1000ret_data16=65535
1001ret_data32=4294967295
1002ret_data64=18446744073709551615
1003ret_data8=255
1004system=system
1005update_data=false
1006warn_access=
1007pio=system.iobus.master[15]
1008
1009[system.tsunami.fake_pnp_read5]
1010type=IsaFake
1011clock=1000
1012fake_mem=false
1013pio_addr=8804615848771
1014pio_latency=100000
1015pio_size=8
1016ret_bad_addr=false
1017ret_data16=65535
1018ret_data32=4294967295
1019ret_data64=18446744073709551615
1020ret_data8=255
1021system=system
1022update_data=false
1023warn_access=
1024pio=system.iobus.master[16]
1025
1026[system.tsunami.fake_pnp_read6]
1027type=IsaFake
1028clock=1000
1029fake_mem=false
1030pio_addr=8804615848835
1031pio_latency=100000
1032pio_size=8
1033ret_bad_addr=false
1034ret_data16=65535
1035ret_data32=4294967295
1036ret_data64=18446744073709551615
1037ret_data8=255
1038system=system
1039update_data=false
1040warn_access=
1041pio=system.iobus.master[17]
1042
1043[system.tsunami.fake_pnp_read7]
1044type=IsaFake
1045clock=1000
1046fake_mem=false
1047pio_addr=8804615848899
1048pio_latency=100000
1049pio_size=8
1050ret_bad_addr=false
1051ret_data16=65535
1052ret_data32=4294967295
1053ret_data64=18446744073709551615
1054ret_data8=255
1055system=system
1056update_data=false
1057warn_access=
1058pio=system.iobus.master[18]
1059
1060[system.tsunami.fake_pnp_write]
1061type=IsaFake
1062clock=1000
1063fake_mem=false
1064pio_addr=8804615850617
1065pio_latency=100000
1066pio_size=8
1067ret_bad_addr=false
1068ret_data16=65535
1069ret_data32=4294967295
1070ret_data64=18446744073709551615
1071ret_data8=255
1072system=system
1073update_data=false
1074warn_access=
1075pio=system.iobus.master[10]
1076
1077[system.tsunami.fake_ppc]
1078type=IsaFake
1079clock=1000
1080fake_mem=false
1081pio_addr=8804615848891
1082pio_latency=100000
1083pio_size=8
1084ret_bad_addr=false
1085ret_data16=65535
1086ret_data32=4294967295
1087ret_data64=18446744073709551615
1088ret_data8=255
1089system=system
1090update_data=false
1091warn_access=
1092pio=system.iobus.master[7]
1093
1094[system.tsunami.fake_sm_chip]
1095type=IsaFake
1096clock=1000
1097fake_mem=false
1098pio_addr=8804615848816
1099pio_latency=100000
1100pio_size=8
1101ret_bad_addr=false
1102ret_data16=65535
1103ret_data32=4294967295
1104ret_data64=18446744073709551615
1105ret_data8=255
1106system=system
1107update_data=false
1108warn_access=
1109pio=system.iobus.master[2]
1110
1111[system.tsunami.fake_uart1]
1112type=IsaFake
1113clock=1000
1114fake_mem=false
1115pio_addr=8804615848696
1116pio_latency=100000
1117pio_size=8
1118ret_bad_addr=false
1119ret_data16=65535
1120ret_data32=4294967295
1121ret_data64=18446744073709551615
1122ret_data8=255
1123system=system
1124update_data=false
1125warn_access=
1126pio=system.iobus.master[3]
1127
1128[system.tsunami.fake_uart2]
1129type=IsaFake
1130clock=1000
1131fake_mem=false
1132pio_addr=8804615848936
1133pio_latency=100000
1134pio_size=8
1135ret_bad_addr=false
1136ret_data16=65535
1137ret_data32=4294967295
1138ret_data64=18446744073709551615
1139ret_data8=255
1140system=system
1141update_data=false
1142warn_access=
1143pio=system.iobus.master[4]
1144
1145[system.tsunami.fake_uart3]
1146type=IsaFake
1147clock=1000
1148fake_mem=false
1149pio_addr=8804615848680
1150pio_latency=100000
1151pio_size=8
1152ret_bad_addr=false
1153ret_data16=65535
1154ret_data32=4294967295
1155ret_data64=18446744073709551615
1156ret_data8=255
1157system=system
1158update_data=false
1159warn_access=
1160pio=system.iobus.master[5]
1161
1162[system.tsunami.fake_uart4]
1163type=IsaFake
1164clock=1000
1165fake_mem=false
1166pio_addr=8804615848944
1167pio_latency=100000
1168pio_size=8
1169ret_bad_addr=false
1170ret_data16=65535
1171ret_data32=4294967295
1172ret_data64=18446744073709551615
1173ret_data8=255
1174system=system
1175update_data=false
1176warn_access=
1177pio=system.iobus.master[6]
1178
1179[system.tsunami.fb]
1180type=BadDevice
1181clock=1000
1182devicename=FrameBuffer
1183pio_addr=8804615848912
1184pio_latency=100000
1185system=system
1186pio=system.iobus.master[21]
1187
1188[system.tsunami.ide]
1189type=IdeController
1190BAR0=1
1191BAR0LegacyIO=false
1192BAR0Size=8
1193BAR1=1
1194BAR1LegacyIO=false
1195BAR1Size=4
1196BAR2=1
1197BAR2LegacyIO=false
1198BAR2Size=8
1199BAR3=1
1200BAR3LegacyIO=false
1201BAR3Size=4
1202BAR4=1
1203BAR4LegacyIO=false
1204BAR4Size=16
1205BAR5=1
1206BAR5LegacyIO=false
1207BAR5Size=0
1208BIST=0
1209CacheLineSize=0
1210CardbusCIS=0
1211ClassCode=1
1212Command=0
1213DeviceID=28945
1214ExpansionROM=0
1215HeaderType=0
1216InterruptLine=31
1217InterruptPin=1
1218LatencyTimer=0
1219MaximumLatency=0
1220MinimumGrant=0
1221ProgIF=133
1222Revision=0
1223Status=640
1224SubClassCode=1
1225SubsystemID=0
1226SubsystemVendorID=0
1227VendorID=32902
1228clock=1000
1229config_latency=20000
1230ctrl_offset=0
1231disks=system.disk0 system.disk2
1232io_shift=0
1233pci_bus=0
1234pci_dev=0
1235pci_func=0
1236pio_latency=30000
1237platform=system.tsunami
1238system=system
1239config=system.iobus.master[26]
1240dma=system.iobus.slave[1]
1241pio=system.iobus.master[25]
1242
1243[system.tsunami.io]
1244type=TsunamiIO
1245clock=1000
1246frequency=976562500
1247pio_addr=8804615847936
1248pio_latency=100000
1249system=system
1250time=Thu Jan 1 00:00:00 2009
1251tsunami=system.tsunami
1252year_is_bcd=false
1253pio=system.iobus.master[22]
1254
1255[system.tsunami.pchip]
1256type=TsunamiPChip
1257clock=1000
1258pio_addr=8802535473152
1259pio_latency=100000
1260system=system
1261tsunami=system.tsunami
1262pio=system.iobus.master[1]
1263
1264[system.tsunami.pciconfig]
1265type=PciConfigAll
1266bus=0
1267clock=1000
1268pio_latency=30000
1269platform=system.tsunami
1270size=16777216
1271system=system
1272pio=system.iobus.default
1273
1274[system.tsunami.uart]
1275type=Uart8250
1276clock=1000
1277pio_addr=8804615848952
1278pio_latency=100000
1279platform=system.tsunami
1280system=system
1281terminal=system.terminal
1282pio=system.iobus.master[23]
1283