tests/long/se/70.twolf/ref/arm/linux/o3-timing/stats.txt

---------- Begin Simulation Statistics ----------
sim_seconds                                  0.084938                       # Number of seconds simulated
sim_ticks                                 84937723500                       # Number of ticks simulated
final_tick                                84937723500                       # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq                                 1000000000000                       # Frequency of simulated ticks
host_inst_rate                                 146803                       # Simulator instruction rate (inst/s)
host_op_rate                                   154755                       # Simulator op (including micro ops) rate (op/s)
host_tick_rate                               72367413                       # Simulator tick rate (ticks/s)
host_mem_usage                                 271624                       # Number of bytes of host memory used
host_seconds                                  1173.70                       # Real time elapsed on the host
sim_insts                                   172303022                       # Number of instructions simulated
sim_ops                                     181635954                       # Number of ops (including micro ops) simulated
system.voltage_domain.voltage                       1                       # Voltage in Volts
system.clk_domain.clock                          1000                       # Clock period in ticks
system.physmem.bytes_read::cpu.inst            587328                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data            132096                       # Number of bytes read from this memory
system.physmem.bytes_read::cpu.l2cache.prefetcher        70976                       # Number of bytes read from this memory
system.physmem.bytes_read::total               790400                       # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst       587328                       # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total          587328                       # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst               9177                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data               2064                       # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.l2cache.prefetcher         1109                       # Number of read requests responded to by this memory
system.physmem.num_reads::total                 12350                       # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst              6914807                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data              1555210                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.l2cache.prefetcher       835624                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total                 9305641                       # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst         6914807                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total            6914807                       # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst             6914807                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data             1555210                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.l2cache.prefetcher       835624                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total                9305641                       # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs                         12351                       # Number of read requests accepted
system.physmem.writeReqs                            0                       # Number of write requests accepted
system.physmem.readBursts                       12351                       # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts                          0                       # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM                   790464                       # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ                         0                       # Total number of bytes read from write queue
system.physmem.bytesWritten                         0                       # Total number of bytes written to DRAM
system.physmem.bytesReadSys                    790464                       # Total read bytes from the system interface side
system.physmem.bytesWrittenSys                      0                       # Total written bytes from the system interface side
system.physmem.servicedByWrQ                        0                       # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts                       0                       # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs              0                       # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0                1113                       # Per bank write bursts
system.physmem.perBankRdBursts::1                 381                       # Per bank write bursts
system.physmem.perBankRdBursts::2                5089                       # Per bank write bursts
system.physmem.perBankRdBursts::3                 423                       # Per bank write bursts
system.physmem.perBankRdBursts::4                1959                       # Per bank write bursts
system.physmem.perBankRdBursts::5                 424                       # Per bank write bursts
system.physmem.perBankRdBursts::6                 265                       # Per bank write bursts
system.physmem.perBankRdBursts::7                 373                       # Per bank write bursts
system.physmem.perBankRdBursts::8                 266                       # Per bank write bursts
system.physmem.perBankRdBursts::9                 219                       # Per bank write bursts
system.physmem.perBankRdBursts::10                295                       # Per bank write bursts
system.physmem.perBankRdBursts::11                324                       # Per bank write bursts
system.physmem.perBankRdBursts::12                199                       # Per bank write bursts
system.physmem.perBankRdBursts::13                249                       # Per bank write bursts
system.physmem.perBankRdBursts::14                229                       # Per bank write bursts
system.physmem.perBankRdBursts::15                543                       # Per bank write bursts
system.physmem.perBankWrBursts::0                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::1                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::2                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::3                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::4                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::5                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::6                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::7                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::8                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::9                   0                       # Per bank write bursts
system.physmem.perBankWrBursts::10                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::11                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::12                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::13                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::14                  0                       # Per bank write bursts
system.physmem.perBankWrBursts::15                  0                       # Per bank write bursts
system.physmem.numRdRetry                           0                       # Number of times read queue was full causing retry
system.physmem.numWrRetry                           0                       # Number of times write queue was full causing retry
system.physmem.totGap                     84937714500                       # Total gap between requests
system.physmem.readPktSize::0                       0                       # Read request sizes (log2)
system.physmem.readPktSize::1                       0                       # Read request sizes (log2)
system.physmem.readPktSize::2                       0                       # Read request sizes (log2)
system.physmem.readPktSize::3                       0                       # Read request sizes (log2)
system.physmem.readPktSize::4                       0                       # Read request sizes (log2)
system.physmem.readPktSize::5                       0                       # Read request sizes (log2)
system.physmem.readPktSize::6                   12351                       # Read request sizes (log2)
system.physmem.writePktSize::0                      0                       # Write request sizes (log2)
system.physmem.writePktSize::1                      0                       # Write request sizes (log2)
system.physmem.writePktSize::2                      0                       # Write request sizes (log2)
system.physmem.writePktSize::3                      0                       # Write request sizes (log2)
system.physmem.writePktSize::4                      0                       # Write request sizes (log2)
system.physmem.writePktSize::5                      0                       # Write request sizes (log2)
system.physmem.writePktSize::6                      0                       # Write request sizes (log2)
system.physmem.rdQLenPdf::0                     10935                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1                       975                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2                       172                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3                        85                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4                        60                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5                        38                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6                        30                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7                        28                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8                        27                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9                         1                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30                        0                       # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31                        0                       # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9                         0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62                        0                       # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63                        0                       # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples         7250                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean      108.738207                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean      85.269087                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev     131.624325                       # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127           5249     72.40%     72.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255         1564     21.57%     93.97% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383          167      2.30%     96.28% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511           93      1.28%     97.56% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639           42      0.58%     98.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767           24      0.33%     98.47% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895           18      0.25%     98.72% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023           21      0.29%     99.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151           72      0.99%    100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total           7250                       # Bytes accessed per row activation
system.physmem.totQLat                      171430514                       # Total ticks spent queuing
system.physmem.totMemAccLat                 403011764                       # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat                     61755000                       # Total ticks spent in databus transfers
system.physmem.avgQLat                       13879.89                       # Average queueing delay per DRAM burst
system.physmem.avgBusLat                      5000.00                       # Average bus latency per DRAM burst
system.physmem.avgMemAccLat                  32629.89                       # Average memory access latency per DRAM burst
system.physmem.avgRdBW                           9.31                       # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW                           0.00                       # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys                        9.31                       # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys                        0.00                       # Average system write bandwidth in MiByte/s
system.physmem.peakBW                        12800.00                       # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil                           0.07                       # Data bus utilization in percentage
system.physmem.busUtilRead                       0.07                       # Data bus utilization in percentage for reads
system.physmem.busUtilWrite                      0.00                       # Data bus utilization in percentage for writes
system.physmem.avgRdQLen                         1.01                       # Average read queue length when enqueuing
system.physmem.avgWrQLen                         0.00                       # Average write queue length when enqueuing
system.physmem.readRowHits                       5094                       # Number of row buffer hits during reads
system.physmem.writeRowHits                         0                       # Number of row buffer hits during writes
system.physmem.readRowHitRate                   41.24                       # Row buffer hit rate for reads
system.physmem.writeRowHitRate                    nan                       # Row buffer hit rate for writes
system.physmem.avgGap                      6876990.89                       # Average gap between requests
system.physmem.pageHitRate                      41.24                       # Row buffer hit rate, read and write combined
system.physmem_0.actEnergy                   48452040                       # Energy for activate commands per rank (pJ)
system.physmem_0.preEnergy                   26437125                       # Energy for precharge commands per rank (pJ)
system.physmem_0.readEnergy                  78179400                       # Energy for read commands per rank (pJ)
system.physmem_0.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_0.refreshEnergy             5547372480                       # Energy for refresh commands per rank (pJ)
system.physmem_0.actBackEnergy            16645874445                       # Energy for active background per rank (pJ)
system.physmem_0.preBackEnergy            36357960750                       # Energy for precharge background per rank (pJ)
system.physmem_0.totalEnergy              58704276240                       # Total energy per rank (pJ)
system.physmem_0.averagePower              691.186004                       # Core power per rank (mW)
system.physmem_0.memoryStateTime::IDLE    60381088491                       # Time in different power states
system.physmem_0.memoryStateTime::REF      2836080000                       # Time in different power states
system.physmem_0.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_0.memoryStateTime::ACT     21718991509                       # Time in different power states
system.physmem_0.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.physmem_1.actEnergy                    6335280                       # Energy for activate commands per rank (pJ)
system.physmem_1.preEnergy                    3456750                       # Energy for precharge commands per rank (pJ)
system.physmem_1.readEnergy                  17877600                       # Energy for read commands per rank (pJ)
system.physmem_1.writeEnergy                        0                       # Energy for write commands per rank (pJ)
system.physmem_1.refreshEnergy             5547372480                       # Energy for refresh commands per rank (pJ)
system.physmem_1.actBackEnergy             3295031490                       # Energy for active background per rank (pJ)
system.physmem_1.preBackEnergy            48069226500                       # Energy for precharge background per rank (pJ)
system.physmem_1.totalEnergy              56939300100                       # Total energy per rank (pJ)
system.physmem_1.averagePower              670.405119                       # Core power per rank (mW)
system.physmem_1.memoryStateTime::IDLE    79958437412                       # Time in different power states
system.physmem_1.memoryStateTime::REF      2836080000                       # Time in different power states
system.physmem_1.memoryStateTime::PRE_PDN            0                       # Time in different power states
system.physmem_1.memoryStateTime::ACT      2138239588                       # Time in different power states
system.physmem_1.memoryStateTime::ACT_PDN            0                       # Time in different power states
system.cpu.branchPred.lookups                85626366                       # Number of BP lookups
system.cpu.branchPred.condPredicted          68177013                       # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect           5935452                       # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups             39946926                       # Number of BTB lookups
system.cpu.branchPred.BTBHits                38187698                       # Number of BTB hits
system.cpu.branchPred.BTBCorrect                    0                       # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct             95.596087                       # BTB Hit Percentage
system.cpu.branchPred.usedRAS                 3683716                       # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect              81912                       # Number of incorrect RAS predictions.
system.cpu.branchPred.indirectLookups          681689                       # Number of indirect predictor lookups.
system.cpu.branchPred.indirectHits             653746                       # Number of indirect target hits.
system.cpu.branchPred.indirectMisses            27943                       # Number of indirect misses.
system.cpu.branchPredindirectMispredicted        40316                       # Number of mispredicted indirect branches.
system.cpu_clk_domain.clock                       500                       # Clock period in ticks
system.cpu.dstage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dstage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.dstage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.dstage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.dstage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.dstage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.dstage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.dstage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.dstage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.dstage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.dstage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.dstage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.dstage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.dstage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.dstage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.dstage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.dstage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.dtb.walker.walks                         0                       # Table walker walks requested
system.cpu.dtb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.dtb.inst_hits                            0                       # ITB inst hits
system.cpu.dtb.inst_misses                          0                       # ITB inst misses
system.cpu.dtb.read_hits                            0                       # DTB read hits
system.cpu.dtb.read_misses                          0                       # DTB read misses
system.cpu.dtb.write_hits                           0                       # DTB write hits
system.cpu.dtb.write_misses                         0                       # DTB write misses
system.cpu.dtb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.dtb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.dtb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.dtb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.dtb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.dtb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.dtb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.dtb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.dtb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.dtb.read_accesses                        0                       # DTB read accesses
system.cpu.dtb.write_accesses                       0                       # DTB write accesses
system.cpu.dtb.inst_accesses                        0                       # ITB inst accesses
system.cpu.dtb.hits                                 0                       # DTB hits
system.cpu.dtb.misses                               0                       # DTB misses
system.cpu.dtb.accesses                             0                       # DTB accesses
system.cpu.istage2_mmu.stage2_tlb.walker.walks            0                       # Table walker walks requested
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.istage2_mmu.stage2_tlb.inst_hits            0                       # ITB inst hits
system.cpu.istage2_mmu.stage2_tlb.inst_misses            0                       # ITB inst misses
system.cpu.istage2_mmu.stage2_tlb.read_hits            0                       # DTB read hits
system.cpu.istage2_mmu.stage2_tlb.read_misses            0                       # DTB read misses
system.cpu.istage2_mmu.stage2_tlb.write_hits            0                       # DTB write hits
system.cpu.istage2_mmu.stage2_tlb.write_misses            0                       # DTB write misses
system.cpu.istage2_mmu.stage2_tlb.flush_tlb            0                       # Number of times complete TLB was flushed
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva            0                       # Number of times TLB was flushed by MVA
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid            0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid            0                       # Number of times TLB was flushed by ASID
system.cpu.istage2_mmu.stage2_tlb.flush_entries            0                       # Number of entries that have been flushed from TLB
system.cpu.istage2_mmu.stage2_tlb.align_faults            0                       # Number of TLB faults due to alignment restrictions
system.cpu.istage2_mmu.stage2_tlb.prefetch_faults            0                       # Number of TLB faults due to prefetch
system.cpu.istage2_mmu.stage2_tlb.domain_faults            0                       # Number of TLB faults due to domain restrictions
system.cpu.istage2_mmu.stage2_tlb.perms_faults            0                       # Number of TLB faults due to permissions restrictions
system.cpu.istage2_mmu.stage2_tlb.read_accesses            0                       # DTB read accesses
system.cpu.istage2_mmu.stage2_tlb.write_accesses            0                       # DTB write accesses
system.cpu.istage2_mmu.stage2_tlb.inst_accesses            0                       # ITB inst accesses
system.cpu.istage2_mmu.stage2_tlb.hits              0                       # DTB hits
system.cpu.istage2_mmu.stage2_tlb.misses            0                       # DTB misses
system.cpu.istage2_mmu.stage2_tlb.accesses            0                       # DTB accesses
system.cpu.itb.walker.walks                         0                       # Table walker walks requested
system.cpu.itb.walker.walkRequestOrigin_Requested::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Requested::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Data            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::Inst            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin_Completed::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.walker.walkRequestOrigin::total            0                       # Table walker requests started/completed, data/inst
system.cpu.itb.inst_hits                            0                       # ITB inst hits
system.cpu.itb.inst_misses                          0                       # ITB inst misses
system.cpu.itb.read_hits                            0                       # DTB read hits
system.cpu.itb.read_misses                          0                       # DTB read misses
system.cpu.itb.write_hits                           0                       # DTB write hits
system.cpu.itb.write_misses                         0                       # DTB write misses
system.cpu.itb.flush_tlb                            0                       # Number of times complete TLB was flushed
system.cpu.itb.flush_tlb_mva                        0                       # Number of times TLB was flushed by MVA
system.cpu.itb.flush_tlb_mva_asid                   0                       # Number of times TLB was flushed by MVA & ASID
system.cpu.itb.flush_tlb_asid                       0                       # Number of times TLB was flushed by ASID
system.cpu.itb.flush_entries                        0                       # Number of entries that have been flushed from TLB
system.cpu.itb.align_faults                         0                       # Number of TLB faults due to alignment restrictions
system.cpu.itb.prefetch_faults                      0                       # Number of TLB faults due to prefetch
system.cpu.itb.domain_faults                        0                       # Number of TLB faults due to domain restrictions
system.cpu.itb.perms_faults                         0                       # Number of TLB faults due to permissions restrictions
system.cpu.itb.read_accesses                        0                       # DTB read accesses
system.cpu.itb.write_accesses                       0                       # DTB write accesses
system.cpu.itb.inst_accesses                        0                       # ITB inst accesses
system.cpu.itb.hits                                 0                       # DTB hits
system.cpu.itb.misses                               0                       # DTB misses
system.cpu.itb.accesses                             0                       # DTB accesses
system.cpu.workload.num_syscalls                  400                       # Number of system calls
system.cpu.numCycles                        169875448                       # number of cpu cycles simulated
system.cpu.numWorkItemsStarted                      0                       # number of work items this cpu started
system.cpu.numWorkItemsCompleted                    0                       # number of work items this cpu completed
system.cpu.fetch.icacheStallCycles            5671940                       # Number of cycles fetch is stalled on an Icache miss
system.cpu.fetch.Insts                      347162762                       # Number of instructions fetch has processed
system.cpu.fetch.Branches                    85626366                       # Number of branches that fetch encountered
system.cpu.fetch.predictedBranches           42525160                       # Number of branches that fetch has predicted taken
system.cpu.fetch.Cycles                     157499775                       # Number of cycles fetch has run and was not squashing or blocked
system.cpu.fetch.SquashCycles                11884731                       # Number of cycles fetch has spent squashing
system.cpu.fetch.MiscStallCycles                 2609                       # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
system.cpu.fetch.PendingQuiesceStallCycles           23                       # Number of stall cycles due to pending quiesce instructions
system.cpu.fetch.IcacheWaitRetryStallCycles         3808                       # Number of stall cycles due to full MSHR
system.cpu.fetch.CacheLines                  78326624                       # Number of cache lines fetched
system.cpu.fetch.IcacheSquashes                 18246                       # Number of outstanding Icache misses that were squashed
system.cpu.fetch.rateDist::samples          169120520                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::mean              2.147875                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::stdev             1.049260                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows               0      0.00%      0.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::0                 17456404     10.32%     10.32% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::1                 30071791     17.78%     28.10% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::2                 31598997     18.68%     46.79% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::3                 89993328     53.21%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows                0      0.00%    100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value                0                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value                3                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::total            169120520                       # Number of instructions fetched each cycle (Total)
system.cpu.fetch.branchRate                  0.504054                       # Number of branch fetches per cycle
system.cpu.fetch.rate                        2.043631                       # Number of inst fetches per cycle
system.cpu.decode.IdleCycles                 17509987                       # Number of cycles decode is idle
system.cpu.decode.BlockedCycles              17244874                       # Number of cycles decode is blocked
system.cpu.decode.RunCycles                 121866560                       # Number of cycles decode is running
system.cpu.decode.UnblockCycles               6731455                       # Number of cycles decode is unblocking
system.cpu.decode.SquashCycles                5767644                       # Number of cycles decode is squashing
system.cpu.decode.BranchResolved             11064434                       # Number of times decode resolved a branch
system.cpu.decode.BranchMispred                189777                       # Number of times decode detected a branch misprediction
system.cpu.decode.DecodedInsts              304997911                       # Number of instructions handled by decode
system.cpu.decode.SquashedInsts              27240618                       # Number of squashed instructions handled by decode
system.cpu.rename.SquashCycles                5767644                       # Number of cycles rename is squashing
system.cpu.rename.IdleCycles                 37477523                       # Number of cycles rename is idle
system.cpu.rename.BlockCycles                 8502539                       # Number of cycles rename is blocking
system.cpu.rename.serializeStallCycles         578983                       # count of cycles rename stalled for serializing inst
system.cpu.rename.RunCycles                 108355768                       # Number of cycles rename is running
system.cpu.rename.UnblockCycles               8438063                       # Number of cycles rename is unblocking
system.cpu.rename.RenamedInsts              277420851                       # Number of instructions processed by rename
system.cpu.rename.SquashedInsts              13180734                       # Number of squashed instructions processed by rename
system.cpu.rename.ROBFullEvents               3058487                       # Number of times rename has blocked due to ROB full
system.cpu.rename.IQFullEvents                 843003                       # Number of times rename has blocked due to IQ full
system.cpu.rename.LQFullEvents                2280960                       # Number of times rename has blocked due to LQ full
system.cpu.rename.SQFullEvents                  36243                       # Number of times rename has blocked due to SQ full
system.cpu.rename.FullRegisterEvents            27083                       # Number of times there has been no free registers
system.cpu.rename.RenamedOperands           481449871                       # Number of destination operands rename has renamed
system.cpu.rename.RenameLookups            1191735135                       # Number of register rename lookups that rename has made
system.cpu.rename.int_rename_lookups        296461789                       # Number of integer rename lookups
system.cpu.rename.fp_rename_lookups           3004325                       # Number of floating rename lookups
system.cpu.rename.CommittedMaps             292976929                       # Number of HB maps that are committed
system.cpu.rename.UndoneMaps                188472942                       # Number of HB maps that are undone due to squashing
system.cpu.rename.serializingInsts              23603                       # count of serializing insts renamed
system.cpu.rename.tempSerializingInsts          23603                       # count of temporary serializing insts renamed
system.cpu.rename.skidInsts                  13353784                       # count of insts added to the skid buffer
system.cpu.memDep0.insertedLoads             33915046                       # Number of loads inserted to the mem dependence unit.
system.cpu.memDep0.insertedStores            14407100                       # Number of stores inserted to the mem dependence unit.
system.cpu.memDep0.conflictingLoads           2540378                       # Number of conflicting loads.
system.cpu.memDep0.conflictingStores          1803003                       # Number of conflicting stores.
system.cpu.iq.iqInstsAdded                  263798584                       # Number of instructions added to the IQ (excludes non-spec)
system.cpu.iq.iqNonSpecInstsAdded               45955                       # Number of non-speculative instructions added to the IQ
system.cpu.iq.iqInstsIssued                 214411803                       # Number of instructions issued
system.cpu.iq.iqSquashedInstsIssued           5187874                       # Number of squashed instructions issued
system.cpu.iq.iqSquashedInstsExamined        82208585                       # Number of squashed instructions iterated over during squash; mainly for profiling
system.cpu.iq.iqSquashedOperandsExamined    217092419                       # Number of squashed operands that are examined and possibly removed from graph
system.cpu.iq.iqSquashedNonSpecRemoved            739                       # Number of squashed non-spec instructions that were removed
system.cpu.iq.issued_per_cycle::samples     169120520                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::mean         1.267805                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::stdev        1.017994                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows            0      0.00%      0.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::0            52408217     30.99%     30.99% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::1            35940187     21.25%     52.24% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::2            65510990     38.74%     90.98% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::3            13642635      8.07%     99.04% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::4             1570936      0.93%     99.97% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::5               47343      0.03%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::6                 212      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::7                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::8                   0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows            0      0.00%    100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value            0                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value            6                       # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::total       169120520                       # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass                   0      0.00%      0.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IntAlu                35659439     66.16%     66.16% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult                 153265      0.28%     66.45% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv                       0      0.00%     66.45% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd                     0      0.00%     66.45% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCmp                     0      0.00%     66.45% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatCvt                     0      0.00%     66.45% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatMult                    0      0.00%     66.45% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatDiv                     0      0.00%     66.45% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatSqrt                    0      0.00%     66.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAdd                      0      0.00%     66.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAddAcc                   0      0.00%     66.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdAlu                      0      0.00%     66.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCmp                      0      0.00%     66.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdCvt                      0      0.00%     66.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMisc                     0      0.00%     66.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMult                     0      0.00%     66.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdMultAcc                  0      0.00%     66.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShift                    0      0.00%     66.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdShiftAcc                 0      0.00%     66.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdSqrt                     0      0.00%     66.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAdd              1066      0.00%     66.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatAlu                 0      0.00%     66.45% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCmp             35730      0.07%     66.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatCvt               240      0.00%     66.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatDiv               201      0.00%     66.51% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMisc              958      0.00%     66.52% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult            34286      0.06%     66.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc             4      0.00%     66.58% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt                0      0.00%     66.58% # attempts to use FU when none available
system.cpu.iq.fu_full::MemRead               14056522     26.08%     92.66% # attempts to use FU when none available
system.cpu.iq.fu_full::MemWrite               3955910      7.34%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess                    0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch                 0      0.00%    100.00% # attempts to use FU when none available
system.cpu.iq.FU_type_0::No_OpClass                 0      0.00%      0.00% # Type of FU issued
system.cpu.iq.FU_type_0::IntAlu             166992897     77.88%     77.88% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult               919175      0.43%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv                     0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd                   0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCmp                   0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatCvt                   0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatMult                  0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatDiv                   0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::FloatSqrt                  0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAdd                    0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAddAcc                 0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdAlu                    0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCmp                    0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdCvt                    0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMisc                   0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMult                   0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdMultAcc                0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShift                  0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdShiftAcc               0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdSqrt                   0      0.00%     78.31% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAdd           33015      0.02%     78.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatAlu               0      0.00%     78.33% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCmp          165179      0.08%     78.41% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatCvt          245702      0.11%     78.52% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatDiv           76018      0.04%     78.56% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMisc         460499      0.21%     78.77% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult         206683      0.10%     78.87% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc        71623      0.03%     78.90% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt            319      0.00%     78.90% # Type of FU issued
system.cpu.iq.FU_type_0::MemRead             31868874     14.86%     93.76% # Type of FU issued
system.cpu.iq.FU_type_0::MemWrite            13371819      6.24%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess                  0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch               0      0.00%    100.00% # Type of FU issued
system.cpu.iq.FU_type_0::total              214411803                       # Type of FU issued
system.cpu.iq.rate                           1.262171                       # Inst issue rate
system.cpu.iq.fu_busy_cnt                    53897621                       # FU busy when requested
system.cpu.iq.fu_busy_rate                   0.251374                       # FU busy rate (busy events/executed inst)
system.cpu.iq.int_inst_queue_reads          653076785                       # Number of integer instruction queue reads
system.cpu.iq.int_inst_queue_writes         344050437                       # Number of integer instruction queue writes
system.cpu.iq.int_inst_queue_wakeup_accesses    204251594                       # Number of integer instruction queue wakeup accesses
system.cpu.iq.fp_inst_queue_reads             3952836                       # Number of floating instruction queue reads
system.cpu.iq.fp_inst_queue_writes            2009578                       # Number of floating instruction queue writes
system.cpu.iq.fp_inst_queue_wakeup_accesses      1806333                       # Number of floating instruction queue wakeup accesses
system.cpu.iq.int_alu_accesses              266175663                       # Number of integer alu accesses
system.cpu.iq.fp_alu_accesses                 2133761                       # Number of floating point alu accesses
system.cpu.iew.lsq.thread0.forwLoads          1598827                       # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads             0                       # Number of loads ignored due to an invalid address
system.cpu.iew.lsq.thread0.squashedLoads      6018902                       # Number of loads squashed
system.cpu.iew.lsq.thread0.ignoredResponses         7447                       # Number of memory responses ignored because the instruction is squashed
system.cpu.iew.lsq.thread0.memOrderViolation         7034                       # Number of memory ordering violations
system.cpu.iew.lsq.thread0.squashedStores      1762466                       # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs             0                       # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads             0                       # Number of blocked loads due to partial load-store forwarding
system.cpu.iew.lsq.thread0.rescheduledLoads        25527                       # Number of loads that were rescheduled
system.cpu.iew.lsq.thread0.cacheBlocked           769                       # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles                        0                       # Number of cycles IEW is idle
system.cpu.iew.iewSquashCycles                5767644                       # Number of cycles IEW is squashing
system.cpu.iew.iewBlockCycles                 5618767                       # Number of cycles IEW is blocking
system.cpu.iew.iewUnblockCycles                 62916                       # Number of cycles IEW is unblocking
system.cpu.iew.iewDispatchedInsts           263864756                       # Number of instructions dispatched to IQ
system.cpu.iew.iewDispSquashedInsts                 0                       # Number of squashed instructions skipped by dispatch
system.cpu.iew.iewDispLoadInsts              33915046                       # Number of dispatched load instructions
system.cpu.iew.iewDispStoreInsts             14407100                       # Number of dispatched store instructions
system.cpu.iew.iewDispNonSpecInsts              23547                       # Number of dispatched non-speculative instructions
system.cpu.iew.iewIQFullEvents                   3855                       # Number of times the IQ has become full, causing a stall
system.cpu.iew.iewLSQFullEvents                 55872                       # Number of times the LSQ has become full, causing a stall
system.cpu.iew.memOrderViolationEvents           7034                       # Number of memory order violations
system.cpu.iew.predictedTakenIncorrect        3149041                       # Number of branches that were predicted taken incorrectly
system.cpu.iew.predictedNotTakenIncorrect      3246654                       # Number of branches that were predicted not taken incorrectly
system.cpu.iew.branchMispredicts              6395695                       # Number of branch mispredicts detected at execute
system.cpu.iew.iewExecutedInsts             207125960                       # Number of executed instructions
system.cpu.iew.iewExecLoadInsts              30633355                       # Number of load instructions executed
system.cpu.iew.iewExecSquashedInsts           7285843                       # Number of squashed instructions skipped in execute
system.cpu.iew.exec_swp                             0                       # number of swp insts executed
system.cpu.iew.exec_nop                         20217                       # number of nop insts executed
system.cpu.iew.exec_refs                     43771495                       # number of memory reference insts executed
system.cpu.iew.exec_branches                 44852998                       # Number of branches executed
system.cpu.iew.exec_stores                   13138140                       # Number of stores executed
system.cpu.iew.exec_rate                     1.219281                       # Inst execution rate
system.cpu.iew.wb_sent                      206368045                       # cumulative count of insts sent to commit
system.cpu.iew.wb_count                     206057927                       # cumulative count of insts written-back
system.cpu.iew.wb_producers                 129397136                       # num instructions producing a value
system.cpu.iew.wb_consumers                 221651580                       # num instructions consuming a value
system.cpu.iew.wb_rate                       1.212994                       # insts written-back per cycle
system.cpu.iew.wb_fanout                     0.583786                       # average fanout of values written-back
system.cpu.commit.commitSquashedInsts        68672645                       # The number of squashed insts skipped by commit
system.cpu.commit.commitNonSpecStalls           45216                       # The number of times commit has been forced to stall to communicate backwards
system.cpu.commit.branchMispredicts           5760731                       # The number of times a branch was mispredicted
system.cpu.commit.committed_per_cycle::samples    157823719                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::mean     1.150970                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::stdev     1.652577                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::underflows            0      0.00%      0.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::0     73232232     46.40%     46.40% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::1     41142749     26.07%     72.47% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::2     22534270     14.28%     86.75% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::3      9514853      6.03%     92.78% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::4      3552076      2.25%     95.03% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::5      2143258      1.36%     96.39% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::6      1327703      0.84%     97.23% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::7      1008942      0.64%     97.87% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::8      3367636      2.13%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows            0      0.00%    100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value            0                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value            8                       # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::total    157823719                       # Number of insts commited each cycle
system.cpu.commit.committedInsts            172317410                       # Number of instructions committed
system.cpu.commit.committedOps              181650342                       # Number of ops (including micro ops) committed
system.cpu.commit.swp_count                         0                       # Number of s/w prefetches committed
system.cpu.commit.refs                       40540778                       # Number of memory references committed
system.cpu.commit.loads                      27896144                       # Number of loads committed
system.cpu.commit.membars                       22408                       # Number of memory barriers committed
system.cpu.commit.branches                   40300312                       # Number of branches committed
system.cpu.commit.fp_insts                    1752310                       # Number of committed floating point instructions.
system.cpu.commit.int_insts                 143085667                       # Number of committed integer instructions.
system.cpu.commit.function_calls              1848934                       # Number of function calls committed.
system.cpu.commit.op_class_0::No_OpClass            0      0.00%      0.00% # Class of committed instruction
system.cpu.commit.op_class_0::IntAlu        138987813     76.51%     76.51% # Class of committed instruction
system.cpu.commit.op_class_0::IntMult          908940      0.50%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::IntDiv                0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatAdd              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCmp              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatCvt              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatMult             0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatDiv              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::FloatSqrt             0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAdd               0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAddAcc            0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdAlu               0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCmp               0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdCvt               0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMisc              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMult              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdMultAcc            0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShift             0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdShiftAcc            0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdSqrt              0      0.00%     77.01% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAdd        32754      0.02%     77.03% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatAlu            0      0.00%     77.03% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCmp       154829      0.09%     77.12% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatCvt       238880      0.13%     77.25% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatDiv        76016      0.04%     77.29% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMisc       437591      0.24%     77.53% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMult       200806      0.11%     77.64% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatMultAcc        71617      0.04%     77.68% # Class of committed instruction
system.cpu.commit.op_class_0::SimdFloatSqrt          318      0.00%     77.68% # Class of committed instruction
system.cpu.commit.op_class_0::MemRead        27896144     15.36%     93.04% # Class of committed instruction
system.cpu.commit.op_class_0::MemWrite       12644634      6.96%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::IprAccess             0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::InstPrefetch            0      0.00%    100.00% # Class of committed instruction
system.cpu.commit.op_class_0::total         181650342                       # Class of committed instruction
system.cpu.commit.bw_lim_events               3367636                       # number cycles where commit BW limit reached
system.cpu.rob.rob_reads                    404773869                       # The number of ROB reads
system.cpu.rob.rob_writes                   511956769                       # The number of ROB writes
system.cpu.timesIdled                            9030                       # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles                          754928                       # Total number of cycles that the CPU has spent unscheduled due to idling
system.cpu.committedInsts                   172303022                       # Number of Instructions Simulated
system.cpu.committedOps                     181635954                       # Number of Ops (including micro ops) Simulated
system.cpu.cpi                               0.985911                       # CPI: Cycles Per Instruction
system.cpu.cpi_total                         0.985911                       # CPI: Total CPI of All Threads
system.cpu.ipc                               1.014290                       # IPC: Instructions Per Cycle
system.cpu.ipc_total                         1.014290                       # IPC: Total IPC of All Threads
system.cpu.int_regfile_reads                218725741                       # number of integer regfile reads
system.cpu.int_regfile_writes               114168991                       # number of integer regfile writes
system.cpu.fp_regfile_reads                   2904222                       # number of floating regfile reads
system.cpu.fp_regfile_writes                  2441435                       # number of floating regfile writes
system.cpu.cc_regfile_reads                 708194084                       # number of cc regfile reads
system.cpu.cc_regfile_writes                229512691                       # number of cc regfile writes
system.cpu.misc_regfile_reads                59249211                       # number of misc regfile reads
system.cpu.misc_regfile_writes                 820036                       # number of misc regfile writes
system.cpu.dcache.tags.replacements             72581                       # number of replacements
system.cpu.dcache.tags.tagsinuse           511.413915                       # Cycle average of tags in use
system.cpu.dcache.tags.total_refs            41031177                       # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs             73093                       # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs            561.355766                       # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle         508221500                       # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data   511.413915                       # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data     0.998855                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total     0.998855                       # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0           55                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1          162                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2          229                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3           44                       # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4           22                       # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses          82360603                       # Number of tag accesses
system.cpu.dcache.tags.data_accesses         82360603                       # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data     28644947                       # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total        28644947                       # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data     12341311                       # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total       12341311                       # number of WriteReq hits
system.cpu.dcache.SoftPFReq_hits::cpu.data          364                       # number of SoftPFReq hits
system.cpu.dcache.SoftPFReq_hits::total           364                       # number of SoftPFReq hits
system.cpu.dcache.LoadLockedReq_hits::cpu.data        22148                       # number of LoadLockedReq hits
system.cpu.dcache.LoadLockedReq_hits::total        22148                       # number of LoadLockedReq hits
system.cpu.dcache.StoreCondReq_hits::cpu.data        22407                       # number of StoreCondReq hits
system.cpu.dcache.StoreCondReq_hits::total        22407                       # number of StoreCondReq hits
system.cpu.dcache.demand_hits::cpu.data      40986258                       # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total         40986258                       # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data     40986622                       # number of overall hits
system.cpu.dcache.overall_hits::total        40986622                       # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data        89227                       # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total         89227                       # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data        22976                       # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total        22976                       # number of WriteReq misses
system.cpu.dcache.SoftPFReq_misses::cpu.data          116                       # number of SoftPFReq misses
system.cpu.dcache.SoftPFReq_misses::total          116                       # number of SoftPFReq misses
system.cpu.dcache.LoadLockedReq_misses::cpu.data          259                       # number of LoadLockedReq misses
system.cpu.dcache.LoadLockedReq_misses::total          259                       # number of LoadLockedReq misses
system.cpu.dcache.demand_misses::cpu.data       112203                       # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total         112203                       # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data       112319                       # number of overall misses
system.cpu.dcache.overall_misses::total        112319                       # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data   1066843000                       # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total   1066843000                       # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data    241030499                       # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total    241030499                       # number of WriteReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data      2297500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.LoadLockedReq_miss_latency::total      2297500                       # number of LoadLockedReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data   1307873499                       # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total   1307873499                       # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data   1307873499                       # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total   1307873499                       # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data     28734174                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total     28734174                       # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data     12364287                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total     12364287                       # number of WriteReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::cpu.data          480                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.SoftPFReq_accesses::total          480                       # number of SoftPFReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::cpu.data        22407                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.LoadLockedReq_accesses::total        22407                       # number of LoadLockedReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::cpu.data        22407                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.StoreCondReq_accesses::total        22407                       # number of StoreCondReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data     41098461                       # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total     41098461                       # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data     41098941                       # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total     41098941                       # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data     0.003105                       # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total     0.003105                       # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data     0.001858                       # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total     0.001858                       # miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::cpu.data     0.241667                       # miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_miss_rate::total     0.241667                       # miss rate for SoftPFReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data     0.011559                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.LoadLockedReq_miss_rate::total     0.011559                       # miss rate for LoadLockedReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data     0.002730                       # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total     0.002730                       # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data     0.002733                       # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total     0.002733                       # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 11956.504197                       # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 11956.504197                       # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 10490.533557                       # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 10490.533557                       # average WriteReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data  8870.656371                       # average LoadLockedReq miss latency
system.cpu.dcache.LoadLockedReq_avg_miss_latency::total  8870.656371                       # average LoadLockedReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 11656.314885                       # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 11656.314885                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 11644.276561                       # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 11644.276561                       # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs          166                       # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets        10738                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs                 2                       # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets             864                       # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs           83                       # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets    12.428241                       # average number of cycles each access was blocked
system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
system.cpu.dcache.writebacks::writebacks        72581                       # number of writebacks
system.cpu.dcache.writebacks::total             72581                       # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data        24802                       # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total        24802                       # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data        14421                       # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total        14421                       # number of WriteReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::cpu.data          259                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.LoadLockedReq_mshr_hits::total          259                       # number of LoadLockedReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data        39223                       # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total        39223                       # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data        39223                       # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total        39223                       # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data        64425                       # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total        64425                       # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data         8555                       # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total         8555                       # number of WriteReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data          113                       # number of SoftPFReq MSHR misses
system.cpu.dcache.SoftPFReq_mshr_misses::total          113                       # number of SoftPFReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data        72980                       # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total        72980                       # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data        73093                       # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total        73093                       # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data    653903000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total    653903000                       # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data     85317499                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total     85317499                       # number of WriteReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data       962000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.SoftPFReq_mshr_miss_latency::total       962000                       # number of SoftPFReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data    739220499                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total    739220499                       # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data    740182499                       # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total    740182499                       # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data     0.002242                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total     0.002242                       # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data     0.000692                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total     0.000692                       # mshr miss rate for WriteReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data     0.235417                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.SoftPFReq_mshr_miss_rate::total     0.235417                       # mshr miss rate for SoftPFReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data     0.001776                       # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total     0.001776                       # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data     0.001778                       # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total     0.001778                       # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 10149.833139                       # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 10149.833139                       # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data  9972.822794                       # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total  9972.822794                       # average WriteReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data  8513.274336                       # average SoftPFReq mshr miss latency
system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total  8513.274336                       # average SoftPFReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 10129.083297                       # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 10129.083297                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 10126.585295                       # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 10126.585295                       # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.icache.tags.replacements             53623                       # number of replacements
system.cpu.icache.tags.tagsinuse           510.594536                       # Cycle average of tags in use
system.cpu.icache.tags.total_refs            78269055                       # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs             54135                       # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs           1445.812413                       # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle       84183071500                       # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst   510.594536                       # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst     0.997255                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total     0.997255                       # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024          512                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0           83                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1          100                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2          276                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3            2                       # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4           51                       # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024            1                       # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses         156707315                       # Number of tag accesses
system.cpu.icache.tags.data_accesses        156707315                       # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst     78269055                       # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total        78269055                       # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst      78269055                       # number of demand (read+write) hits
system.cpu.icache.demand_hits::total         78269055                       # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst     78269055                       # number of overall hits
system.cpu.icache.overall_hits::total        78269055                       # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst        57535                       # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total         57535                       # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst        57535                       # number of demand (read+write) misses
system.cpu.icache.demand_misses::total          57535                       # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst        57535                       # number of overall misses
system.cpu.icache.overall_misses::total         57535                       # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst   1155198430                       # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total   1155198430                       # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst   1155198430                       # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total   1155198430                       # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst   1155198430                       # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total   1155198430                       # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst     78326590                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total     78326590                       # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst     78326590                       # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total     78326590                       # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst     78326590                       # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total     78326590                       # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst     0.000735                       # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total     0.000735                       # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst     0.000735                       # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total     0.000735                       # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst     0.000735                       # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total     0.000735                       # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20078.185974                       # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 20078.185974                       # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 20078.185974                       # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 20078.185974                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 20078.185974                       # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 20078.185974                       # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs        73195                       # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets           27                       # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs              3246                       # number of cycles access was blocked
system.cpu.icache.blocked::no_targets               2                       # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs    22.549291                       # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets    13.500000                       # average number of cycles each access was blocked
system.cpu.icache.fast_writes                       0                       # number of fast writes performed
system.cpu.icache.cache_copies                      0                       # number of cache copies performed
system.cpu.icache.writebacks::writebacks        53623                       # number of writebacks
system.cpu.icache.writebacks::total             53623                       # number of writebacks
system.cpu.icache.ReadReq_mshr_hits::cpu.inst         3399                       # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total         3399                       # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst         3399                       # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total         3399                       # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst         3399                       # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total         3399                       # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst        54136                       # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total        54136                       # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst        54136                       # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total        54136                       # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst        54136                       # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total        54136                       # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst   1039886452                       # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total   1039886452                       # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst   1039886452                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total   1039886452                       # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst   1039886452                       # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total   1039886452                       # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst     0.000691                       # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total     0.000691                       # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst     0.000691                       # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total     0.000691                       # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst     0.000691                       # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total     0.000691                       # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19208.778853                       # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19208.778853                       # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19208.778853                       # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 19208.778853                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19208.778853                       # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 19208.778853                       # average overall mshr miss latency
system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
system.cpu.l2cache.prefetcher.num_hwpf_issued         9269                       # number of hwpf issued
system.cpu.l2cache.prefetcher.pfIdentified         9269                       # number of prefetch candidates identified
system.cpu.l2cache.prefetcher.pfBufferHit            0                       # number of redundant prefetches already in prefetch queue
system.cpu.l2cache.prefetcher.pfInCache             0                       # number of redundant prefetches already in cache/mshr dropped
system.cpu.l2cache.prefetcher.pfRemovedFull            0                       # number of prefetches dropped due to prefetch queue size
system.cpu.l2cache.prefetcher.pfSpanPage         1371                       # number of prefetches not generated due to page crossing
system.cpu.l2cache.tags.replacements                0                       # number of replacements
system.cpu.l2cache.tags.tagsinuse         2141.370901                       # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs             157591                       # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs             3198                       # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs            49.277986                       # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle                0                       # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks  1986.257511                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.l2cache.prefetcher   155.113391                       # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks     0.121232                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.l2cache.prefetcher     0.009467                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total     0.130699                       # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1022          254                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_blocks::1024         2944                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::0            2                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::1           24                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::2           87                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1022::4          141                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0           79                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1          194                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2          856                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3          162                       # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4         1653                       # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1022     0.015503                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024     0.179688                       # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses          3955418                       # Number of tag accesses
system.cpu.l2cache.tags.data_accesses         3955418                       # Number of data accesses
system.cpu.l2cache.WritebackDirty_hits::writebacks        64698                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackDirty_hits::total        64698                       # number of WritebackDirty hits
system.cpu.l2cache.WritebackClean_hits::writebacks        51033                       # number of WritebackClean hits
system.cpu.l2cache.WritebackClean_hits::total        51033                       # number of WritebackClean hits
system.cpu.l2cache.ReadExReq_hits::cpu.data         8387                       # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total         8387                       # number of ReadExReq hits
system.cpu.l2cache.ReadCleanReq_hits::cpu.inst        44953                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadCleanReq_hits::total        44953                       # number of ReadCleanReq hits
system.cpu.l2cache.ReadSharedReq_hits::cpu.data        62632                       # number of ReadSharedReq hits
system.cpu.l2cache.ReadSharedReq_hits::total        62632                       # number of ReadSharedReq hits
system.cpu.l2cache.demand_hits::cpu.inst        44953                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data        71019                       # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total          115972                       # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst        44953                       # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data        71019                       # number of overall hits
system.cpu.l2cache.overall_hits::total         115972                       # number of overall hits
system.cpu.l2cache.ReadExReq_misses::cpu.data          235                       # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total          235                       # number of ReadExReq misses
system.cpu.l2cache.ReadCleanReq_misses::cpu.inst         9183                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadCleanReq_misses::total         9183                       # number of ReadCleanReq misses
system.cpu.l2cache.ReadSharedReq_misses::cpu.data         1839                       # number of ReadSharedReq misses
system.cpu.l2cache.ReadSharedReq_misses::total         1839                       # number of ReadSharedReq misses
system.cpu.l2cache.demand_misses::cpu.inst         9183                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data         2074                       # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total         11257                       # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst         9183                       # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data         2074                       # number of overall misses
system.cpu.l2cache.overall_misses::total        11257                       # number of overall misses
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data     18101500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total     18101500                       # number of ReadExReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst    689865000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadCleanReq_miss_latency::total    689865000                       # number of ReadCleanReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data    142794500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.ReadSharedReq_miss_latency::total    142794500                       # number of ReadSharedReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst    689865000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data    160896000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total    850761000                       # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst    689865000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data    160896000                       # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total    850761000                       # number of overall miss cycles
system.cpu.l2cache.WritebackDirty_accesses::writebacks        64698                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackDirty_accesses::total        64698                       # number of WritebackDirty accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::writebacks        51033                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.WritebackClean_accesses::total        51033                       # number of WritebackClean accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data         8622                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total         8622                       # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst        54136                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadCleanReq_accesses::total        54136                       # number of ReadCleanReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::cpu.data        64471                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.ReadSharedReq_accesses::total        64471                       # number of ReadSharedReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst        54136                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data        73093                       # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total       127229                       # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst        54136                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data        73093                       # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total       127229                       # number of overall (read+write) accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data     0.027256                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total     0.027256                       # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst     0.169628                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_miss_rate::total     0.169628                       # miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data     0.028524                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_miss_rate::total     0.028524                       # miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst     0.169628                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data     0.028375                       # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total     0.088478                       # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst     0.169628                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data     0.028375                       # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total     0.088478                       # miss rate for overall accesses
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 77027.659574                       # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 77027.659574                       # average ReadExReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 75124.142437                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 75124.142437                       # average ReadCleanReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 77647.906471                       # average ReadSharedReq miss latency
system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 77647.906471                       # average ReadSharedReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 75124.142437                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 77577.627772                       # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 75576.174825                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 75124.142437                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 77577.627772                       # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 75576.174825                       # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets            0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs                0                       # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets              0                       # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets          nan                       # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
system.cpu.l2cache.ReadExReq_mshr_hits::cpu.data            1                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadExReq_mshr_hits::total            1                       # number of ReadExReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst            5                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadCleanReq_mshr_hits::total            5                       # number of ReadCleanReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data            9                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.ReadSharedReq_mshr_hits::total            9                       # number of ReadSharedReq MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.inst            5                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::cpu.data           10                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.demand_mshr_hits::total           15                       # number of demand (read+write) MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.inst            5                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::cpu.data           10                       # number of overall MSHR hits
system.cpu.l2cache.overall_mshr_hits::total           15                       # number of overall MSHR hits
system.cpu.l2cache.HardPFReq_mshr_misses::cpu.l2cache.prefetcher         2007                       # number of HardPFReq MSHR misses
system.cpu.l2cache.HardPFReq_mshr_misses::total         2007                       # number of HardPFReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data          234                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total          234                       # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst         9178                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadCleanReq_mshr_misses::total         9178                       # number of ReadCleanReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data         1830                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.ReadSharedReq_mshr_misses::total         1830                       # number of ReadSharedReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst         9178                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data         2064                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total        11242                       # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst         9178                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data         2064                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.l2cache.prefetcher         2007                       # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total        13249                       # number of overall MSHR misses
system.cpu.l2cache.HardPFReq_mshr_miss_latency::cpu.l2cache.prefetcher     68828649                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_latency::total     68828649                       # number of HardPFReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data     16491500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total     16491500                       # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst    634496500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total    634496500                       # number of ReadCleanReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data    131272000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total    131272000                       # number of ReadSharedReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst    634496500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data    147763500                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total    782260000                       # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst    634496500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data    147763500                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.l2cache.prefetcher     68828649                       # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total    851088649                       # number of overall MSHR miss cycles
system.cpu.l2cache.HardPFReq_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.HardPFReq_mshr_miss_rate::total          inf                       # mshr miss rate for HardPFReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data     0.027140                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total     0.027140                       # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst     0.169536                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total     0.169536                       # mshr miss rate for ReadCleanReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data     0.028385                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total     0.028385                       # mshr miss rate for ReadSharedReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst     0.169536                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data     0.028238                       # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total     0.088360                       # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst     0.169536                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data     0.028238                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.l2cache.prefetcher          inf                       # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total     0.104135                       # mshr miss rate for overall accesses
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34294.294469                       # average HardPFReq mshr miss latency
system.cpu.l2cache.HardPFReq_avg_mshr_miss_latency::total 34294.294469                       # average HardPFReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70476.495726                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70476.495726                       # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 69132.327304                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 69132.327304                       # average ReadCleanReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71733.333333                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71733.333333                       # average ReadSharedReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 69132.327304                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71590.843023                       # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69583.703967                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 69132.327304                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71590.843023                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.l2cache.prefetcher 34294.294469                       # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 64237.953732                       # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
system.cpu.toL2Bus.snoop_filter.tot_requests       253433                       # Total number of requests made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_requests       126224                       # Number of requests hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_requests        10473                       # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.snoop_filter.tot_snoops        11905                       # Total number of snoops made to the snoop filter.
system.cpu.toL2Bus.snoop_filter.hit_single_snoops         3377                       # Number of snoops hitting in the snoop filter with a single holder of the requested data.
system.cpu.toL2Bus.snoop_filter.hit_multi_snoops         8528                       # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
system.cpu.toL2Bus.trans_dist::ReadResp        118606                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackDirty        64698                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::WritebackClean        61506                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::CleanEvict        11007                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::HardPFReq         2350                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq         8622                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp         8622                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadCleanReq        54136                       # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadSharedReq        64471                       # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side       161894                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side       218767                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total            380661                       # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side      6896512                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side      9323136                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_size::total           16219648                       # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.snoops                       13357                       # Total snoops (count)
system.cpu.toL2Bus.snoop_fanout::samples       140586                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::mean        0.219979                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::stdev       0.541213                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::underflows            0      0.00%      0.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::0             118188     84.07%     84.07% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::1              13870      9.87%     93.93% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::2               8528      6.07%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::overflows            0      0.00%    100.00% # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::min_value            0                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::max_value            2                       # Request fanout histogram
system.cpu.toL2Bus.snoop_fanout::total         140586                       # Request fanout histogram
system.cpu.toL2Bus.reqLayer0.occupancy      252920500                       # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization          0.3                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy      81207989                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization          0.1                       # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy     109644490                       # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization          0.1                       # Layer utilization (%)
system.membus.trans_dist::ReadResp              12116                       # Transaction distribution
system.membus.trans_dist::ReadExReq               234                       # Transaction distribution
system.membus.trans_dist::ReadExResp              234                       # Transaction distribution
system.membus.trans_dist::ReadSharedReq         12117                       # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port        24701                       # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total                  24701                       # Packet count per connected master and slave (bytes)
system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port       790400                       # Cumulative packet size per connected master and slave (bytes)
system.membus.pkt_size::total                  790400                       # Cumulative packet size per connected master and slave (bytes)
system.membus.snoops                                0                       # Total snoops (count)
system.membus.snoop_fanout::samples             12351                       # Request fanout histogram
system.membus.snoop_fanout::mean                    0                       # Request fanout histogram
system.membus.snoop_fanout::stdev                   0                       # Request fanout histogram
system.membus.snoop_fanout::underflows              0      0.00%      0.00% # Request fanout histogram
system.membus.snoop_fanout::0                   12351    100.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::1                       0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::overflows               0      0.00%    100.00% # Request fanout histogram
system.membus.snoop_fanout::min_value               0                       # Request fanout histogram
system.membus.snoop_fanout::max_value               0                       # Request fanout histogram
system.membus.snoop_fanout::total               12351                       # Request fanout histogram
system.membus.reqLayer0.occupancy            15618188                       # Layer occupancy (ticks)
system.membus.reqLayer0.utilization               0.0                       # Layer utilization (%)
system.membus.respLayer1.occupancy           66520835                       # Layer occupancy (ticks)
system.membus.respLayer1.utilization              0.1                       # Layer utilization (%)

---------- End Simulation Statistics   ----------