commit 0fa5ed40c471429318c967833592aee0bd361dea
author Giacomo Travaglini <giacomo.travaglini@arm.com> Tue Mar 27 14:23:28 2018 +0100
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Fri Apr 06 09:58:41 2018 +0000
tree c532523a3f4bf4fec53d07d8f61190efa89255ac
parent 906ef2f7cd043339ea917c9bf744210dc45999a9

arch-arm: Correct mcrr,mrrc disassemble

This patch is fixing AArch32 mcrr,mrrc instruction disassemble by
printing the correct source/destination registers

Change-Id: I3fcffa0349aeee466e7c60ba4d1244824fb65d91
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9501
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

src/arch/arm/insts/misc.cc

diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index 9c7a051..d4a2ba2 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -153,7 +153,7 @@
     ss << ", ";
     printIntReg(ss, dest2);
     ss << ", ";
-    printIntReg(ss, op1);
+    printMiscReg(ss, op1);
     return ss.str();
 }
 
@@ -162,7 +162,7 @@
 {
     std::stringstream ss;
     printMnemonic(ss);
-    printIntReg(ss, dest);
+    printMiscReg(ss, dest);
     ss << ", ";
     printIntReg(ss, op1);
     ss << ", ";