| |
| ---------- Begin Simulation Statistics ---------- |
| sim_seconds 0.000372 |
| sim_ticks 372284000 |
| final_tick 372284000 |
| sim_freq 1000000000000 |
| host_inst_rate 111411 |
| host_op_rate 128815 |
| host_tick_rate 8307715104 |
| host_mem_usage 662496 |
| host_seconds 0.05 |
| sim_insts 4988 |
| sim_ops 5770 |
| system.clk_domain.voltage_domain.voltage 1 |
| system.clk_domain.clock 1000 |
| system.mem_ctrl.pwrStateResidencyTicks::UNDEFINED 372284000 |
| system.mem_ctrl.bytes_read::cpu.inst 20108 |
| system.mem_ctrl.bytes_read::cpu.data 4672 |
| system.mem_ctrl.bytes_read::total 24780 |
| system.mem_ctrl.bytes_inst_read::cpu.inst 20108 |
| system.mem_ctrl.bytes_inst_read::total 20108 |
| system.mem_ctrl.bytes_written::cpu.data 3696 |
| system.mem_ctrl.bytes_written::total 3696 |
| system.mem_ctrl.num_reads::cpu.inst 5027 |
| system.mem_ctrl.num_reads::cpu.data 1061 |
| system.mem_ctrl.num_reads::total 6088 |
| system.mem_ctrl.num_writes::cpu.data 936 |
| system.mem_ctrl.num_writes::total 936 |
| system.mem_ctrl.bw_read::cpu.inst 54012528 |
| system.mem_ctrl.bw_read::cpu.data 12549559 |
| system.mem_ctrl.bw_read::total 66562087 |
| system.mem_ctrl.bw_inst_read::cpu.inst 54012528 |
| system.mem_ctrl.bw_inst_read::total 54012528 |
| system.mem_ctrl.bw_write::cpu.data 9927905 |
| system.mem_ctrl.bw_write::total 9927905 |
| system.mem_ctrl.bw_total::cpu.inst 54012528 |
| system.mem_ctrl.bw_total::cpu.data 22477463 |
| system.mem_ctrl.bw_total::total 76489992 |
| system.mem_ctrl.readReqs 6089 |
| system.mem_ctrl.writeReqs 936 |
| system.mem_ctrl.readBursts 6089 |
| system.mem_ctrl.writeBursts 936 |
| system.mem_ctrl.bytesReadDRAM 383296 |
| system.mem_ctrl.bytesReadWrQ 6400 |
| system.mem_ctrl.bytesWritten 4096 |
| system.mem_ctrl.bytesReadSys 24784 |
| system.mem_ctrl.bytesWrittenSys 3696 |
| system.mem_ctrl.servicedByWrQ 100 |
| system.mem_ctrl.mergedWrBursts 855 |
| system.mem_ctrl.neitherReadNorWriteReqs 0 |
| system.mem_ctrl.perBankRdBursts::0 911 |
| system.mem_ctrl.perBankRdBursts::1 1454 |
| system.mem_ctrl.perBankRdBursts::2 724 |
| system.mem_ctrl.perBankRdBursts::3 364 |
| system.mem_ctrl.perBankRdBursts::4 505 |
| system.mem_ctrl.perBankRdBursts::5 303 |
| system.mem_ctrl.perBankRdBursts::6 487 |
| system.mem_ctrl.perBankRdBursts::7 206 |
| system.mem_ctrl.perBankRdBursts::8 42 |
| system.mem_ctrl.perBankRdBursts::9 155 |
| system.mem_ctrl.perBankRdBursts::10 192 |
| system.mem_ctrl.perBankRdBursts::11 422 |
| system.mem_ctrl.perBankRdBursts::12 108 |
| system.mem_ctrl.perBankRdBursts::13 36 |
| system.mem_ctrl.perBankRdBursts::14 0 |
| system.mem_ctrl.perBankRdBursts::15 80 |
| system.mem_ctrl.perBankWrBursts::0 0 |
| system.mem_ctrl.perBankWrBursts::1 0 |
| system.mem_ctrl.perBankWrBursts::2 0 |
| system.mem_ctrl.perBankWrBursts::3 0 |
| system.mem_ctrl.perBankWrBursts::4 0 |
| system.mem_ctrl.perBankWrBursts::5 0 |
| system.mem_ctrl.perBankWrBursts::6 0 |
| system.mem_ctrl.perBankWrBursts::7 0 |
| system.mem_ctrl.perBankWrBursts::8 0 |
| system.mem_ctrl.perBankWrBursts::9 0 |
| system.mem_ctrl.perBankWrBursts::10 13 |
| system.mem_ctrl.perBankWrBursts::11 46 |
| system.mem_ctrl.perBankWrBursts::12 5 |
| system.mem_ctrl.perBankWrBursts::13 0 |
| system.mem_ctrl.perBankWrBursts::14 0 |
| system.mem_ctrl.perBankWrBursts::15 0 |
| system.mem_ctrl.numRdRetry 0 |
| system.mem_ctrl.numWrRetry 0 |
| system.mem_ctrl.totGap 372207000 |
| system.mem_ctrl.readPktSize::0 70 |
| system.mem_ctrl.readPktSize::1 1 |
| system.mem_ctrl.readPktSize::2 5858 |
| system.mem_ctrl.readPktSize::3 160 |
| system.mem_ctrl.readPktSize::4 0 |
| system.mem_ctrl.readPktSize::5 0 |
| system.mem_ctrl.readPktSize::6 0 |
| system.mem_ctrl.writePktSize::0 16 |
| system.mem_ctrl.writePktSize::1 0 |
| system.mem_ctrl.writePktSize::2 920 |
| system.mem_ctrl.writePktSize::3 0 |
| system.mem_ctrl.writePktSize::4 0 |
| system.mem_ctrl.writePktSize::5 0 |
| system.mem_ctrl.writePktSize::6 0 |
| system.mem_ctrl.rdQLenPdf::0 5980 |
| system.mem_ctrl.rdQLenPdf::1 9 |
| system.mem_ctrl.rdQLenPdf::2 0 |
| system.mem_ctrl.rdQLenPdf::3 0 |
| system.mem_ctrl.rdQLenPdf::4 0 |
| system.mem_ctrl.rdQLenPdf::5 0 |
| system.mem_ctrl.rdQLenPdf::6 0 |
| system.mem_ctrl.rdQLenPdf::7 0 |
| system.mem_ctrl.rdQLenPdf::8 0 |
| system.mem_ctrl.rdQLenPdf::9 0 |
| system.mem_ctrl.rdQLenPdf::10 0 |
| system.mem_ctrl.rdQLenPdf::11 0 |
| system.mem_ctrl.rdQLenPdf::12 0 |
| system.mem_ctrl.rdQLenPdf::13 0 |
| system.mem_ctrl.rdQLenPdf::14 0 |
| system.mem_ctrl.rdQLenPdf::15 0 |
| system.mem_ctrl.rdQLenPdf::16 0 |
| system.mem_ctrl.rdQLenPdf::17 0 |
| system.mem_ctrl.rdQLenPdf::18 0 |
| system.mem_ctrl.rdQLenPdf::19 0 |
| system.mem_ctrl.rdQLenPdf::20 0 |
| system.mem_ctrl.rdQLenPdf::21 0 |
| system.mem_ctrl.rdQLenPdf::22 0 |
| system.mem_ctrl.rdQLenPdf::23 0 |
| system.mem_ctrl.rdQLenPdf::24 0 |
| system.mem_ctrl.rdQLenPdf::25 0 |
| system.mem_ctrl.rdQLenPdf::26 0 |
| system.mem_ctrl.rdQLenPdf::27 0 |
| system.mem_ctrl.rdQLenPdf::28 0 |
| system.mem_ctrl.rdQLenPdf::29 0 |
| system.mem_ctrl.rdQLenPdf::30 0 |
| system.mem_ctrl.rdQLenPdf::31 0 |
| system.mem_ctrl.wrQLenPdf::0 1 |
| system.mem_ctrl.wrQLenPdf::1 1 |
| system.mem_ctrl.wrQLenPdf::2 1 |
| system.mem_ctrl.wrQLenPdf::3 1 |
| system.mem_ctrl.wrQLenPdf::4 1 |
| system.mem_ctrl.wrQLenPdf::5 1 |
| system.mem_ctrl.wrQLenPdf::6 1 |
| system.mem_ctrl.wrQLenPdf::7 1 |
| system.mem_ctrl.wrQLenPdf::8 1 |
| system.mem_ctrl.wrQLenPdf::9 1 |
| system.mem_ctrl.wrQLenPdf::10 1 |
| system.mem_ctrl.wrQLenPdf::11 1 |
| system.mem_ctrl.wrQLenPdf::12 1 |
| system.mem_ctrl.wrQLenPdf::13 1 |
| system.mem_ctrl.wrQLenPdf::14 1 |
| system.mem_ctrl.wrQLenPdf::15 1 |
| system.mem_ctrl.wrQLenPdf::16 1 |
| system.mem_ctrl.wrQLenPdf::17 4 |
| system.mem_ctrl.wrQLenPdf::18 4 |
| system.mem_ctrl.wrQLenPdf::19 4 |
| system.mem_ctrl.wrQLenPdf::20 4 |
| system.mem_ctrl.wrQLenPdf::21 4 |
| system.mem_ctrl.wrQLenPdf::22 4 |
| system.mem_ctrl.wrQLenPdf::23 4 |
| system.mem_ctrl.wrQLenPdf::24 4 |
| system.mem_ctrl.wrQLenPdf::25 4 |
| system.mem_ctrl.wrQLenPdf::26 4 |
| system.mem_ctrl.wrQLenPdf::27 4 |
| system.mem_ctrl.wrQLenPdf::28 4 |
| system.mem_ctrl.wrQLenPdf::29 4 |
| system.mem_ctrl.wrQLenPdf::30 4 |
| system.mem_ctrl.wrQLenPdf::31 4 |
| system.mem_ctrl.wrQLenPdf::32 4 |
| system.mem_ctrl.wrQLenPdf::33 0 |
| system.mem_ctrl.wrQLenPdf::34 0 |
| system.mem_ctrl.wrQLenPdf::35 0 |
| system.mem_ctrl.wrQLenPdf::36 0 |
| system.mem_ctrl.wrQLenPdf::37 0 |
| system.mem_ctrl.wrQLenPdf::38 0 |
| system.mem_ctrl.wrQLenPdf::39 0 |
| system.mem_ctrl.wrQLenPdf::40 0 |
| system.mem_ctrl.wrQLenPdf::41 0 |
| system.mem_ctrl.wrQLenPdf::42 0 |
| system.mem_ctrl.wrQLenPdf::43 0 |
| system.mem_ctrl.wrQLenPdf::44 0 |
| system.mem_ctrl.wrQLenPdf::45 0 |
| system.mem_ctrl.wrQLenPdf::46 0 |
| system.mem_ctrl.wrQLenPdf::47 0 |
| system.mem_ctrl.wrQLenPdf::48 0 |
| system.mem_ctrl.wrQLenPdf::49 0 |
| system.mem_ctrl.wrQLenPdf::50 0 |
| system.mem_ctrl.wrQLenPdf::51 0 |
| system.mem_ctrl.wrQLenPdf::52 0 |
| system.mem_ctrl.wrQLenPdf::53 0 |
| system.mem_ctrl.wrQLenPdf::54 0 |
| system.mem_ctrl.wrQLenPdf::55 0 |
| system.mem_ctrl.wrQLenPdf::56 0 |
| system.mem_ctrl.wrQLenPdf::57 0 |
| system.mem_ctrl.wrQLenPdf::58 0 |
| system.mem_ctrl.wrQLenPdf::59 0 |
| system.mem_ctrl.wrQLenPdf::60 0 |
| system.mem_ctrl.wrQLenPdf::61 0 |
| system.mem_ctrl.wrQLenPdf::62 0 |
| system.mem_ctrl.wrQLenPdf::63 0 |
| system.mem_ctrl.bytesPerActivate::samples 514 |
| system.mem_ctrl.bytesPerActivate::mean 749.322957 |
| system.mem_ctrl.bytesPerActivate::gmean 608.037375 |
| system.mem_ctrl.bytesPerActivate::stdev 344.826867 |
| system.mem_ctrl.bytesPerActivate::0-127 25 4.86% 4.86% |
| system.mem_ctrl.bytesPerActivate::128-255 42 8.17% 13.04% |
| system.mem_ctrl.bytesPerActivate::256-383 44 8.56% 21.60% |
| system.mem_ctrl.bytesPerActivate::384-511 26 5.06% 26.65% |
| system.mem_ctrl.bytesPerActivate::512-639 25 4.86% 31.52% |
| system.mem_ctrl.bytesPerActivate::640-767 34 6.61% 38.13% |
| system.mem_ctrl.bytesPerActivate::768-895 27 5.25% 43.39% |
| system.mem_ctrl.bytesPerActivate::896-1023 27 5.25% 48.64% |
| system.mem_ctrl.bytesPerActivate::1024-1151 264 51.36% 100.00% |
| system.mem_ctrl.bytesPerActivate::total 514 |
| system.mem_ctrl.rdPerTurnAround::samples 4 |
| system.mem_ctrl.rdPerTurnAround::mean 1490.500000 |
| system.mem_ctrl.rdPerTurnAround::gmean 1373.591360 |
| system.mem_ctrl.rdPerTurnAround::stdev 606.712727 |
| system.mem_ctrl.rdPerTurnAround::640-767 1 25.00% 25.00% |
| system.mem_ctrl.rdPerTurnAround::1408-1535 1 25.00% 50.00% |
| system.mem_ctrl.rdPerTurnAround::1792-1919 1 25.00% 75.00% |
| system.mem_ctrl.rdPerTurnAround::2048-2175 1 25.00% 100.00% |
| system.mem_ctrl.rdPerTurnAround::total 4 |
| system.mem_ctrl.wrPerTurnAround::samples 4 |
| system.mem_ctrl.wrPerTurnAround::mean 16 |
| system.mem_ctrl.wrPerTurnAround::gmean 16.000000 |
| system.mem_ctrl.wrPerTurnAround::16 4 100.00% 100.00% |
| system.mem_ctrl.wrPerTurnAround::total 4 |
| system.mem_ctrl.totQLat 57609500 |
| system.mem_ctrl.totMemAccLat 169903250 |
| system.mem_ctrl.totBusLat 29945000 |
| system.mem_ctrl.avgQLat 9619.22 |
| system.mem_ctrl.avgBusLat 5000.00 |
| system.mem_ctrl.avgMemAccLat 28369.22 |
| system.mem_ctrl.avgRdBW 1029.58 |
| system.mem_ctrl.avgWrBW 11.00 |
| system.mem_ctrl.avgRdBWSys 66.57 |
| system.mem_ctrl.avgWrBWSys 9.93 |
| system.mem_ctrl.peakBW 12800.00 |
| system.mem_ctrl.busUtil 8.13 |
| system.mem_ctrl.busUtilRead 8.04 |
| system.mem_ctrl.busUtilWrite 0.09 |
| system.mem_ctrl.avgRdQLen 1.00 |
| system.mem_ctrl.avgWrQLen 24.94 |
| system.mem_ctrl.readRowHits 5473 |
| system.mem_ctrl.writeRowHits 62 |
| system.mem_ctrl.readRowHitRate 91.38 |
| system.mem_ctrl.writeRowHitRate 76.54 |
| system.mem_ctrl.avgGap 52983.20 |
| system.mem_ctrl.pageHitRate 91.19 |
| system.mem_ctrl_0.actEnergy 2727480 |
| system.mem_ctrl_0.preEnergy 1438305 |
| system.mem_ctrl_0.readEnergy 35364420 |
| system.mem_ctrl_0.writeEnergy 0 |
| system.mem_ctrl_0.refreshEnergy 28888080.000000 |
| system.mem_ctrl_0.actBackEnergy 64999380 |
| system.mem_ctrl_0.preBackEnergy 1619520 |
| system.mem_ctrl_0.actPowerDownEnergy 98643060 |
| system.mem_ctrl_0.prePowerDownEnergy 3533760 |
| system.mem_ctrl_0.selfRefreshEnergy 0 |
| system.mem_ctrl_0.totalEnergy 237214005 |
| system.mem_ctrl_0.averagePower 637.183891 |
| system.mem_ctrl_0.totalIdleTime 225396250 |
| system.mem_ctrl_0.memoryStateTime::IDLE 954000 |
| system.mem_ctrl_0.memoryStateTime::REF 12220000 |
| system.mem_ctrl_0.memoryStateTime::SREF 0 |
| system.mem_ctrl_0.memoryStateTime::PRE_PDN 9196500 |
| system.mem_ctrl_0.memoryStateTime::ACT 133713750 |
| system.mem_ctrl_0.memoryStateTime::ACT_PDN 216199750 |
| system.mem_ctrl_1.actEnergy 971040 |
| system.mem_ctrl_1.preEnergy 512325 |
| system.mem_ctrl_1.readEnergy 7389900 |
| system.mem_ctrl_1.writeEnergy 334080 |
| system.mem_ctrl_1.refreshEnergy 27658800.000000 |
| system.mem_ctrl_1.actBackEnergy 18607080 |
| system.mem_ctrl_1.preBackEnergy 791520 |
| system.mem_ctrl_1.actPowerDownEnergy 128152530 |
| system.mem_ctrl_1.prePowerDownEnergy 7837920 |
| system.mem_ctrl_1.selfRefreshEnergy 7265340 |
| system.mem_ctrl_1.totalEnergy 199520535 |
| system.mem_ctrl_1.averagePower 535.934929 |
| system.mem_ctrl_1.totalIdleTime 328663750 |
| system.mem_ctrl_1.memoryStateTime::IDLE 770000 |
| system.mem_ctrl_1.memoryStateTime::REF 11706000 |
| system.mem_ctrl_1.memoryStateTime::SREF 27971000 |
| system.mem_ctrl_1.memoryStateTime::PRE_PDN 20415250 |
| system.mem_ctrl_1.memoryStateTime::ACT 30385000 |
| system.mem_ctrl_1.memoryStateTime::ACT_PDN 281036750 |
| system.pwrStateResidencyTicks::UNDEFINED 372284000 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 |
| system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 |
| system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.accesses 0 |
| system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 |
| system.cpu.dtb.walker.walks 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.dtb.walker.walkRequestOrigin::total 0 |
| system.cpu.dtb.inst_hits 0 |
| system.cpu.dtb.inst_misses 0 |
| system.cpu.dtb.read_hits 0 |
| system.cpu.dtb.read_misses 0 |
| system.cpu.dtb.write_hits 0 |
| system.cpu.dtb.write_misses 0 |
| system.cpu.dtb.flush_tlb 0 |
| system.cpu.dtb.flush_tlb_mva 0 |
| system.cpu.dtb.flush_tlb_mva_asid 0 |
| system.cpu.dtb.flush_tlb_asid 0 |
| system.cpu.dtb.flush_entries 0 |
| system.cpu.dtb.align_faults 0 |
| system.cpu.dtb.prefetch_faults 0 |
| system.cpu.dtb.domain_faults 0 |
| system.cpu.dtb.perms_faults 0 |
| system.cpu.dtb.read_accesses 0 |
| system.cpu.dtb.write_accesses 0 |
| system.cpu.dtb.inst_accesses 0 |
| system.cpu.dtb.hits 0 |
| system.cpu.dtb.misses 0 |
| system.cpu.dtb.accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 |
| system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.read_hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.read_misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.write_hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.write_misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 |
| system.cpu.istage2_mmu.stage2_tlb.align_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.accesses 0 |
| system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 372284000 |
| system.cpu.itb.walker.walks 0 |
| system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.itb.walker.walkRequestOrigin::total 0 |
| system.cpu.itb.inst_hits 0 |
| system.cpu.itb.inst_misses 0 |
| system.cpu.itb.read_hits 0 |
| system.cpu.itb.read_misses 0 |
| system.cpu.itb.write_hits 0 |
| system.cpu.itb.write_misses 0 |
| system.cpu.itb.flush_tlb 0 |
| system.cpu.itb.flush_tlb_mva 0 |
| system.cpu.itb.flush_tlb_mva_asid 0 |
| system.cpu.itb.flush_tlb_asid 0 |
| system.cpu.itb.flush_entries 0 |
| system.cpu.itb.align_faults 0 |
| system.cpu.itb.prefetch_faults 0 |
| system.cpu.itb.domain_faults 0 |
| system.cpu.itb.perms_faults 0 |
| system.cpu.itb.read_accesses 0 |
| system.cpu.itb.write_accesses 0 |
| system.cpu.itb.inst_accesses 0 |
| system.cpu.itb.hits 0 |
| system.cpu.itb.misses 0 |
| system.cpu.itb.accesses 0 |
| system.cpu.workload.numSyscalls 13 |
| system.cpu.pwrStateResidencyTicks::ON 372284000 |
| system.cpu.numCycles 372284 |
| system.cpu.numWorkItemsStarted 0 |
| system.cpu.numWorkItemsCompleted 0 |
| system.cpu.committedInsts 4988 |
| system.cpu.committedOps 5770 |
| system.cpu.num_int_alu_accesses 4977 |
| system.cpu.num_fp_alu_accesses 16 |
| system.cpu.num_func_calls 215 |
| system.cpu.num_conditional_control_insts 800 |
| system.cpu.num_int_insts 4977 |
| system.cpu.num_fp_insts 16 |
| system.cpu.num_int_register_reads 8049 |
| system.cpu.num_int_register_writes 2992 |
| system.cpu.num_fp_register_reads 16 |
| system.cpu.num_fp_register_writes 0 |
| system.cpu.num_cc_register_reads 20681 |
| system.cpu.num_cc_register_writes 2647 |
| system.cpu.num_mem_refs 2035 |
| system.cpu.num_load_insts 1085 |
| system.cpu.num_store_insts 950 |
| system.cpu.num_idle_cycles 0 |
| system.cpu.num_busy_cycles 372284 |
| system.cpu.not_idle_fraction 1 |
| system.cpu.idle_fraction 0 |
| system.cpu.Branches 1107 |
| system.cpu.op_class::No_OpClass 0 0.00% 0.00% |
| system.cpu.op_class::IntAlu 3789 64.98% 64.98% |
| system.cpu.op_class::IntMult 4 0.07% 65.05% |
| system.cpu.op_class::IntDiv 0 0.00% 65.05% |
| system.cpu.op_class::FloatAdd 0 0.00% 65.05% |
| system.cpu.op_class::FloatCmp 0 0.00% 65.05% |
| system.cpu.op_class::FloatCvt 0 0.00% 65.05% |
| system.cpu.op_class::FloatMult 0 0.00% 65.05% |
| system.cpu.op_class::FloatMultAcc 0 0.00% 65.05% |
| system.cpu.op_class::FloatDiv 0 0.00% 65.05% |
| system.cpu.op_class::FloatMisc 0 0.00% 65.05% |
| system.cpu.op_class::FloatSqrt 0 0.00% 65.05% |
| system.cpu.op_class::SimdAdd 0 0.00% 65.05% |
| system.cpu.op_class::SimdAddAcc 0 0.00% 65.05% |
| system.cpu.op_class::SimdAlu 0 0.00% 65.05% |
| system.cpu.op_class::SimdCmp 0 0.00% 65.05% |
| system.cpu.op_class::SimdCvt 0 0.00% 65.05% |
| system.cpu.op_class::SimdMisc 0 0.00% 65.05% |
| system.cpu.op_class::SimdMult 0 0.00% 65.05% |
| system.cpu.op_class::SimdMultAcc 0 0.00% 65.05% |
| system.cpu.op_class::SimdShift 0 0.00% 65.05% |
| system.cpu.op_class::SimdShiftAcc 0 0.00% 65.05% |
| system.cpu.op_class::SimdSqrt 0 0.00% 65.05% |
| system.cpu.op_class::SimdFloatAdd 0 0.00% 65.05% |
| system.cpu.op_class::SimdFloatAlu 0 0.00% 65.05% |
| system.cpu.op_class::SimdFloatCmp 0 0.00% 65.05% |
| system.cpu.op_class::SimdFloatCvt 0 0.00% 65.05% |
| system.cpu.op_class::SimdFloatDiv 0 0.00% 65.05% |
| system.cpu.op_class::SimdFloatMisc 3 0.05% 65.10% |
| system.cpu.op_class::SimdFloatMult 0 0.00% 65.10% |
| system.cpu.op_class::SimdFloatMultAcc 0 0.00% 65.10% |
| system.cpu.op_class::SimdFloatSqrt 0 0.00% 65.10% |
| system.cpu.op_class::MemRead 1085 18.61% 83.71% |
| system.cpu.op_class::MemWrite 934 16.02% 99.73% |
| system.cpu.op_class::FloatMemRead 0 0.00% 99.73% |
| system.cpu.op_class::FloatMemWrite 16 0.27% 100.00% |
| system.cpu.op_class::IprAccess 0 0.00% 100.00% |
| system.cpu.op_class::InstPrefetch 0 0.00% 100.00% |
| system.cpu.op_class::total 5831 |
| system.membus.snoop_filter.tot_requests 0 |
| system.membus.snoop_filter.hit_single_requests 0 |
| system.membus.snoop_filter.hit_multi_requests 0 |
| system.membus.snoop_filter.tot_snoops 0 |
| system.membus.snoop_filter.hit_single_snoops 0 |
| system.membus.snoop_filter.hit_multi_snoops 0 |
| system.membus.pwrStateResidencyTicks::UNDEFINED 372284000 |
| system.membus.trans_dist::ReadReq 6078 |
| system.membus.trans_dist::ReadResp 6088 |
| system.membus.trans_dist::WriteReq 925 |
| system.membus.trans_dist::WriteResp 925 |
| system.membus.trans_dist::LoadLockedReq 11 |
| system.membus.trans_dist::StoreCondReq 11 |
| system.membus.trans_dist::StoreCondResp 11 |
| system.membus.pkt_count_system.cpu.icache_port::system.mem_ctrl.port 10055 |
| system.membus.pkt_count_system.cpu.dcache_port::system.mem_ctrl.port 3994 |
| system.membus.pkt_count::total 14049 |
| system.membus.pkt_size_system.cpu.icache_port::system.mem_ctrl.port 20108 |
| system.membus.pkt_size_system.cpu.dcache_port::system.mem_ctrl.port 8368 |
| system.membus.pkt_size::total 28476 |
| system.membus.snoops 0 |
| system.membus.snoopTraffic 0 |
| system.membus.snoop_fanout::samples 7025 |
| system.membus.snoop_fanout::mean 0 |
| system.membus.snoop_fanout::stdev 0 |
| system.membus.snoop_fanout::underflows 0 0.00% 0.00% |
| system.membus.snoop_fanout::0 7025 100.00% 100.00% |
| system.membus.snoop_fanout::1 0 0.00% 100.00% |
| system.membus.snoop_fanout::overflows 0 0.00% 100.00% |
| system.membus.snoop_fanout::min_value 0 |
| system.membus.snoop_fanout::max_value 0 |
| system.membus.snoop_fanout::total 7025 |
| system.membus.reqLayer0.occupancy 7961000 |
| system.membus.reqLayer0.utilization 2.1 |
| system.membus.respLayer0.occupancy 11413250 |
| system.membus.respLayer0.utilization 3.1 |
| system.membus.respLayer1.occupancy 3327250 |
| system.membus.respLayer1.utilization 0.9 |
| |
| ---------- End Simulation Statistics ---------- |
