| [root] |
| type=Root |
| children=system |
| eventq_index=0 |
| full_system=false |
| sim_quantum=0 |
| time_sync_enable=false |
| time_sync_period=100000000000 |
| time_sync_spin_threshold=100000000 |
| |
| [system] |
| type=System |
| children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain |
| boot_osflags=a |
| cache_line_size=64 |
| clk_domain=system.clk_domain |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| exit_on_work_items=false |
| init_param=0 |
| kernel= |
| kernel_addr_check=true |
| load_addr_mask=1099511627775 |
| load_offset=0 |
| mem_mode=timing |
| mem_ranges= |
| memories=system.physmem |
| mmap_using_noreserve=false |
| multi_thread=false |
| num_work_ids=16 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| readfile= |
| symbolfile= |
| thermal_components= |
| thermal_model=Null |
| work_begin_ckpt_count=0 |
| work_begin_cpu_id_exit=-1 |
| work_begin_exit_count=0 |
| work_cpus_ckpt_count=0 |
| work_end_ckpt_count=0 |
| work_end_exit_count=0 |
| work_item_id=-1 |
| system_port=system.membus.slave[0] |
| |
| [system.clk_domain] |
| type=SrcClockDomain |
| clock=1000 |
| domain_id=-1 |
| eventq_index=0 |
| init_perf_level=0 |
| voltage_domain=system.voltage_domain |
| |
| [system.cpu] |
| type=DerivO3CPU |
| children=branchPred dcache dstage2_mmu dtb fuPool icache interrupts isa istage2_mmu itb l2cache toL2Bus tracer workload |
| LFSTSize=1024 |
| LQEntries=16 |
| LSQCheckLoads=true |
| LSQDepCheckShift=0 |
| SQEntries=16 |
| SSITSize=1024 |
| activity=0 |
| backComSize=5 |
| branchPred=system.cpu.branchPred |
| cacheStorePorts=200 |
| checker=Null |
| clk_domain=system.cpu_clk_domain |
| commitToDecodeDelay=1 |
| commitToFetchDelay=1 |
| commitToIEWDelay=1 |
| commitToRenameDelay=1 |
| commitWidth=8 |
| cpu_id=0 |
| decodeToFetchDelay=1 |
| decodeToRenameDelay=2 |
| decodeWidth=3 |
| default_p_state=UNDEFINED |
| dispatchWidth=6 |
| do_checkpoint_insts=true |
| do_quiesce=true |
| do_statistics_insts=true |
| dstage2_mmu=system.cpu.dstage2_mmu |
| dtb=system.cpu.dtb |
| eventq_index=0 |
| fetchBufferSize=16 |
| fetchQueueSize=32 |
| fetchToDecodeDelay=3 |
| fetchTrapLatency=1 |
| fetchWidth=3 |
| forwardComSize=5 |
| fuPool=system.cpu.fuPool |
| function_trace=false |
| function_trace_start=0 |
| iewToCommitDelay=1 |
| iewToDecodeDelay=1 |
| iewToFetchDelay=1 |
| iewToRenameDelay=1 |
| interrupts=system.cpu.interrupts |
| isa=system.cpu.isa |
| issueToExecuteDelay=1 |
| issueWidth=8 |
| istage2_mmu=system.cpu.istage2_mmu |
| itb=system.cpu.itb |
| max_insts_all_threads=0 |
| max_insts_any_thread=0 |
| max_loads_all_threads=0 |
| max_loads_any_thread=0 |
| needsTSO=false |
| numIQEntries=32 |
| numPhysCCRegs=640 |
| numPhysFloatRegs=192 |
| numPhysIntRegs=128 |
| numROBEntries=40 |
| numRobs=1 |
| numThreads=1 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| profile=0 |
| progress_interval=0 |
| renameToDecodeDelay=1 |
| renameToFetchDelay=1 |
| renameToIEWDelay=1 |
| renameToROBDelay=1 |
| renameWidth=3 |
| simpoint_start_insts= |
| smtCommitPolicy=RoundRobin |
| smtFetchPolicy=SingleThread |
| smtIQPolicy=Partitioned |
| smtIQThreshold=100 |
| smtLSQPolicy=Partitioned |
| smtLSQThreshold=100 |
| smtNumFetchingThreads=1 |
| smtROBPolicy=Partitioned |
| smtROBThreshold=100 |
| socket_id=0 |
| squashWidth=8 |
| store_set_clear_period=250000 |
| switched_out=false |
| syscallRetryLatency=10000 |
| system=system |
| tracer=system.cpu.tracer |
| trapLatency=13 |
| wbWidth=8 |
| workload=system.cpu.workload |
| dcache_port=system.cpu.dcache.cpu_side |
| icache_port=system.cpu.icache.cpu_side |
| |
| [system.cpu.branchPred] |
| type=BiModeBP |
| BTBEntries=2048 |
| BTBTagSize=18 |
| RASSize=16 |
| choiceCtrBits=2 |
| choicePredictorSize=8192 |
| eventq_index=0 |
| globalCtrBits=2 |
| globalPredictorSize=8192 |
| indirectHashGHR=true |
| indirectHashTargets=true |
| indirectPathLength=3 |
| indirectSets=256 |
| indirectTagSize=16 |
| indirectWays=2 |
| instShiftAmt=2 |
| numThreads=1 |
| useIndirect=true |
| |
| [system.cpu.dcache] |
| type=Cache |
| children=tags |
| addr_ranges=0:18446744073709551615:0:0:0:0 |
| assoc=2 |
| clk_domain=system.cpu_clk_domain |
| clusivity=mostly_incl |
| data_latency=2 |
| default_p_state=UNDEFINED |
| demand_mshr_reserve=1 |
| eventq_index=0 |
| is_read_only=false |
| max_miss_count=0 |
| mshrs=6 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| prefetch_on_access=false |
| prefetcher=Null |
| response_latency=2 |
| sequential_access=false |
| size=32768 |
| system=system |
| tag_latency=2 |
| tags=system.cpu.dcache.tags |
| tgts_per_mshr=8 |
| write_buffers=16 |
| writeback_clean=true |
| cpu_side=system.cpu.dcache_port |
| mem_side=system.cpu.toL2Bus.slave[1] |
| |
| [system.cpu.dcache.tags] |
| type=LRU |
| assoc=2 |
| block_size=64 |
| clk_domain=system.cpu_clk_domain |
| data_latency=2 |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| sequential_access=false |
| size=32768 |
| tag_latency=2 |
| |
| [system.cpu.dstage2_mmu] |
| type=ArmStage2MMU |
| children=stage2_tlb |
| eventq_index=0 |
| stage2_tlb=system.cpu.dstage2_mmu.stage2_tlb |
| sys=system |
| tlb=system.cpu.dtb |
| |
| [system.cpu.dstage2_mmu.stage2_tlb] |
| type=ArmTLB |
| children=walker |
| eventq_index=0 |
| is_stage2=true |
| size=32 |
| walker=system.cpu.dstage2_mmu.stage2_tlb.walker |
| |
| [system.cpu.dstage2_mmu.stage2_tlb.walker] |
| type=ArmTableWalker |
| clk_domain=system.cpu_clk_domain |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| is_stage2=true |
| num_squash_per_cycle=2 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| sys=system |
| |
| [system.cpu.dtb] |
| type=ArmTLB |
| children=walker |
| eventq_index=0 |
| is_stage2=false |
| size=64 |
| walker=system.cpu.dtb.walker |
| |
| [system.cpu.dtb.walker] |
| type=ArmTableWalker |
| clk_domain=system.cpu_clk_domain |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| is_stage2=false |
| num_squash_per_cycle=2 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| sys=system |
| port=system.cpu.toL2Bus.slave[3] |
| |
| [system.cpu.fuPool] |
| type=FUPool |
| children=FUList0 FUList1 FUList2 FUList3 FUList4 |
| FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 |
| eventq_index=0 |
| |
| [system.cpu.fuPool.FUList0] |
| type=FUDesc |
| children=opList |
| count=2 |
| eventq_index=0 |
| opList=system.cpu.fuPool.FUList0.opList |
| |
| [system.cpu.fuPool.FUList0.opList] |
| type=OpDesc |
| eventq_index=0 |
| opClass=IntAlu |
| opLat=1 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList1] |
| type=FUDesc |
| children=opList0 opList1 opList2 |
| count=1 |
| eventq_index=0 |
| opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 system.cpu.fuPool.FUList1.opList2 |
| |
| [system.cpu.fuPool.FUList1.opList0] |
| type=OpDesc |
| eventq_index=0 |
| opClass=IntMult |
| opLat=3 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList1.opList1] |
| type=OpDesc |
| eventq_index=0 |
| opClass=IntDiv |
| opLat=12 |
| pipelined=false |
| |
| [system.cpu.fuPool.FUList1.opList2] |
| type=OpDesc |
| eventq_index=0 |
| opClass=IprAccess |
| opLat=3 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList2] |
| type=FUDesc |
| children=opList0 opList1 |
| count=1 |
| eventq_index=0 |
| opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 |
| |
| [system.cpu.fuPool.FUList2.opList0] |
| type=OpDesc |
| eventq_index=0 |
| opClass=MemRead |
| opLat=2 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList2.opList1] |
| type=OpDesc |
| eventq_index=0 |
| opClass=FloatMemRead |
| opLat=2 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList3] |
| type=FUDesc |
| children=opList0 opList1 |
| count=1 |
| eventq_index=0 |
| opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 |
| |
| [system.cpu.fuPool.FUList3.opList0] |
| type=OpDesc |
| eventq_index=0 |
| opClass=MemWrite |
| opLat=2 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList3.opList1] |
| type=OpDesc |
| eventq_index=0 |
| opClass=FloatMemWrite |
| opLat=2 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList4] |
| type=FUDesc |
| children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 opList20 opList21 opList22 opList23 opList24 opList25 opList26 opList27 |
| count=2 |
| eventq_index=0 |
| opList=system.cpu.fuPool.FUList4.opList00 system.cpu.fuPool.FUList4.opList01 system.cpu.fuPool.FUList4.opList02 system.cpu.fuPool.FUList4.opList03 system.cpu.fuPool.FUList4.opList04 system.cpu.fuPool.FUList4.opList05 system.cpu.fuPool.FUList4.opList06 system.cpu.fuPool.FUList4.opList07 system.cpu.fuPool.FUList4.opList08 system.cpu.fuPool.FUList4.opList09 system.cpu.fuPool.FUList4.opList10 system.cpu.fuPool.FUList4.opList11 system.cpu.fuPool.FUList4.opList12 system.cpu.fuPool.FUList4.opList13 system.cpu.fuPool.FUList4.opList14 system.cpu.fuPool.FUList4.opList15 system.cpu.fuPool.FUList4.opList16 system.cpu.fuPool.FUList4.opList17 system.cpu.fuPool.FUList4.opList18 system.cpu.fuPool.FUList4.opList19 system.cpu.fuPool.FUList4.opList20 system.cpu.fuPool.FUList4.opList21 system.cpu.fuPool.FUList4.opList22 system.cpu.fuPool.FUList4.opList23 system.cpu.fuPool.FUList4.opList24 system.cpu.fuPool.FUList4.opList25 system.cpu.fuPool.FUList4.opList26 system.cpu.fuPool.FUList4.opList27 |
| |
| [system.cpu.fuPool.FUList4.opList00] |
| type=OpDesc |
| eventq_index=0 |
| opClass=SimdAdd |
| opLat=4 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList4.opList01] |
| type=OpDesc |
| eventq_index=0 |
| opClass=SimdAddAcc |
| opLat=4 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList4.opList02] |
| type=OpDesc |
| eventq_index=0 |
| opClass=SimdAlu |
| opLat=4 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList4.opList03] |
| type=OpDesc |
| eventq_index=0 |
| opClass=SimdCmp |
| opLat=4 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList4.opList04] |
| type=OpDesc |
| eventq_index=0 |
| opClass=SimdCvt |
| opLat=3 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList4.opList05] |
| type=OpDesc |
| eventq_index=0 |
| opClass=SimdMisc |
| opLat=3 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList4.opList06] |
| type=OpDesc |
| eventq_index=0 |
| opClass=SimdMult |
| opLat=5 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList4.opList07] |
| type=OpDesc |
| eventq_index=0 |
| opClass=SimdMultAcc |
| opLat=5 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList4.opList08] |
| type=OpDesc |
| eventq_index=0 |
| opClass=SimdShift |
| opLat=3 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList4.opList09] |
| type=OpDesc |
| eventq_index=0 |
| opClass=SimdShiftAcc |
| opLat=3 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList4.opList10] |
| type=OpDesc |
| eventq_index=0 |
| opClass=SimdSqrt |
| opLat=9 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList4.opList11] |
| type=OpDesc |
| eventq_index=0 |
| opClass=SimdFloatAdd |
| opLat=5 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList4.opList12] |
| type=OpDesc |
| eventq_index=0 |
| opClass=SimdFloatAlu |
| opLat=5 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList4.opList13] |
| type=OpDesc |
| eventq_index=0 |
| opClass=SimdFloatCmp |
| opLat=3 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList4.opList14] |
| type=OpDesc |
| eventq_index=0 |
| opClass=SimdFloatCvt |
| opLat=3 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList4.opList15] |
| type=OpDesc |
| eventq_index=0 |
| opClass=SimdFloatDiv |
| opLat=3 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList4.opList16] |
| type=OpDesc |
| eventq_index=0 |
| opClass=SimdFloatMisc |
| opLat=3 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList4.opList17] |
| type=OpDesc |
| eventq_index=0 |
| opClass=SimdFloatMult |
| opLat=3 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList4.opList18] |
| type=OpDesc |
| eventq_index=0 |
| opClass=SimdFloatMultAcc |
| opLat=5 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList4.opList19] |
| type=OpDesc |
| eventq_index=0 |
| opClass=SimdFloatSqrt |
| opLat=9 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList4.opList20] |
| type=OpDesc |
| eventq_index=0 |
| opClass=FloatAdd |
| opLat=5 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList4.opList21] |
| type=OpDesc |
| eventq_index=0 |
| opClass=FloatCmp |
| opLat=5 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList4.opList22] |
| type=OpDesc |
| eventq_index=0 |
| opClass=FloatCvt |
| opLat=5 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList4.opList23] |
| type=OpDesc |
| eventq_index=0 |
| opClass=FloatDiv |
| opLat=9 |
| pipelined=false |
| |
| [system.cpu.fuPool.FUList4.opList24] |
| type=OpDesc |
| eventq_index=0 |
| opClass=FloatSqrt |
| opLat=33 |
| pipelined=false |
| |
| [system.cpu.fuPool.FUList4.opList25] |
| type=OpDesc |
| eventq_index=0 |
| opClass=FloatMult |
| opLat=4 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList4.opList26] |
| type=OpDesc |
| eventq_index=0 |
| opClass=FloatMultAcc |
| opLat=5 |
| pipelined=true |
| |
| [system.cpu.fuPool.FUList4.opList27] |
| type=OpDesc |
| eventq_index=0 |
| opClass=FloatMisc |
| opLat=3 |
| pipelined=true |
| |
| [system.cpu.icache] |
| type=Cache |
| children=tags |
| addr_ranges=0:18446744073709551615:0:0:0:0 |
| assoc=2 |
| clk_domain=system.cpu_clk_domain |
| clusivity=mostly_incl |
| data_latency=1 |
| default_p_state=UNDEFINED |
| demand_mshr_reserve=1 |
| eventq_index=0 |
| is_read_only=true |
| max_miss_count=0 |
| mshrs=2 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| prefetch_on_access=false |
| prefetcher=Null |
| response_latency=1 |
| sequential_access=false |
| size=32768 |
| system=system |
| tag_latency=1 |
| tags=system.cpu.icache.tags |
| tgts_per_mshr=8 |
| write_buffers=8 |
| writeback_clean=true |
| cpu_side=system.cpu.icache_port |
| mem_side=system.cpu.toL2Bus.slave[0] |
| |
| [system.cpu.icache.tags] |
| type=LRU |
| assoc=2 |
| block_size=64 |
| clk_domain=system.cpu_clk_domain |
| data_latency=1 |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| sequential_access=false |
| size=32768 |
| tag_latency=1 |
| |
| [system.cpu.interrupts] |
| type=ArmInterrupts |
| eventq_index=0 |
| |
| [system.cpu.isa] |
| type=ArmISA |
| decoderFlavour=Generic |
| eventq_index=0 |
| fpsid=1090793632 |
| id_aa64afr0_el1=0 |
| id_aa64afr1_el1=0 |
| id_aa64dfr0_el1=1052678 |
| id_aa64dfr1_el1=0 |
| id_aa64isar0_el1=0 |
| id_aa64isar1_el1=0 |
| id_aa64mmfr0_el1=15728642 |
| id_aa64mmfr1_el1=0 |
| id_isar0=34607377 |
| id_isar1=34677009 |
| id_isar2=555950401 |
| id_isar3=17899825 |
| id_isar4=268501314 |
| id_isar5=0 |
| id_mmfr0=270536963 |
| id_mmfr1=0 |
| id_mmfr2=19070976 |
| id_mmfr3=34611729 |
| midr=1091551472 |
| pmu=Null |
| system=system |
| |
| [system.cpu.istage2_mmu] |
| type=ArmStage2MMU |
| children=stage2_tlb |
| eventq_index=0 |
| stage2_tlb=system.cpu.istage2_mmu.stage2_tlb |
| sys=system |
| tlb=system.cpu.itb |
| |
| [system.cpu.istage2_mmu.stage2_tlb] |
| type=ArmTLB |
| children=walker |
| eventq_index=0 |
| is_stage2=true |
| size=32 |
| walker=system.cpu.istage2_mmu.stage2_tlb.walker |
| |
| [system.cpu.istage2_mmu.stage2_tlb.walker] |
| type=ArmTableWalker |
| clk_domain=system.cpu_clk_domain |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| is_stage2=true |
| num_squash_per_cycle=2 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| sys=system |
| |
| [system.cpu.itb] |
| type=ArmTLB |
| children=walker |
| eventq_index=0 |
| is_stage2=false |
| size=64 |
| walker=system.cpu.itb.walker |
| |
| [system.cpu.itb.walker] |
| type=ArmTableWalker |
| clk_domain=system.cpu_clk_domain |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| is_stage2=false |
| num_squash_per_cycle=2 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| sys=system |
| port=system.cpu.toL2Bus.slave[2] |
| |
| [system.cpu.l2cache] |
| type=Cache |
| children=prefetcher tags |
| addr_ranges=0:18446744073709551615:0:0:0:0 |
| assoc=16 |
| clk_domain=system.cpu_clk_domain |
| clusivity=mostly_excl |
| data_latency=12 |
| default_p_state=UNDEFINED |
| demand_mshr_reserve=1 |
| eventq_index=0 |
| is_read_only=false |
| max_miss_count=0 |
| mshrs=16 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| prefetch_on_access=true |
| prefetcher=system.cpu.l2cache.prefetcher |
| response_latency=12 |
| sequential_access=false |
| size=1048576 |
| system=system |
| tag_latency=12 |
| tags=system.cpu.l2cache.tags |
| tgts_per_mshr=8 |
| write_buffers=8 |
| writeback_clean=false |
| cpu_side=system.cpu.toL2Bus.master[0] |
| mem_side=system.membus.slave[1] |
| |
| [system.cpu.l2cache.prefetcher] |
| type=StridePrefetcher |
| cache_snoop=false |
| clk_domain=system.cpu_clk_domain |
| default_p_state=UNDEFINED |
| degree=8 |
| eventq_index=0 |
| latency=1 |
| max_conf=7 |
| min_conf=0 |
| on_data=true |
| on_inst=true |
| on_miss=false |
| on_read=true |
| on_write=true |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| queue_filter=true |
| queue_size=32 |
| queue_squash=true |
| start_conf=4 |
| sys=system |
| table_assoc=4 |
| table_sets=16 |
| tag_prefetch=true |
| thresh_conf=4 |
| use_master_id=true |
| |
| [system.cpu.l2cache.tags] |
| type=RandomRepl |
| assoc=16 |
| block_size=64 |
| clk_domain=system.cpu_clk_domain |
| data_latency=12 |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| power_model=Null |
| sequential_access=false |
| size=1048576 |
| tag_latency=12 |
| |
| [system.cpu.toL2Bus] |
| type=CoherentXBar |
| children=snoop_filter |
| clk_domain=system.cpu_clk_domain |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| forward_latency=0 |
| frontend_latency=1 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| point_of_coherency=false |
| power_model=Null |
| response_latency=1 |
| snoop_filter=system.cpu.toL2Bus.snoop_filter |
| snoop_response_latency=1 |
| system=system |
| use_default_range=false |
| width=32 |
| master=system.cpu.l2cache.cpu_side |
| slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.itb.walker.port system.cpu.dtb.walker.port |
| |
| [system.cpu.toL2Bus.snoop_filter] |
| type=SnoopFilter |
| eventq_index=0 |
| lookup_latency=0 |
| max_capacity=8388608 |
| system=system |
| |
| [system.cpu.tracer] |
| type=ExeTracer |
| eventq_index=0 |
| |
| [system.cpu.workload] |
| type=Process |
| cmd=hello |
| cwd= |
| drivers= |
| egid=100 |
| env= |
| errout=cerr |
| euid=100 |
| eventq_index=0 |
| executable=/usr/local/google/home/gabeblack/gem5/dist/m5/regression/test-progs/hello/bin/arm/linux/hello |
| gid=100 |
| input=cin |
| kvmInSE=false |
| maxStackSize=67108864 |
| output=cout |
| pgid=100 |
| pid=100 |
| ppid=0 |
| simpoint=0 |
| system=system |
| uid=100 |
| useArchPT=false |
| |
| [system.cpu_clk_domain] |
| type=SrcClockDomain |
| clock=500 |
| domain_id=-1 |
| eventq_index=0 |
| init_perf_level=0 |
| voltage_domain=system.voltage_domain |
| |
| [system.dvfs_handler] |
| type=DVFSHandler |
| domains= |
| enable=false |
| eventq_index=0 |
| sys_clk_domain=system.clk_domain |
| transition_latency=100000000 |
| |
| [system.membus] |
| type=CoherentXBar |
| children=snoop_filter |
| clk_domain=system.clk_domain |
| default_p_state=UNDEFINED |
| eventq_index=0 |
| forward_latency=4 |
| frontend_latency=3 |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| point_of_coherency=true |
| power_model=Null |
| response_latency=2 |
| snoop_filter=system.membus.snoop_filter |
| snoop_response_latency=4 |
| system=system |
| use_default_range=false |
| width=16 |
| master=system.physmem.port |
| slave=system.system_port system.cpu.l2cache.mem_side |
| |
| [system.membus.snoop_filter] |
| type=SnoopFilter |
| eventq_index=0 |
| lookup_latency=1 |
| max_capacity=8388608 |
| system=system |
| |
| [system.physmem] |
| type=DRAMCtrl |
| IDD0=0.055000 |
| IDD02=0.000000 |
| IDD2N=0.032000 |
| IDD2N2=0.000000 |
| IDD2P0=0.000000 |
| IDD2P02=0.000000 |
| IDD2P1=0.032000 |
| IDD2P12=0.000000 |
| IDD3N=0.038000 |
| IDD3N2=0.000000 |
| IDD3P0=0.000000 |
| IDD3P02=0.000000 |
| IDD3P1=0.038000 |
| IDD3P12=0.000000 |
| IDD4R=0.157000 |
| IDD4R2=0.000000 |
| IDD4W=0.125000 |
| IDD4W2=0.000000 |
| IDD5=0.235000 |
| IDD52=0.000000 |
| IDD6=0.020000 |
| IDD62=0.000000 |
| VDD=1.500000 |
| VDD2=0.000000 |
| activation_limit=4 |
| addr_mapping=RoRaBaCoCh |
| bank_groups_per_rank=0 |
| banks_per_rank=8 |
| burst_length=8 |
| channels=1 |
| clk_domain=system.clk_domain |
| conf_table_reported=true |
| default_p_state=UNDEFINED |
| device_bus_width=8 |
| device_rowbuffer_size=1024 |
| device_size=536870912 |
| devices_per_rank=8 |
| dll=true |
| eventq_index=0 |
| in_addr_map=true |
| kvm_map=true |
| max_accesses_per_row=16 |
| mem_sched_policy=frfcfs |
| min_writes_per_switch=16 |
| null=false |
| p_state_clk_gate_bins=20 |
| p_state_clk_gate_max=1000000000000 |
| p_state_clk_gate_min=1000 |
| page_policy=open_adaptive |
| power_model=Null |
| range=0:134217727:0:0:0:0 |
| ranks_per_channel=2 |
| read_buffer_size=32 |
| static_backend_latency=10000 |
| static_frontend_latency=10000 |
| tBURST=5000 |
| tCCD_L=0 |
| tCK=1250 |
| tCL=13750 |
| tCS=2500 |
| tRAS=35000 |
| tRCD=13750 |
| tREFI=7800000 |
| tRFC=260000 |
| tRP=13750 |
| tRRD=6000 |
| tRRD_L=0 |
| tRTP=7500 |
| tRTW=2500 |
| tWR=15000 |
| tWTR=7500 |
| tXAW=30000 |
| tXP=6000 |
| tXPDLL=0 |
| tXS=270000 |
| tXSDLL=0 |
| write_buffer_size=64 |
| write_high_thresh_perc=85 |
| write_low_thresh_perc=50 |
| port=system.membus.master[0] |
| |
| [system.voltage_domain] |
| type=VoltageDomain |
| eventq_index=0 |
| voltage=1.000000 |
| |
