commit 699ef82eba4ffe4ba49645968d2969b56599b617
author Nikos Nikoleris <nikos.nikoleris@arm.com> Mon Nov 21 10:12:25 2016 +0000
committer Nikos Nikoleris <nikos.nikoleris@arm.com> Tue Jun 19 08:05:30 2018 +0000
tree efb7e2e1af54c8a814467fdd54ab7cb1b4836424
parent 05c4c2b566ce351ab217b2bd7035562aa7a76570

mem-cache: Fix support for secure blocks in the FALRU cache

Fully associative caches use an unordered map to enable efficient
lookups of existing blocks. Previously this map was indexed using the
tag of the block. Security extentions allow secure and non secure
versions of a block with the same tag to co-exist in the cache. This
patch amends the block map to allow correct lookups for FALRU caches.

Change-Id: Iccf07464deab56d1d270bae14bb3b154047e3556
Reviewed-on: https://gem5-review.googlesource.com/11309
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

src/mem/cache/tags/fa_lru.cc

diff --git a/src/mem/cache/tags/fa_lru.cc b/src/mem/cache/tags/fa_lru.cc
index bcf785e..60998e2 100644
--- a/src/mem/cache/tags/fa_lru.cc
+++ b/src/mem/cache/tags/fa_lru.cc
@@ -107,16 +107,6 @@
     cacheTracking.regStats(name());
 }
 
-FALRUBlk *
-FALRU::hashLookup(Addr addr) const
-{
-    tagIterator iter = tagHash.find(addr);
-    if (iter != tagHash.end()) {
-        return (*iter).second;
-    }
-    return nullptr;
-}
-
 void
 FALRU::invalidate(CacheBlk *blk)
 {
@@ -129,7 +119,7 @@
     moveToTail((FALRUBlk*)blk);
 
     // Erase block entry in the hash table
-    tagHash.erase(blk->tag);
+    tagHash.erase(std::make_pair(blk->tag, blk->isSecure()));
 }
 
 CacheBlk*
@@ -145,7 +135,7 @@
     CachesMask mask = 0;
     FALRUBlk* blk = static_cast<FALRUBlk*>(findBlock(addr, is_secure));
 
-    if (blk != nullptr) {
+    if (blk && blk->isValid()) {
         // If a cache hit
         lat = accessLatency;
         // Check if the block to be accessed is available. If not,
@@ -175,15 +165,19 @@
 CacheBlk*
 FALRU::findBlock(Addr addr, bool is_secure) const
 {
+    FALRUBlk* blk = nullptr;
+
     Addr tag = extractTag(addr);
-    FALRUBlk* blk = hashLookup(tag);
+    auto iter = tagHash.find(std::make_pair(tag, is_secure));
+    if (iter != tagHash.end()) {
+        blk = (*iter).second;
+    }
 
     if (blk && blk->isValid()) {
         assert(blk->tag == tag);
         assert(blk->isSecure() == is_secure);
-    } else {
-        blk = nullptr;
     }
+
     return blk;
 }
 
@@ -225,7 +219,7 @@
     moveToHead(falruBlk);
 
     // Insert new block in the hash table
-    tagHash[falruBlk->tag] = falruBlk;
+    tagHash[std::make_pair(blk->tag, blk->isSecure())] = falruBlk;
 }
 
 void
@@ -406,7 +400,7 @@
     }
 
     // Record stats for the actual cache too
-    if (blk) {
+    if (blk && blk->isValid()) {
         hits[numTrackedCaches]++;
     } else {
         misses[numTrackedCaches]++;

src/mem/cache/tags/fa_lru.hh

diff --git a/src/mem/cache/tags/fa_lru.hh b/src/mem/cache/tags/fa_lru.hh
index 35413c2..876219b 100644
--- a/src/mem/cache/tags/fa_lru.hh
+++ b/src/mem/cache/tags/fa_lru.hh
@@ -111,19 +111,19 @@
     FALRUBlk *tail;
 
     /** Hash table type mapping addresses to cache block pointers. */
-    typedef std::unordered_map<Addr, FALRUBlk *, std::hash<Addr> > hash_t;
-    /** Iterator into the address hash table. */
-    typedef hash_t::const_iterator tagIterator;
+    struct PairHash
+    {
+        template <class T1, class T2>
+        std::size_t operator()(const std::pair<T1, T2> &p) const
+        {
+            return std::hash<T1>()(p.first) ^ std::hash<T2>()(p.second);
+        }
+    };
+    typedef std::pair<Addr, bool> TagHashKey;
+    typedef std::unordered_map<TagHashKey, FALRUBlk *, PairHash> TagHash;
 
     /** The address hash table. */
-    hash_t tagHash;
-
-    /**
-     * Find the cache block for the given address.
-     * @param addr The address to find.
-     * @return The cache block of the address, if any.
-     */
-    FALRUBlk * hashLookup(Addr addr) const;
+    TagHash tagHash;
 
     /**
      * Move a cache block to the MRU position.