commit 936b584ce35c079db98ab17c6ac9c6943ce7220e
author Giacomo Travaglini <giacomo.travaglini@arm.com> Wed May 09 15:59:38 2018 +0100
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Tue May 29 10:17:32 2018 +0000
tree 9812c2258e7d7fb72d827bafe077397da56cbb33
parent 494a0f3e716081ed75e0749e2955893fce6f4b4e

arch-arm: Remove unusued MISCREG_A64_UNIMPL

In case the decoder fails to find a suitable MiscReg during a MSR/MRS
in AArch64, MISCREG_UNKNOWN is used, so there is no need for an extra
MISCREG_A64_UNIMPL register.

Change-Id: I7c709fc554e554b39d765dffb7ceb90e33b7c15f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/10503
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

src/arch/arm/miscregs.cc

diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 08e37bb..31b3580 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -4007,9 +4007,6 @@
     InitReg(MISCREG_CP15_UNIMPL)
       .unimplemented()
       .warnNotFail();
-    InitReg(MISCREG_A64_UNIMPL)
-      .unimplemented()
-      .warnNotFail();
     InitReg(MISCREG_UNKNOWN);
 
     // Register mappings for some unimplemented registers:

src/arch/arm/miscregs.hh

diff --git a/src/arch/arm/miscregs.hh b/src/arch/arm/miscregs.hh
index b43b04f..b00e5ff 100644
--- a/src/arch/arm/miscregs.hh
+++ b/src/arch/arm/miscregs.hh
@@ -689,7 +689,6 @@
         MISCREG_RAZ,
         MISCREG_CP14_UNIMPL,
         MISCREG_CP15_UNIMPL,
-        MISCREG_A64_UNIMPL,
         MISCREG_UNKNOWN,
 
         // Implementation defined register: this represent
@@ -1386,7 +1385,6 @@
         "raz",
         "cp14_unimpl",
         "cp15_unimpl",
-        "a64_unimpl",
         "unknown",
         "impl_defined"
     };