commit 98cbcbb54f56475759fae747b60e47568617640f
author Austin Harris <austinharris@utexas.edu> Sat Jul 07 15:43:27 2018 -0500
committer Austin Harris <austin.dane.harris@gmail.com> Mon Jul 09 01:53:49 2018 +0000
tree aa8a1e2a566aa1d5086ead641364b2b323371086
parent 0ee4a543648a4c183a27b7d953317a99f6f30928

arch-riscv: Fix the srlw and srliw instructions.

Change-Id: I14ccb0655819887db2306fee1188e1c83a991743
Signed-off-by: Austin Harris <austinharris@utexas.edu>
Reviewed-on: https://gem5-review.googlesource.com/11669
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Alec Roelke <alec.roelke@gmail.com>

src/arch/riscv/isa/decoder.isa

diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index d8f3395..b4bf385 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -447,7 +447,7 @@
                 }});
                 0x5: decode SRTYPE {
                     0x0: srliw({{
-                        Rd = Rs1_uw >> SHAMT5;
+                        Rd_sd = (int32_t)(Rs1_uw >> SHAMT5);
                     }});
                     0x1: sraiw({{
                         Rd_sd = Rs1_sw >> SHAMT5;
@@ -759,7 +759,7 @@
                 }}, IntDivOp);
                 0x5: decode FUNCT7 {
                     0x0: srlw({{
-                        Rd_uw = Rs1_uw >> Rs2<4:0>;
+                        Rd_sd = (int32_t)(Rs1_uw >> Rs2<4:0>);
                     }});
                     0x1: divuw({{
                         if (Rs2_uw == 0) {