| warn: DRAM device capacity (8192 Mbytes) does not match the address range assigned (256 Mbytes) | |
| info: kernel located at: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vmlinux.aarch32.ll_20131205.0-gem5 | |
| warn: Sockets disabled, not accepting vnc client connections | |
| warn: Sockets disabled, not accepting terminal connections | |
| warn: Sockets disabled, not accepting gdb connections | |
| warn: ClockedObject: More than one power state change request encountered within the same simulation tick | |
| info: Using bootloader at address 0x10 | |
| info: Using kernel entry physical address at 0x80008000 | |
| info: Loading DTB file: /usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb at address 0x88000000 | |
| warn: Existing EnergyCtrl, but no enabled DVFSHandler found. | |
| info: Entering event queue @ 0. Starting simulation... | |
| warn: Not doing anything for miscreg ACTLR | |
| warn: Not doing anything for write of miscreg ACTLR | |
| warn: The clidr register always reports 0 caches. | |
| warn: clidr LoUIS field of 0b001 to match current ARM implementations. | |
| warn: The csselr register isn't implemented. | |
| warn: instruction 'mcr dccmvau' unimplemented | |
| warn: instruction 'mcr icimvau' unimplemented | |
| warn: instruction 'mcr bpiallis' unimplemented | |
| warn: instruction 'mcr icialluis' unimplemented | |
| warn: instruction 'mcr dccimvac' unimplemented | |
| warn: Tried to read RealView I/O at offset 0x60 that doesn't exist | |
| warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist | |
| warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist | |
| warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist | |
| warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist | |
| warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist | |
| warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist | |
| warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist | |
| warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist | |
| warn: Tried to write RVIO at offset 0xa8 (data 0) that doesn't exist | |
| info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 | |
| info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 | |
| info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 | |
| info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 | |
| info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 | |
| info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 | |
| info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 | |
| info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 | |
| info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 | |
| info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 | |
| info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 | |
| info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 | |
| info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 | |
| info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 | |
| info: trap check M:0 N:0 1:0 2:0 hdcr 0, hcptr 3fff, hstr 0 | |
| warn: CP14 unimplemented crn[1], opc1[0], crm[3], opc2[4] | |
| warn: CP14 unimplemented crn[1], opc1[0], crm[0], opc2[4] | |
| warn: CP14 unimplemented crn[0], opc1[0], crm[7], opc2[0] | |
| warn: Returning zero for read from miscreg pmcr | |
| warn: Ignoring write to miscreg pmcntenclr | |
| warn: Ignoring write to miscreg pmintenclr | |
| warn: Ignoring write to miscreg pmovsr | |
| warn: Ignoring write to miscreg pmcr |