src/arch/mips/isa/formats/branch.isa - amd/gem5 - Git at Google

 // -*- mode:c++ -*-

 // Copyright (c) 2007 MIPS Technologies, Inc.
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
 // modification, are permitted provided that the following conditions are
 // met: redistributions of source code must retain the above copyright
 // notice, this list of conditions and the following disclaimer;
 // redistributions in binary form must reproduce the above copyright
 // notice, this list of conditions and the following disclaimer in the
 // documentation and/or other materials provided with the distribution;
 // neither the name of the copyright holders nor the names of its
 // contributors may be used to endorse or promote products derived from
 // this software without specific prior written permission.
 //
 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 //
 // Authors: Korey Sewell

 ////////////////////////////////////////////////////////////////////
 //
 // Control transfer instructions
 //

 output header {{

 #include <iostream>
     using namespace std;

     /**
      * Base class for instructions whose disassembly is not purely a
      * function of the machine instruction (i.e., it depends on the
      * PC).  This class overrides the disassemble() method to check
      * the PC and symbol table values before re-using a cached
      * disassembly string.  This is necessary for branches and jumps,
      * where the disassembly string includes the target address (which
      * may depend on the PC and/or symbol table).
      */
     class PCDependentDisassembly : public MipsStaticInst
     {
       protected:
         /// Cached program counter from last disassembly
         mutable Addr cachedPC;

         /// Cached symbol table pointer from last disassembly
         mutable const SymbolTable *cachedSymtab;

         /// Constructor
         PCDependentDisassembly(const char *mnem, MachInst _machInst,
                                OpClass __opClass)
             : MipsStaticInst(mnem, _machInst, __opClass),
               cachedPC(0), cachedSymtab(0)
         {
         }

         const std::string &
         disassemble(Addr pc, const SymbolTable *symtab) const;
     };

     /**
      * Base class for branches (PC-relative control transfers),
      * conditional or unconditional.
      */
     class Branch : public PCDependentDisassembly
     {
       protected:
         /// target address (signed) Displacement .
         int32_t disp;

         /// Constructor.
         Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
             : PCDependentDisassembly(mnem, _machInst, __opClass),
               disp(OFFSET << 2)
         {
             //If Bit 17 is 1 then Sign Extend
             if ( (disp & 0x00020000) > 0  ) {
                 disp |= 0xFFFE0000;
             }
         }

         MipsISA::PCState branchTarget(
                 const MipsISA::PCState &branchPC) const override;

         /// Explicitly import the otherwise hidden branchTarget
         using StaticInst::branchTarget;

         std::string generateDisassembly(
                 Addr pc, const SymbolTable *symtab) const override;
     };

     /**
      * Base class for jumps (register-indirect control transfers).  In
      * the Mips ISA, these are always unconditional.
      */
     class Jump : public PCDependentDisassembly
     {
       protected:

         /// Displacement to target address (signed).
         int32_t disp;

         uint32_t target;

       public:
         /// Constructor
         Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
             : PCDependentDisassembly(mnem, _machInst, __opClass),
               disp(JMPTARG << 2)
         {
         }

         MipsISA::PCState branchTarget(ThreadContext *tc) const override;

         /// Explicitly import the otherwise hidden branchTarget
         using StaticInst::branchTarget;

         std::string generateDisassembly(
                 Addr pc, const SymbolTable *symtab) const override;
     };
 }};

 output decoder {{
     MipsISA::PCState
     Branch::branchTarget(const MipsISA::PCState &branchPC) const
     {
         MipsISA::PCState target = branchPC;
         target.advance();
         target.npc(branchPC.pc() + sizeof(MachInst) + disp);
         target.nnpc(target.npc() + sizeof(MachInst));
         return target;
     }

     MipsISA::PCState
     Jump::branchTarget(ThreadContext *tc) const
     {
         MipsISA::PCState target = tc->pcState();
         Addr pc = target.pc();
         target.advance();
         target.npc((pc & 0xF0000000) | disp);
         target.nnpc(target.npc() + sizeof(MachInst));
         return target;
     }

     const std::string &
     PCDependentDisassembly::disassemble(Addr pc,
                                         const SymbolTable *symtab) const
     {
         if (!cachedDisassembly ||
             pc != cachedPC || symtab != cachedSymtab)
         {
             if (cachedDisassembly)
                 delete cachedDisassembly;

             cachedDisassembly =
                 new std::string(generateDisassembly(pc, symtab));
             cachedPC = pc;
             cachedSymtab = symtab;
         }

         return *cachedDisassembly;
     }

     std::string
     Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
     {
         std::stringstream ss;

         ccprintf(ss, "%-10s ", mnemonic);

         // There's only one register arg (RA), but it could be
         // either a source (the condition for conditional
         // branches) or a destination (the link reg for
         // unconditional branches)
         if (_numSrcRegs == 1) {
             printReg(ss, _srcRegIdx[0]);
             ss << ", ";
         } else if(_numSrcRegs == 2) {
             printReg(ss, _srcRegIdx[0]);
             ss << ", ";
             printReg(ss, _srcRegIdx[1]);
             ss << ", ";
         }

         Addr target = pc + 4 + disp;

         std::string str;
         if (symtab && symtab->findSymbol(target, str))
             ss << str;
         else
             ccprintf(ss, "0x%x", target);

         return ss.str();
     }

     std::string
     Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const
     {
         std::stringstream ss;

         ccprintf(ss, "%-10s ", mnemonic);

         if ( strcmp(mnemonic,"jal") == 0 ) {
             Addr npc = pc + 4;
             ccprintf(ss,"0x%x",(npc & 0xF0000000) | disp);
         } else if (_numSrcRegs == 0) {
             std::string str;
             if (symtab && symtab->findSymbol(disp, str))
                 ss << str;
             else
                 ccprintf(ss, "0x%x", disp);
         } else if (_numSrcRegs == 1) {
              printReg(ss, _srcRegIdx[0]);
         } else if(_numSrcRegs == 2) {
             printReg(ss, _srcRegIdx[0]);
             ss << ", ";
             printReg(ss, _srcRegIdx[1]);
         }

         return ss.str();
     }
 }};

 def format Branch(code, *opt_flags) {{
     not_taken_code = 'NNPC = NNPC; NPC = NPC;'

     #Build Instruction Flags
     #Use Link & Likely Flags to Add Link/Condition Code
     inst_flags = ('IsDirectControl', )
     for x in opt_flags:
         if x == 'Link':
             code += 'R31 = NNPC;\n'
         elif x == 'Likely':
             not_taken_code = 'NNPC = NPC; NPC = PC;'
             inst_flags += ('IsCondDelaySlot', )
         else:
             inst_flags += (x, )

     #Take into account uncond. branch instruction
     if 'cond = 1' in code:
          inst_flags += ('IsUncondControl', )
     else:
          inst_flags += ('IsCondControl', )

     #Condition code
     code = '''
     bool cond;
     %(code)s
     if (cond) {
         NNPC = NPC + disp;
     } else {
         %(not_taken_code)s
     }
     ''' % { "code" : code, "not_taken_code" : not_taken_code }

     iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
     header_output = BasicDeclare.subst(iop)
     decoder_output = BasicConstructor.subst(iop)
     decode_block = BasicDecode.subst(iop)
     exec_output = BasicExecute.subst(iop)
 }};

 def format DspBranch(code, *opt_flags) {{
     not_taken_code = 'NNPC = NNPC; NPC = NPC;'

     #Build Instruction Flags
     #Use Link & Likely Flags to Add Link/Condition Code
     inst_flags = ('IsDirectControl', )
     for x in opt_flags:
         if x == 'Link':
             code += 'R32 = NNPC;'
         elif x == 'Likely':
             not_taken_code = 'NNPC = NPC, NPC = PC;'
             inst_flags += ('IsCondDelaySlot', )
         else:
             inst_flags += (x, )

     #Take into account uncond. branch instruction
     if 'cond = 1' in code:
          inst_flags += ('IsUncondControl', )
     else:
          inst_flags += ('IsCondControl', )

     #Condition code
     code = '''
     bool cond;
     uint32_t dspctl = DSPControl;
     %(code)s
     if (cond) {
         NNPC = NPC + disp;
     } else {
         %(not_taken_code)s
     }
     ''' % { "code" : code, "not_taken_code" : not_taken_code }

     iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
     header_output = BasicDeclare.subst(iop)
     decoder_output = BasicConstructor.subst(iop)
     decode_block = BasicDecode.subst(iop)
     exec_output = BasicExecute.subst(iop)
 }};

 def format Jump(code, *opt_flags) {{
     #Build Instruction Flags
     #Use Link Flag to Add Link Code
     inst_flags = ('IsIndirectControl', 'IsUncondControl')
     for x in opt_flags:
         if x == 'Link':
             code = '''
             R31 = NNPC;
             ''' + code
         elif x == 'ClearHazards':
             code += '/* Code Needed to Clear Execute & Inst Hazards */\n'
         else:
             inst_flags += (x, )

     iop = InstObjParams(name, Name, 'Jump', code, inst_flags)
     header_output = BasicDeclare.subst(iop)
     decoder_output = BasicConstructor.subst(iop)
     decode_block = BasicDecode.subst(iop)
     exec_output = BasicExecute.subst(iop)
 }};
	// -- mode:c++ --

	// Copyright (c) 2007 MIPS Technologies, Inc.
	// All rights reserved.
	//
	// Redistribution and use in source and binary forms, with or without
	// modification, are permitted provided that the following conditions are
	// met: redistributions of source code must retain the above copyright
	// notice, this list of conditions and the following disclaimer;
	// redistributions in binary form must reproduce the above copyright
	// notice, this list of conditions and the following disclaimer in the
	// documentation and/or other materials provided with the distribution;
	// neither the name of the copyright holders nor the names of its
	// contributors may be used to endorse or promote products derived from
	// this software without specific prior written permission.
	//
	// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
	// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
	// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
	// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
	// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
	// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
	// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
	// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
	// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
	// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
	// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
	//
	// Authors: Korey Sewell

	////////////////////////////////////////////////////////////////////
	//
	// Control transfer instructions
	//

	output header {{

	#include <iostream>
	using namespace std;

	/**
	* Base class for instructions whose disassembly is not purely a
	* function of the machine instruction (i.e., it depends on the
	* PC). This class overrides the disassemble() method to check
	* the PC and symbol table values before re-using a cached
	* disassembly string. This is necessary for branches and jumps,
	* where the disassembly string includes the target address (which
	* may depend on the PC and/or symbol table).
	*/
	class PCDependentDisassembly : public MipsStaticInst
	{
	protected:
	/// Cached program counter from last disassembly
	mutable Addr cachedPC;

	/// Cached symbol table pointer from last disassembly
	mutable const SymbolTable *cachedSymtab;

	/// Constructor
	PCDependentDisassembly(const char *mnem, MachInst _machInst,
	OpClass __opClass)
	: MipsStaticInst(mnem, _machInst, __opClass),
	cachedPC(0), cachedSymtab(0)
	{
	}

	const std::string &
	disassemble(Addr pc, const SymbolTable *symtab) const;
	};

	/**
	* Base class for branches (PC-relative control transfers),
	* conditional or unconditional.
	*/
	class Branch : public PCDependentDisassembly
	{
	protected:
	/// target address (signed) Displacement .
	int32_t disp;

	/// Constructor.
	Branch(const char *mnem, MachInst _machInst, OpClass __opClass)
	: PCDependentDisassembly(mnem, _machInst, __opClass),
	disp(OFFSET << 2)
	{
	//If Bit 17 is 1 then Sign Extend
	if ( (disp & 0x00020000) > 0 ) {
	disp \|= 0xFFFE0000;
	}
	}

	MipsISA::PCState branchTarget(
	const MipsISA::PCState &branchPC) const override;

	/// Explicitly import the otherwise hidden branchTarget
	using StaticInst::branchTarget;

	std::string generateDisassembly(
	Addr pc, const SymbolTable *symtab) const override;
	};

	/**
	* Base class for jumps (register-indirect control transfers). In
	* the Mips ISA, these are always unconditional.
	*/
	class Jump : public PCDependentDisassembly
	{
	protected:

	/// Displacement to target address (signed).
	int32_t disp;

	uint32_t target;

	public:
	/// Constructor
	Jump(const char *mnem, MachInst _machInst, OpClass __opClass)
	: PCDependentDisassembly(mnem, _machInst, __opClass),
	disp(JMPTARG << 2)
	{
	}

	MipsISA::PCState branchTarget(ThreadContext *tc) const override;

	/// Explicitly import the otherwise hidden branchTarget
	using StaticInst::branchTarget;

	std::string generateDisassembly(
	Addr pc, const SymbolTable *symtab) const override;
	};
	}};

	output decoder {{
	MipsISA::PCState
	Branch::branchTarget(const MipsISA::PCState &branchPC) const
	{
	MipsISA::PCState target = branchPC;
	target.advance();
	target.npc(branchPC.pc() + sizeof(MachInst) + disp);
	target.nnpc(target.npc() + sizeof(MachInst));
	return target;
	}

	MipsISA::PCState
	Jump::branchTarget(ThreadContext *tc) const
	{
	MipsISA::PCState target = tc->pcState();
	Addr pc = target.pc();
	target.advance();
	target.npc((pc & 0xF0000000) \| disp);
	target.nnpc(target.npc() + sizeof(MachInst));
	return target;
	}

	const std::string &
	PCDependentDisassembly::disassemble(Addr pc,
	const SymbolTable *symtab) const
	{
	if (!cachedDisassembly \|\|
	pc != cachedPC \|\| symtab != cachedSymtab)
	{
	if (cachedDisassembly)
	delete cachedDisassembly;

	cachedDisassembly =
	new std::string(generateDisassembly(pc, symtab));
	cachedPC = pc;
	cachedSymtab = symtab;
	}

	return *cachedDisassembly;
	}

	std::string
	Branch::generateDisassembly(Addr pc, const SymbolTable *symtab) const
	{
	std::stringstream ss;

	ccprintf(ss, "%-10s ", mnemonic);

	// There's only one register arg (RA), but it could be
	// either a source (the condition for conditional
	// branches) or a destination (the link reg for
	// unconditional branches)
	if (_numSrcRegs == 1) {
	printReg(ss, _srcRegIdx[0]);
	ss << ", ";
	} else if(_numSrcRegs == 2) {
	printReg(ss, _srcRegIdx[0]);
	ss << ", ";
	printReg(ss, _srcRegIdx[1]);
	ss << ", ";
	}

	Addr target = pc + 4 + disp;

	std::string str;
	if (symtab && symtab->findSymbol(target, str))
	ss << str;
	else
	ccprintf(ss, "0x%x", target);

	return ss.str();
	}

	std::string
	Jump::generateDisassembly(Addr pc, const SymbolTable *symtab) const
	{
	std::stringstream ss;

	ccprintf(ss, "%-10s ", mnemonic);

	if ( strcmp(mnemonic,"jal") == 0 ) {
	Addr npc = pc + 4;
	ccprintf(ss,"0x%x",(npc & 0xF0000000) \| disp);
	} else if (_numSrcRegs == 0) {
	std::string str;
	if (symtab && symtab->findSymbol(disp, str))
	ss << str;
	else
	ccprintf(ss, "0x%x", disp);
	} else if (_numSrcRegs == 1) {
	printReg(ss, _srcRegIdx[0]);
	} else if(_numSrcRegs == 2) {
	printReg(ss, _srcRegIdx[0]);
	ss << ", ";
	printReg(ss, _srcRegIdx[1]);
	}

	return ss.str();
	}
	}};

	def format Branch(code, *opt_flags) {{
	not_taken_code = 'NNPC = NNPC; NPC = NPC;'

	#Build Instruction Flags
	#Use Link & Likely Flags to Add Link/Condition Code
	inst_flags = ('IsDirectControl', )
	for x in opt_flags:
	if x == 'Link':
	code += 'R31 = NNPC;\n'
	elif x == 'Likely':
	not_taken_code = 'NNPC = NPC; NPC = PC;'
	inst_flags += ('IsCondDelaySlot', )
	else:
	inst_flags += (x, )

	#Take into account uncond. branch instruction
	if 'cond = 1' in code:
	inst_flags += ('IsUncondControl', )
	else:
	inst_flags += ('IsCondControl', )

	#Condition code
	code = '''
	bool cond;
	%(code)s
	if (cond) {
	NNPC = NPC + disp;
	} else {
	%(not_taken_code)s
	}
	''' % { "code" : code, "not_taken_code" : not_taken_code }

	iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
	header_output = BasicDeclare.subst(iop)
	decoder_output = BasicConstructor.subst(iop)
	decode_block = BasicDecode.subst(iop)
	exec_output = BasicExecute.subst(iop)
	}};

	def format DspBranch(code, *opt_flags) {{
	not_taken_code = 'NNPC = NNPC; NPC = NPC;'

	#Build Instruction Flags
	#Use Link & Likely Flags to Add Link/Condition Code
	inst_flags = ('IsDirectControl', )
	for x in opt_flags:
	if x == 'Link':
	code += 'R32 = NNPC;'
	elif x == 'Likely':
	not_taken_code = 'NNPC = NPC, NPC = PC;'
	inst_flags += ('IsCondDelaySlot', )
	else:
	inst_flags += (x, )

	#Take into account uncond. branch instruction
	if 'cond = 1' in code:
	inst_flags += ('IsUncondControl', )
	else:
	inst_flags += ('IsCondControl', )

	#Condition code
	code = '''
	bool cond;
	uint32_t dspctl = DSPControl;
	%(code)s
	if (cond) {
	NNPC = NPC + disp;
	} else {
	%(not_taken_code)s
	}
	''' % { "code" : code, "not_taken_code" : not_taken_code }

	iop = InstObjParams(name, Name, 'Branch', code, inst_flags)
	header_output = BasicDeclare.subst(iop)
	decoder_output = BasicConstructor.subst(iop)
	decode_block = BasicDecode.subst(iop)
	exec_output = BasicExecute.subst(iop)
	}};

	def format Jump(code, *opt_flags) {{
	#Build Instruction Flags
	#Use Link Flag to Add Link Code
	inst_flags = ('IsIndirectControl', 'IsUncondControl')
	for x in opt_flags:
	if x == 'Link':
	code = '''
	R31 = NNPC;
	''' + code
	elif x == 'ClearHazards':
	code += '/* Code Needed to Clear Execute & Inst Hazards */\n'
	else:
	inst_flags += (x, )

	iop = InstObjParams(name, Name, 'Jump', code, inst_flags)
	header_output = BasicDeclare.subst(iop)
	decoder_output = BasicConstructor.subst(iop)
	decode_block = BasicDecode.subst(iop)
	exec_output = BasicExecute.subst(iop)
	}};