commit ed427a3fcdf49a0ea0afa212c96240a04d4678d7
author Robert Kovacsics <rmk35@cl.cam.ac.uk> Fri Jul 13 14:21:53 2018 +0100
committer Kovacsics Róbert <kovirobi@gmail.com> Thu Jul 19 13:43:35 2018 +0000
tree 43ab19aadc833a98147c7ba38fa596669a47cca2
parent ff52563a214c71fcd1e21e9f00ad839612032e3b

mem-cache: Typo in comment: 'proceed' -> 'precede'

The writebacks happen before anything below, not after.

Change-Id: I7eaefbbf33aa17c496255dedd964a56118a28741
Reviewed-on: https://gem5-review.googlesource.com/11749
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

src/mem/cache/base.cc

diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index 8fd9ac2..c1ebdd6 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -348,7 +348,7 @@
         satisfied = access(pkt, blk, lat, writebacks);
 
         // copy writebacks to write buffer here to ensure they logically
-        // proceed anything happening below
+        // precede anything happening below
         doWritebacks(writebacks, forward_time);
     }
 
@@ -593,7 +593,7 @@
     }
 
     // handle writebacks resulting from the access here to ensure they
-    // logically proceed anything happening below
+    // logically precede anything happening below
     doWritebacksAtomic(writebacks);
     assert(writebacks.empty());