arm, power: Make the python TLB simobjects inherit from BaseTLB.
These were still inheriting from SimObject instead of BaseTLB, making
them incompatible with parameters which expect a BaseTLB.
Change-Id: I05115cc5515f745fdeb85e4dea8eded613647e40
Reviewed-on: https://gem5-review.googlesource.com/7348
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
diff --git a/src/arch/arm/ArmTLB.py b/src/arch/arm/ArmTLB.py
index b3f711d..4cac944 100644
--- a/src/arch/arm/ArmTLB.py
+++ b/src/arch/arm/ArmTLB.py
@@ -41,6 +41,7 @@
from m5.params import *
from m5.proxy import *
from MemObject import MemObject
+from BaseTLB import BaseTLB
# Basic stage 1 translation objects
class ArmTableWalker(MemObject):
@@ -59,7 +60,7 @@
sys = Param.System(Parent.any, "system object parameter")
-class ArmTLB(SimObject):
+class ArmTLB(BaseTLB):
type = 'ArmTLB'
cxx_class = 'ArmISA::TLB'
cxx_header = "arch/arm/tlb.hh"
diff --git a/src/arch/power/PowerTLB.py b/src/arch/power/PowerTLB.py
index ae6503a..b12c5a8 100644
--- a/src/arch/power/PowerTLB.py
+++ b/src/arch/power/PowerTLB.py
@@ -31,7 +31,9 @@
from m5.SimObject import SimObject
from m5.params import *
-class PowerTLB(SimObject):
+from BaseTLB import BaseTLB
+
+class PowerTLB(BaseTLB):
type = 'PowerTLB'
cxx_class = 'PowerISA::TLB'
cxx_header = 'arch/power/tlb.hh'
