| |
| ---------- Begin Simulation Statistics ---------- |
| sim_seconds 0.000277 |
| sim_ticks 277930500 |
| final_tick 277930500 |
| sim_freq 1000000000000 |
| host_inst_rate 4092 |
| host_op_rate 4101 |
| host_tick_rate 8659912 |
| host_mem_usage 269952 |
| host_seconds 32.09 |
| sim_insts 131348 |
| sim_ops 131648 |
| system.voltage_domain.voltage 1 |
| system.clk_domain.clock 1000 |
| system.physmem.pwrStateResidencyTicks::UNDEFINED 277930500 |
| system.physmem.bytes_read::cpu.inst 46336 |
| system.physmem.bytes_read::cpu.data 29376 |
| system.physmem.bytes_read::total 75712 |
| system.physmem.bytes_inst_read::cpu.inst 46336 |
| system.physmem.bytes_inst_read::total 46336 |
| system.physmem.num_reads::cpu.inst 724 |
| system.physmem.num_reads::cpu.data 459 |
| system.physmem.num_reads::total 1183 |
| system.physmem.bw_read::cpu.inst 166717938 |
| system.physmem.bw_read::cpu.data 105695488 |
| system.physmem.bw_read::total 272413427 |
| system.physmem.bw_inst_read::cpu.inst 166717938 |
| system.physmem.bw_inst_read::total 166717938 |
| system.physmem.bw_total::cpu.inst 166717938 |
| system.physmem.bw_total::cpu.data 105695488 |
| system.physmem.bw_total::total 272413427 |
| system.pwrStateResidencyTicks::UNDEFINED 277930500 |
| system.cpu_clk_domain.clock 500 |
| system.cpu.dtb.read_hits 0 |
| system.cpu.dtb.read_misses 0 |
| system.cpu.dtb.read_accesses 0 |
| system.cpu.dtb.write_hits 0 |
| system.cpu.dtb.write_misses 0 |
| system.cpu.dtb.write_accesses 0 |
| system.cpu.dtb.hits 0 |
| system.cpu.dtb.misses 0 |
| system.cpu.dtb.accesses 0 |
| system.cpu.itb.read_hits 0 |
| system.cpu.itb.read_misses 0 |
| system.cpu.itb.read_accesses 0 |
| system.cpu.itb.write_hits 0 |
| system.cpu.itb.write_misses 0 |
| system.cpu.itb.write_accesses 0 |
| system.cpu.itb.hits 0 |
| system.cpu.itb.misses 0 |
| system.cpu.itb.accesses 0 |
| system.cpu.workload.numSyscalls 62 |
| system.cpu.pwrStateResidencyTicks::ON 277930500 |
| system.cpu.numCycles 555861 |
| system.cpu.numWorkItemsStarted 0 |
| system.cpu.numWorkItemsCompleted 0 |
| system.cpu.committedInsts 131348 |
| system.cpu.committedOps 131648 |
| system.cpu.num_int_alu_accesses 130924 |
| system.cpu.num_fp_alu_accesses 40 |
| system.cpu.num_vec_alu_accesses 0 |
| system.cpu.num_func_calls 7702 |
| system.cpu.num_conditional_control_insts 21044 |
| system.cpu.num_int_insts 130924 |
| system.cpu.num_fp_insts 40 |
| system.cpu.num_vec_insts 0 |
| system.cpu.num_int_register_reads 163963 |
| system.cpu.num_int_register_writes 87008 |
| system.cpu.num_fp_register_reads 31 |
| system.cpu.num_fp_register_writes 16 |
| system.cpu.num_vec_register_reads 0 |
| system.cpu.num_vec_register_writes 0 |
| system.cpu.num_mem_refs 51848 |
| system.cpu.num_load_insts 31667 |
| system.cpu.num_store_insts 20181 |
| system.cpu.num_idle_cycles -0 |
| system.cpu.num_busy_cycles 555861 |
| system.cpu.not_idle_fraction 1 |
| system.cpu.idle_fraction -0 |
| system.cpu.Branches 28746 |
| system.cpu.op_class::No_OpClass 66 0.05% 0.05% |
| system.cpu.op_class::IntAlu 79621 60.45% 60.50% |
| system.cpu.op_class::IntMult 164 0.12% 60.62% |
| system.cpu.op_class::IntDiv 4 0.00% 60.62% |
| system.cpu.op_class::FloatAdd 2 0.00% 60.63% |
| system.cpu.op_class::FloatCmp 3 0.00% 60.63% |
| system.cpu.op_class::FloatCvt 2 0.00% 60.63% |
| system.cpu.op_class::FloatMult 0 0.00% 60.63% |
| system.cpu.op_class::FloatMultAcc 0 0.00% 60.63% |
| system.cpu.op_class::FloatDiv 0 0.00% 60.63% |
| system.cpu.op_class::FloatMisc 0 0.00% 60.63% |
| system.cpu.op_class::FloatSqrt 0 0.00% 60.63% |
| system.cpu.op_class::SimdAdd 0 0.00% 60.63% |
| system.cpu.op_class::SimdAddAcc 0 0.00% 60.63% |
| system.cpu.op_class::SimdAlu 0 0.00% 60.63% |
| system.cpu.op_class::SimdCmp 0 0.00% 60.63% |
| system.cpu.op_class::SimdCvt 0 0.00% 60.63% |
| system.cpu.op_class::SimdMisc 0 0.00% 60.63% |
| system.cpu.op_class::SimdMult 0 0.00% 60.63% |
| system.cpu.op_class::SimdMultAcc 0 0.00% 60.63% |
| system.cpu.op_class::SimdShift 0 0.00% 60.63% |
| system.cpu.op_class::SimdShiftAcc 0 0.00% 60.63% |
| system.cpu.op_class::SimdSqrt 0 0.00% 60.63% |
| system.cpu.op_class::SimdFloatAdd 0 0.00% 60.63% |
| system.cpu.op_class::SimdFloatAlu 0 0.00% 60.63% |
| system.cpu.op_class::SimdFloatCmp 0 0.00% 60.63% |
| system.cpu.op_class::SimdFloatCvt 0 0.00% 60.63% |
| system.cpu.op_class::SimdFloatDiv 0 0.00% 60.63% |
| system.cpu.op_class::SimdFloatMisc 0 0.00% 60.63% |
| system.cpu.op_class::SimdFloatMult 0 0.00% 60.63% |
| system.cpu.op_class::SimdFloatMultAcc 0 0.00% 60.63% |
| system.cpu.op_class::SimdFloatSqrt 0 0.00% 60.63% |
| system.cpu.op_class::MemRead 31653 24.03% 84.66% |
| system.cpu.op_class::MemWrite 20162 15.30% 99.97% |
| system.cpu.op_class::FloatMemRead 14 0.01% 99.98% |
| system.cpu.op_class::FloatMemWrite 19 0.01% 99.99% |
| system.cpu.op_class::IprAccess 0 0.00% 99.99% |
| system.cpu.op_class::InstPrefetch 0 0.00% 99.99% |
| system.cpu.op_class::total 131710 |
| system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 277930500 |
| system.cpu.dcache.tags.replacements 0 |
| system.cpu.dcache.tags.tagsinuse 345.626018 |
| system.cpu.dcache.tags.total_refs 51389 |
| system.cpu.dcache.tags.sampled_refs 459 |
| system.cpu.dcache.tags.avg_refs 111.958605 |
| system.cpu.dcache.tags.warmup_cycle 0 |
| system.cpu.dcache.tags.occ_blocks::cpu.data 345.626018 |
| system.cpu.dcache.tags.occ_percent::cpu.data 0.084381 |
| system.cpu.dcache.tags.occ_percent::total 0.084381 |
| system.cpu.dcache.tags.occ_task_id_blocks::1024 459 |
| system.cpu.dcache.tags.age_task_id_blocks_1024::0 14 |
| system.cpu.dcache.tags.age_task_id_blocks_1024::1 9 |
| system.cpu.dcache.tags.age_task_id_blocks_1024::2 436 |
| system.cpu.dcache.tags.occ_task_id_percent::1024 0.112060 |
| system.cpu.dcache.tags.tag_accesses 104155 |
| system.cpu.dcache.tags.data_accesses 104155 |
| system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 277930500 |
| system.cpu.dcache.ReadReq_hits::cpu.data 31097 |
| system.cpu.dcache.ReadReq_hits::total 31097 |
| system.cpu.dcache.WriteReq_hits::cpu.data 19625 |
| system.cpu.dcache.WriteReq_hits::total 19625 |
| system.cpu.dcache.LoadLockedReq_hits::cpu.data 333 |
| system.cpu.dcache.LoadLockedReq_hits::total 333 |
| system.cpu.dcache.StoreCondReq_hits::cpu.data 334 |
| system.cpu.dcache.StoreCondReq_hits::total 334 |
| system.cpu.dcache.demand_hits::cpu.data 50722 |
| system.cpu.dcache.demand_hits::total 50722 |
| system.cpu.dcache.overall_hits::cpu.data 50722 |
| system.cpu.dcache.overall_hits::total 50722 |
| system.cpu.dcache.ReadReq_misses::cpu.data 236 |
| system.cpu.dcache.ReadReq_misses::total 236 |
| system.cpu.dcache.WriteReq_misses::cpu.data 222 |
| system.cpu.dcache.WriteReq_misses::total 222 |
| system.cpu.dcache.LoadLockedReq_misses::cpu.data 1 |
| system.cpu.dcache.LoadLockedReq_misses::total 1 |
| system.cpu.dcache.demand_misses::cpu.data 458 |
| system.cpu.dcache.demand_misses::total 458 |
| system.cpu.dcache.overall_misses::cpu.data 458 |
| system.cpu.dcache.overall_misses::total 458 |
| system.cpu.dcache.ReadReq_miss_latency::cpu.data 14868000 |
| system.cpu.dcache.ReadReq_miss_latency::total 14868000 |
| system.cpu.dcache.WriteReq_miss_latency::cpu.data 13986000 |
| system.cpu.dcache.WriteReq_miss_latency::total 13986000 |
| system.cpu.dcache.LoadLockedReq_miss_latency::cpu.data 63000 |
| system.cpu.dcache.LoadLockedReq_miss_latency::total 63000 |
| system.cpu.dcache.demand_miss_latency::cpu.data 28854000 |
| system.cpu.dcache.demand_miss_latency::total 28854000 |
| system.cpu.dcache.overall_miss_latency::cpu.data 28854000 |
| system.cpu.dcache.overall_miss_latency::total 28854000 |
| system.cpu.dcache.ReadReq_accesses::cpu.data 31333 |
| system.cpu.dcache.ReadReq_accesses::total 31333 |
| system.cpu.dcache.WriteReq_accesses::cpu.data 19847 |
| system.cpu.dcache.WriteReq_accesses::total 19847 |
| system.cpu.dcache.LoadLockedReq_accesses::cpu.data 334 |
| system.cpu.dcache.LoadLockedReq_accesses::total 334 |
| system.cpu.dcache.StoreCondReq_accesses::cpu.data 334 |
| system.cpu.dcache.StoreCondReq_accesses::total 334 |
| system.cpu.dcache.demand_accesses::cpu.data 51180 |
| system.cpu.dcache.demand_accesses::total 51180 |
| system.cpu.dcache.overall_accesses::cpu.data 51180 |
| system.cpu.dcache.overall_accesses::total 51180 |
| system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.007531 |
| system.cpu.dcache.ReadReq_miss_rate::total 0.007531 |
| system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.011185 |
| system.cpu.dcache.WriteReq_miss_rate::total 0.011185 |
| system.cpu.dcache.LoadLockedReq_miss_rate::cpu.data 0.002994 |
| system.cpu.dcache.LoadLockedReq_miss_rate::total 0.002994 |
| system.cpu.dcache.demand_miss_rate::cpu.data 0.008948 |
| system.cpu.dcache.demand_miss_rate::total 0.008948 |
| system.cpu.dcache.overall_miss_rate::cpu.data 0.008948 |
| system.cpu.dcache.overall_miss_rate::total 0.008948 |
| system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 |
| system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 |
| system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 |
| system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 |
| system.cpu.dcache.LoadLockedReq_avg_miss_latency::cpu.data 63000 |
| system.cpu.dcache.LoadLockedReq_avg_miss_latency::total 63000 |
| system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 |
| system.cpu.dcache.demand_avg_miss_latency::total 63000 |
| system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 |
| system.cpu.dcache.overall_avg_miss_latency::total 63000 |
| system.cpu.dcache.blocked_cycles::no_mshrs 0 |
| system.cpu.dcache.blocked_cycles::no_targets 0 |
| system.cpu.dcache.blocked::no_mshrs 0 |
| system.cpu.dcache.blocked::no_targets 0 |
| system.cpu.dcache.avg_blocked_cycles::no_mshrs nan |
| system.cpu.dcache.avg_blocked_cycles::no_targets nan |
| system.cpu.dcache.ReadReq_mshr_misses::cpu.data 236 |
| system.cpu.dcache.ReadReq_mshr_misses::total 236 |
| system.cpu.dcache.WriteReq_mshr_misses::cpu.data 222 |
| system.cpu.dcache.WriteReq_mshr_misses::total 222 |
| system.cpu.dcache.LoadLockedReq_mshr_misses::cpu.data 1 |
| system.cpu.dcache.LoadLockedReq_mshr_misses::total 1 |
| system.cpu.dcache.demand_mshr_misses::cpu.data 458 |
| system.cpu.dcache.demand_mshr_misses::total 458 |
| system.cpu.dcache.overall_mshr_misses::cpu.data 458 |
| system.cpu.dcache.overall_mshr_misses::total 458 |
| system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 14632000 |
| system.cpu.dcache.ReadReq_mshr_miss_latency::total 14632000 |
| system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13764000 |
| system.cpu.dcache.WriteReq_mshr_miss_latency::total 13764000 |
| system.cpu.dcache.LoadLockedReq_mshr_miss_latency::cpu.data 62000 |
| system.cpu.dcache.LoadLockedReq_mshr_miss_latency::total 62000 |
| system.cpu.dcache.demand_mshr_miss_latency::cpu.data 28396000 |
| system.cpu.dcache.demand_mshr_miss_latency::total 28396000 |
| system.cpu.dcache.overall_mshr_miss_latency::cpu.data 28396000 |
| system.cpu.dcache.overall_mshr_miss_latency::total 28396000 |
| system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.007531 |
| system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.007531 |
| system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011185 |
| system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011185 |
| system.cpu.dcache.LoadLockedReq_mshr_miss_rate::cpu.data 0.002994 |
| system.cpu.dcache.LoadLockedReq_mshr_miss_rate::total 0.002994 |
| system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.008948 |
| system.cpu.dcache.demand_mshr_miss_rate::total 0.008948 |
| system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.008948 |
| system.cpu.dcache.overall_mshr_miss_rate::total 0.008948 |
| system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 |
| system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 |
| system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 |
| system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 |
| system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu.data 62000 |
| system.cpu.dcache.LoadLockedReq_avg_mshr_miss_latency::total 62000 |
| system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 |
| system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 |
| system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 |
| system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 |
| system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 277930500 |
| system.cpu.icache.tags.replacements 39 |
| system.cpu.icache.tags.tagsinuse 443.060352 |
| system.cpu.icache.tags.total_refs 151986 |
| system.cpu.icache.tags.sampled_refs 726 |
| system.cpu.icache.tags.avg_refs 209.347107 |
| system.cpu.icache.tags.warmup_cycle 0 |
| system.cpu.icache.tags.occ_blocks::cpu.inst 443.060352 |
| system.cpu.icache.tags.occ_percent::cpu.inst 0.216338 |
| system.cpu.icache.tags.occ_percent::total 0.216338 |
| system.cpu.icache.tags.occ_task_id_blocks::1024 687 |
| system.cpu.icache.tags.age_task_id_blocks_1024::0 40 |
| system.cpu.icache.tags.age_task_id_blocks_1024::1 75 |
| system.cpu.icache.tags.age_task_id_blocks_1024::2 572 |
| system.cpu.icache.tags.occ_task_id_percent::1024 0.335449 |
| system.cpu.icache.tags.tag_accesses 306150 |
| system.cpu.icache.tags.data_accesses 306150 |
| system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 277930500 |
| system.cpu.icache.ReadReq_hits::cpu.inst 151986 |
| system.cpu.icache.ReadReq_hits::total 151986 |
| system.cpu.icache.demand_hits::cpu.inst 151986 |
| system.cpu.icache.demand_hits::total 151986 |
| system.cpu.icache.overall_hits::cpu.inst 151986 |
| system.cpu.icache.overall_hits::total 151986 |
| system.cpu.icache.ReadReq_misses::cpu.inst 726 |
| system.cpu.icache.ReadReq_misses::total 726 |
| system.cpu.icache.demand_misses::cpu.inst 726 |
| system.cpu.icache.demand_misses::total 726 |
| system.cpu.icache.overall_misses::cpu.inst 726 |
| system.cpu.icache.overall_misses::total 726 |
| system.cpu.icache.ReadReq_miss_latency::cpu.inst 45639500 |
| system.cpu.icache.ReadReq_miss_latency::total 45639500 |
| system.cpu.icache.demand_miss_latency::cpu.inst 45639500 |
| system.cpu.icache.demand_miss_latency::total 45639500 |
| system.cpu.icache.overall_miss_latency::cpu.inst 45639500 |
| system.cpu.icache.overall_miss_latency::total 45639500 |
| system.cpu.icache.ReadReq_accesses::cpu.inst 152712 |
| system.cpu.icache.ReadReq_accesses::total 152712 |
| system.cpu.icache.demand_accesses::cpu.inst 152712 |
| system.cpu.icache.demand_accesses::total 152712 |
| system.cpu.icache.overall_accesses::cpu.inst 152712 |
| system.cpu.icache.overall_accesses::total 152712 |
| system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.004754 |
| system.cpu.icache.ReadReq_miss_rate::total 0.004754 |
| system.cpu.icache.demand_miss_rate::cpu.inst 0.004754 |
| system.cpu.icache.demand_miss_rate::total 0.004754 |
| system.cpu.icache.overall_miss_rate::cpu.inst 0.004754 |
| system.cpu.icache.overall_miss_rate::total 0.004754 |
| system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62864.325068 |
| system.cpu.icache.ReadReq_avg_miss_latency::total 62864.325068 |
| system.cpu.icache.demand_avg_miss_latency::cpu.inst 62864.325068 |
| system.cpu.icache.demand_avg_miss_latency::total 62864.325068 |
| system.cpu.icache.overall_avg_miss_latency::cpu.inst 62864.325068 |
| system.cpu.icache.overall_avg_miss_latency::total 62864.325068 |
| system.cpu.icache.blocked_cycles::no_mshrs 0 |
| system.cpu.icache.blocked_cycles::no_targets 0 |
| system.cpu.icache.blocked::no_mshrs 0 |
| system.cpu.icache.blocked::no_targets 0 |
| system.cpu.icache.avg_blocked_cycles::no_mshrs nan |
| system.cpu.icache.avg_blocked_cycles::no_targets nan |
| system.cpu.icache.writebacks::writebacks 39 |
| system.cpu.icache.writebacks::total 39 |
| system.cpu.icache.ReadReq_mshr_misses::cpu.inst 726 |
| system.cpu.icache.ReadReq_mshr_misses::total 726 |
| system.cpu.icache.demand_mshr_misses::cpu.inst 726 |
| system.cpu.icache.demand_mshr_misses::total 726 |
| system.cpu.icache.overall_mshr_misses::cpu.inst 726 |
| system.cpu.icache.overall_mshr_misses::total 726 |
| system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 44913500 |
| system.cpu.icache.ReadReq_mshr_miss_latency::total 44913500 |
| system.cpu.icache.demand_mshr_miss_latency::cpu.inst 44913500 |
| system.cpu.icache.demand_mshr_miss_latency::total 44913500 |
| system.cpu.icache.overall_mshr_miss_latency::cpu.inst 44913500 |
| system.cpu.icache.overall_mshr_miss_latency::total 44913500 |
| system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.004754 |
| system.cpu.icache.ReadReq_mshr_miss_rate::total 0.004754 |
| system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.004754 |
| system.cpu.icache.demand_mshr_miss_rate::total 0.004754 |
| system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.004754 |
| system.cpu.icache.overall_mshr_miss_rate::total 0.004754 |
| system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61864.325068 |
| system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61864.325068 |
| system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61864.325068 |
| system.cpu.icache.demand_avg_mshr_miss_latency::total 61864.325068 |
| system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61864.325068 |
| system.cpu.icache.overall_avg_mshr_miss_latency::total 61864.325068 |
| system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 277930500 |
| system.cpu.l2cache.tags.replacements 0 |
| system.cpu.l2cache.tags.tagsinuse 807.449638 |
| system.cpu.l2cache.tags.total_refs 41 |
| system.cpu.l2cache.tags.sampled_refs 1183 |
| system.cpu.l2cache.tags.avg_refs 0.034657 |
| system.cpu.l2cache.tags.warmup_cycle 0 |
| system.cpu.l2cache.tags.occ_blocks::cpu.inst 461.806279 |
| system.cpu.l2cache.tags.occ_blocks::cpu.data 345.643359 |
| system.cpu.l2cache.tags.occ_percent::cpu.inst 0.014093 |
| system.cpu.l2cache.tags.occ_percent::cpu.data 0.010548 |
| system.cpu.l2cache.tags.occ_percent::total 0.024641 |
| system.cpu.l2cache.tags.occ_task_id_blocks::1024 1183 |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::0 54 |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::1 84 |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::2 1045 |
| system.cpu.l2cache.tags.occ_task_id_percent::1024 0.036102 |
| system.cpu.l2cache.tags.tag_accesses 10975 |
| system.cpu.l2cache.tags.data_accesses 10975 |
| system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 277930500 |
| system.cpu.l2cache.WritebackClean_hits::writebacks 39 |
| system.cpu.l2cache.WritebackClean_hits::total 39 |
| system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 |
| system.cpu.l2cache.ReadCleanReq_hits::total 2 |
| system.cpu.l2cache.demand_hits::cpu.inst 2 |
| system.cpu.l2cache.demand_hits::total 2 |
| system.cpu.l2cache.overall_hits::cpu.inst 2 |
| system.cpu.l2cache.overall_hits::total 2 |
| system.cpu.l2cache.ReadExReq_misses::cpu.data 222 |
| system.cpu.l2cache.ReadExReq_misses::total 222 |
| system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 724 |
| system.cpu.l2cache.ReadCleanReq_misses::total 724 |
| system.cpu.l2cache.ReadSharedReq_misses::cpu.data 237 |
| system.cpu.l2cache.ReadSharedReq_misses::total 237 |
| system.cpu.l2cache.demand_misses::cpu.inst 724 |
| system.cpu.l2cache.demand_misses::cpu.data 459 |
| system.cpu.l2cache.demand_misses::total 1183 |
| system.cpu.l2cache.overall_misses::cpu.inst 724 |
| system.cpu.l2cache.overall_misses::cpu.data 459 |
| system.cpu.l2cache.overall_misses::total 1183 |
| system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 13431000 |
| system.cpu.l2cache.ReadExReq_miss_latency::total 13431000 |
| system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 43803000 |
| system.cpu.l2cache.ReadCleanReq_miss_latency::total 43803000 |
| system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 14338500 |
| system.cpu.l2cache.ReadSharedReq_miss_latency::total 14338500 |
| system.cpu.l2cache.demand_miss_latency::cpu.inst 43803000 |
| system.cpu.l2cache.demand_miss_latency::cpu.data 27769500 |
| system.cpu.l2cache.demand_miss_latency::total 71572500 |
| system.cpu.l2cache.overall_miss_latency::cpu.inst 43803000 |
| system.cpu.l2cache.overall_miss_latency::cpu.data 27769500 |
| system.cpu.l2cache.overall_miss_latency::total 71572500 |
| system.cpu.l2cache.WritebackClean_accesses::writebacks 39 |
| system.cpu.l2cache.WritebackClean_accesses::total 39 |
| system.cpu.l2cache.ReadExReq_accesses::cpu.data 222 |
| system.cpu.l2cache.ReadExReq_accesses::total 222 |
| system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 726 |
| system.cpu.l2cache.ReadCleanReq_accesses::total 726 |
| system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 237 |
| system.cpu.l2cache.ReadSharedReq_accesses::total 237 |
| system.cpu.l2cache.demand_accesses::cpu.inst 726 |
| system.cpu.l2cache.demand_accesses::cpu.data 459 |
| system.cpu.l2cache.demand_accesses::total 1185 |
| system.cpu.l2cache.overall_accesses::cpu.inst 726 |
| system.cpu.l2cache.overall_accesses::cpu.data 459 |
| system.cpu.l2cache.overall_accesses::total 1185 |
| system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 |
| system.cpu.l2cache.ReadExReq_miss_rate::total 1 |
| system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.997245 |
| system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.997245 |
| system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 |
| system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 |
| system.cpu.l2cache.demand_miss_rate::cpu.inst 0.997245 |
| system.cpu.l2cache.demand_miss_rate::cpu.data 1 |
| system.cpu.l2cache.demand_miss_rate::total 0.998312 |
| system.cpu.l2cache.overall_miss_rate::cpu.inst 0.997245 |
| system.cpu.l2cache.overall_miss_rate::cpu.data 1 |
| system.cpu.l2cache.overall_miss_rate::total 0.998312 |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 |
| system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.381215 |
| system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.381215 |
| system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 |
| system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.381215 |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 |
| system.cpu.l2cache.demand_avg_miss_latency::total 60500.845308 |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.381215 |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 |
| system.cpu.l2cache.overall_avg_miss_latency::total 60500.845308 |
| system.cpu.l2cache.blocked_cycles::no_mshrs 0 |
| system.cpu.l2cache.blocked_cycles::no_targets 0 |
| system.cpu.l2cache.blocked::no_mshrs 0 |
| system.cpu.l2cache.blocked::no_targets 0 |
| system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan |
| system.cpu.l2cache.avg_blocked_cycles::no_targets nan |
| system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 222 |
| system.cpu.l2cache.ReadExReq_mshr_misses::total 222 |
| system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 724 |
| system.cpu.l2cache.ReadCleanReq_mshr_misses::total 724 |
| system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 237 |
| system.cpu.l2cache.ReadSharedReq_mshr_misses::total 237 |
| system.cpu.l2cache.demand_mshr_misses::cpu.inst 724 |
| system.cpu.l2cache.demand_mshr_misses::cpu.data 459 |
| system.cpu.l2cache.demand_mshr_misses::total 1183 |
| system.cpu.l2cache.overall_mshr_misses::cpu.inst 724 |
| system.cpu.l2cache.overall_mshr_misses::cpu.data 459 |
| system.cpu.l2cache.overall_mshr_misses::total 1183 |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11211000 |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11211000 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 36563000 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 36563000 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 11968500 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 11968500 |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 36563000 |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 23179500 |
| system.cpu.l2cache.demand_mshr_miss_latency::total 59742500 |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 36563000 |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 23179500 |
| system.cpu.l2cache.overall_mshr_miss_latency::total 59742500 |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.997245 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.997245 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.997245 |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 |
| system.cpu.l2cache.demand_mshr_miss_rate::total 0.998312 |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.997245 |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 |
| system.cpu.l2cache.overall_mshr_miss_rate::total 0.998312 |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.381215 |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.381215 |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.381215 |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50500.845308 |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.381215 |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50500.845308 |
| system.cpu.toL2Bus.snoop_filter.tot_requests 1224 |
| system.cpu.toL2Bus.snoop_filter.hit_single_requests 39 |
| system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 |
| system.cpu.toL2Bus.snoop_filter.tot_snoops 0 |
| system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 |
| system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 |
| system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 277930500 |
| system.cpu.toL2Bus.trans_dist::ReadResp 963 |
| system.cpu.toL2Bus.trans_dist::WritebackClean 39 |
| system.cpu.toL2Bus.trans_dist::ReadExReq 222 |
| system.cpu.toL2Bus.trans_dist::ReadExResp 222 |
| system.cpu.toL2Bus.trans_dist::ReadCleanReq 726 |
| system.cpu.toL2Bus.trans_dist::ReadSharedReq 237 |
| system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1491 |
| system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 918 |
| system.cpu.toL2Bus.pkt_count::total 2409 |
| system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 48960 |
| system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 29376 |
| system.cpu.toL2Bus.pkt_size::total 78336 |
| system.cpu.toL2Bus.snoops 0 |
| system.cpu.toL2Bus.snoopTraffic 0 |
| system.cpu.toL2Bus.snoop_fanout::samples 1185 |
| system.cpu.toL2Bus.snoop_fanout::mean 0 |
| system.cpu.toL2Bus.snoop_fanout::stdev -0 |
| system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% |
| system.cpu.toL2Bus.snoop_fanout::0 1185 100.00% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::min_value 0 |
| system.cpu.toL2Bus.snoop_fanout::max_value 0 |
| system.cpu.toL2Bus.snoop_fanout::total 1185 |
| system.cpu.toL2Bus.reqLayer0.occupancy 651000 |
| system.cpu.toL2Bus.reqLayer0.utilization 0.2 |
| system.cpu.toL2Bus.respLayer0.occupancy 1089000 |
| system.cpu.toL2Bus.respLayer0.utilization 0.3 |
| system.cpu.toL2Bus.respLayer1.occupancy 688500 |
| system.cpu.toL2Bus.respLayer1.utilization 0.2 |
| system.membus.snoop_filter.tot_requests 1183 |
| system.membus.snoop_filter.hit_single_requests 0 |
| system.membus.snoop_filter.hit_multi_requests 0 |
| system.membus.snoop_filter.tot_snoops 0 |
| system.membus.snoop_filter.hit_single_snoops 0 |
| system.membus.snoop_filter.hit_multi_snoops 0 |
| system.membus.pwrStateResidencyTicks::UNDEFINED 277930500 |
| system.membus.trans_dist::ReadResp 961 |
| system.membus.trans_dist::ReadExReq 222 |
| system.membus.trans_dist::ReadExResp 222 |
| system.membus.trans_dist::ReadSharedReq 961 |
| system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 2366 |
| system.membus.pkt_count::total 2366 |
| system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 75712 |
| system.membus.pkt_size::total 75712 |
| system.membus.snoops 0 |
| system.membus.snoopTraffic 0 |
| system.membus.snoop_fanout::samples 1183 |
| system.membus.snoop_fanout::mean 0 |
| system.membus.snoop_fanout::stdev -0 |
| system.membus.snoop_fanout::underflows 0 0.00% 0.00% |
| system.membus.snoop_fanout::0 1183 100.00% 100.00% |
| system.membus.snoop_fanout::1 0 0.00% 100.00% |
| system.membus.snoop_fanout::overflows 0 0.00% 100.00% |
| system.membus.snoop_fanout::min_value 0 |
| system.membus.snoop_fanout::max_value 0 |
| system.membus.snoop_fanout::total 1183 |
| system.membus.reqLayer0.occupancy 1184000 |
| system.membus.reqLayer0.utilization 0.4 |
| system.membus.respLayer1.occupancy 5915000 |
| system.membus.respLayer1.utilization 2.1 |
| |
| ---------- End Simulation Statistics ---------- |
