| |
| ---------- Begin Simulation Statistics ---------- |
| sim_seconds 0.000045 |
| sim_ticks 44698500 |
| final_tick 44698500 |
| sim_freq 1000000000000 |
| host_inst_rate 251543 |
| host_op_rate 251424 |
| host_tick_rate 740962061 |
| host_mem_usage 261496 |
| host_seconds 0.06 |
| sim_insts 15162 |
| sim_ops 15162 |
| system.voltage_domain.voltage 1 |
| system.clk_domain.clock 1000 |
| system.physmem.pwrStateResidencyTicks::UNDEFINED 44698500 |
| system.physmem.bytes_read::cpu.inst 17792 |
| system.physmem.bytes_read::cpu.data 8832 |
| system.physmem.bytes_read::total 26624 |
| system.physmem.bytes_inst_read::cpu.inst 17792 |
| system.physmem.bytes_inst_read::total 17792 |
| system.physmem.num_reads::cpu.inst 278 |
| system.physmem.num_reads::cpu.data 138 |
| system.physmem.num_reads::total 416 |
| system.physmem.bw_read::cpu.inst 398044677 |
| system.physmem.bw_read::cpu.data 197590523 |
| system.physmem.bw_read::total 595635200 |
| system.physmem.bw_inst_read::cpu.inst 398044677 |
| system.physmem.bw_inst_read::total 398044677 |
| system.physmem.bw_total::cpu.inst 398044677 |
| system.physmem.bw_total::cpu.data 197590523 |
| system.physmem.bw_total::total 595635200 |
| system.pwrStateResidencyTicks::UNDEFINED 44698500 |
| system.cpu_clk_domain.clock 500 |
| system.cpu.workload.numSyscalls 18 |
| system.cpu.pwrStateResidencyTicks::ON 44698500 |
| system.cpu.numCycles 89397 |
| system.cpu.numWorkItemsStarted 0 |
| system.cpu.numWorkItemsCompleted 0 |
| system.cpu.committedInsts 15162 |
| system.cpu.committedOps 15162 |
| system.cpu.num_int_alu_accesses 12219 |
| system.cpu.num_fp_alu_accesses 0 |
| system.cpu.num_func_calls 385 |
| system.cpu.num_conditional_control_insts 2434 |
| system.cpu.num_int_insts 12219 |
| system.cpu.num_fp_insts 0 |
| system.cpu.num_int_register_reads 29037 |
| system.cpu.num_int_register_writes 13818 |
| system.cpu.num_fp_register_reads 0 |
| system.cpu.num_fp_register_writes 0 |
| system.cpu.num_mem_refs 3683 |
| system.cpu.num_load_insts 2231 |
| system.cpu.num_store_insts 1452 |
| system.cpu.num_idle_cycles 0 |
| system.cpu.num_busy_cycles 89397 |
| system.cpu.not_idle_fraction 1 |
| system.cpu.idle_fraction 0 |
| system.cpu.Branches 3363 |
| system.cpu.op_class::No_OpClass 726 4.77% 4.77% |
| system.cpu.op_class::IntAlu 10798 71.01% 75.78% |
| system.cpu.op_class::IntMult 0 0.00% 75.78% |
| system.cpu.op_class::IntDiv 0 0.00% 75.78% |
| system.cpu.op_class::FloatAdd 0 0.00% 75.78% |
| system.cpu.op_class::FloatCmp 0 0.00% 75.78% |
| system.cpu.op_class::FloatCvt 0 0.00% 75.78% |
| system.cpu.op_class::FloatMult 0 0.00% 75.78% |
| system.cpu.op_class::FloatMultAcc 0 0.00% 75.78% |
| system.cpu.op_class::FloatDiv 0 0.00% 75.78% |
| system.cpu.op_class::FloatMisc 0 0.00% 75.78% |
| system.cpu.op_class::FloatSqrt 0 0.00% 75.78% |
| system.cpu.op_class::SimdAdd 0 0.00% 75.78% |
| system.cpu.op_class::SimdAddAcc 0 0.00% 75.78% |
| system.cpu.op_class::SimdAlu 0 0.00% 75.78% |
| system.cpu.op_class::SimdCmp 0 0.00% 75.78% |
| system.cpu.op_class::SimdCvt 0 0.00% 75.78% |
| system.cpu.op_class::SimdMisc 0 0.00% 75.78% |
| system.cpu.op_class::SimdMult 0 0.00% 75.78% |
| system.cpu.op_class::SimdMultAcc 0 0.00% 75.78% |
| system.cpu.op_class::SimdShift 0 0.00% 75.78% |
| system.cpu.op_class::SimdShiftAcc 0 0.00% 75.78% |
| system.cpu.op_class::SimdSqrt 0 0.00% 75.78% |
| system.cpu.op_class::SimdFloatAdd 0 0.00% 75.78% |
| system.cpu.op_class::SimdFloatAlu 0 0.00% 75.78% |
| system.cpu.op_class::SimdFloatCmp 0 0.00% 75.78% |
| system.cpu.op_class::SimdFloatCvt 0 0.00% 75.78% |
| system.cpu.op_class::SimdFloatDiv 0 0.00% 75.78% |
| system.cpu.op_class::SimdFloatMisc 0 0.00% 75.78% |
| system.cpu.op_class::SimdFloatMult 0 0.00% 75.78% |
| system.cpu.op_class::SimdFloatMultAcc 0 0.00% 75.78% |
| system.cpu.op_class::SimdFloatSqrt 0 0.00% 75.78% |
| system.cpu.op_class::MemRead 2231 14.67% 90.45% |
| system.cpu.op_class::MemWrite 1452 9.55% 100.00% |
| system.cpu.op_class::FloatMemRead 0 0.00% 100.00% |
| system.cpu.op_class::FloatMemWrite 0 0.00% 100.00% |
| system.cpu.op_class::IprAccess 0 0.00% 100.00% |
| system.cpu.op_class::InstPrefetch 0 0.00% 100.00% |
| system.cpu.op_class::total 15207 |
| system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 44698500 |
| system.cpu.dcache.tags.replacements 0 |
| system.cpu.dcache.tags.tagsinuse 97.037351 |
| system.cpu.dcache.tags.total_refs 3535 |
| system.cpu.dcache.tags.sampled_refs 138 |
| system.cpu.dcache.tags.avg_refs 25.615942 |
| system.cpu.dcache.tags.warmup_cycle 0 |
| system.cpu.dcache.tags.occ_blocks::cpu.data 97.037351 |
| system.cpu.dcache.tags.occ_percent::cpu.data 0.023691 |
| system.cpu.dcache.tags.occ_percent::total 0.023691 |
| system.cpu.dcache.tags.occ_task_id_blocks::1024 138 |
| system.cpu.dcache.tags.age_task_id_blocks_1024::0 11 |
| system.cpu.dcache.tags.age_task_id_blocks_1024::1 127 |
| system.cpu.dcache.tags.occ_task_id_percent::1024 0.033691 |
| system.cpu.dcache.tags.tag_accesses 7484 |
| system.cpu.dcache.tags.data_accesses 7484 |
| system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 44698500 |
| system.cpu.dcache.ReadReq_hits::cpu.data 2172 |
| system.cpu.dcache.ReadReq_hits::total 2172 |
| system.cpu.dcache.WriteReq_hits::cpu.data 1357 |
| system.cpu.dcache.WriteReq_hits::total 1357 |
| system.cpu.dcache.SwapReq_hits::cpu.data 6 |
| system.cpu.dcache.SwapReq_hits::total 6 |
| system.cpu.dcache.demand_hits::cpu.data 3529 |
| system.cpu.dcache.demand_hits::total 3529 |
| system.cpu.dcache.overall_hits::cpu.data 3529 |
| system.cpu.dcache.overall_hits::total 3529 |
| system.cpu.dcache.ReadReq_misses::cpu.data 53 |
| system.cpu.dcache.ReadReq_misses::total 53 |
| system.cpu.dcache.WriteReq_misses::cpu.data 85 |
| system.cpu.dcache.WriteReq_misses::total 85 |
| system.cpu.dcache.demand_misses::cpu.data 138 |
| system.cpu.dcache.demand_misses::total 138 |
| system.cpu.dcache.overall_misses::cpu.data 138 |
| system.cpu.dcache.overall_misses::total 138 |
| system.cpu.dcache.ReadReq_miss_latency::cpu.data 3339000 |
| system.cpu.dcache.ReadReq_miss_latency::total 3339000 |
| system.cpu.dcache.WriteReq_miss_latency::cpu.data 5355000 |
| system.cpu.dcache.WriteReq_miss_latency::total 5355000 |
| system.cpu.dcache.demand_miss_latency::cpu.data 8694000 |
| system.cpu.dcache.demand_miss_latency::total 8694000 |
| system.cpu.dcache.overall_miss_latency::cpu.data 8694000 |
| system.cpu.dcache.overall_miss_latency::total 8694000 |
| system.cpu.dcache.ReadReq_accesses::cpu.data 2225 |
| system.cpu.dcache.ReadReq_accesses::total 2225 |
| system.cpu.dcache.WriteReq_accesses::cpu.data 1442 |
| system.cpu.dcache.WriteReq_accesses::total 1442 |
| system.cpu.dcache.SwapReq_accesses::cpu.data 6 |
| system.cpu.dcache.SwapReq_accesses::total 6 |
| system.cpu.dcache.demand_accesses::cpu.data 3667 |
| system.cpu.dcache.demand_accesses::total 3667 |
| system.cpu.dcache.overall_accesses::cpu.data 3667 |
| system.cpu.dcache.overall_accesses::total 3667 |
| system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.023820 |
| system.cpu.dcache.ReadReq_miss_rate::total 0.023820 |
| system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.058946 |
| system.cpu.dcache.WriteReq_miss_rate::total 0.058946 |
| system.cpu.dcache.demand_miss_rate::cpu.data 0.037633 |
| system.cpu.dcache.demand_miss_rate::total 0.037633 |
| system.cpu.dcache.overall_miss_rate::cpu.data 0.037633 |
| system.cpu.dcache.overall_miss_rate::total 0.037633 |
| system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 |
| system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 |
| system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 |
| system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 |
| system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 |
| system.cpu.dcache.demand_avg_miss_latency::total 63000 |
| system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 |
| system.cpu.dcache.overall_avg_miss_latency::total 63000 |
| system.cpu.dcache.blocked_cycles::no_mshrs 0 |
| system.cpu.dcache.blocked_cycles::no_targets 0 |
| system.cpu.dcache.blocked::no_mshrs 0 |
| system.cpu.dcache.blocked::no_targets 0 |
| system.cpu.dcache.avg_blocked_cycles::no_mshrs nan |
| system.cpu.dcache.avg_blocked_cycles::no_targets nan |
| system.cpu.dcache.ReadReq_mshr_misses::cpu.data 53 |
| system.cpu.dcache.ReadReq_mshr_misses::total 53 |
| system.cpu.dcache.WriteReq_mshr_misses::cpu.data 85 |
| system.cpu.dcache.WriteReq_mshr_misses::total 85 |
| system.cpu.dcache.demand_mshr_misses::cpu.data 138 |
| system.cpu.dcache.demand_mshr_misses::total 138 |
| system.cpu.dcache.overall_mshr_misses::cpu.data 138 |
| system.cpu.dcache.overall_mshr_misses::total 138 |
| system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3286000 |
| system.cpu.dcache.ReadReq_mshr_miss_latency::total 3286000 |
| system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5270000 |
| system.cpu.dcache.WriteReq_mshr_miss_latency::total 5270000 |
| system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8556000 |
| system.cpu.dcache.demand_mshr_miss_latency::total 8556000 |
| system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8556000 |
| system.cpu.dcache.overall_mshr_miss_latency::total 8556000 |
| system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.023820 |
| system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.023820 |
| system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.058946 |
| system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.058946 |
| system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037633 |
| system.cpu.dcache.demand_mshr_miss_rate::total 0.037633 |
| system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037633 |
| system.cpu.dcache.overall_mshr_miss_rate::total 0.037633 |
| system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 |
| system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 |
| system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 |
| system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 |
| system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 |
| system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 |
| system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 |
| system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 |
| system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 44698500 |
| system.cpu.icache.tags.replacements 0 |
| system.cpu.icache.tags.tagsinuse 151.480746 |
| system.cpu.icache.tags.total_refs 14928 |
| system.cpu.icache.tags.sampled_refs 280 |
| system.cpu.icache.tags.avg_refs 53.314286 |
| system.cpu.icache.tags.warmup_cycle 0 |
| system.cpu.icache.tags.occ_blocks::cpu.inst 151.480746 |
| system.cpu.icache.tags.occ_percent::cpu.inst 0.073965 |
| system.cpu.icache.tags.occ_percent::total 0.073965 |
| system.cpu.icache.tags.occ_task_id_blocks::1024 280 |
| system.cpu.icache.tags.age_task_id_blocks_1024::0 45 |
| system.cpu.icache.tags.age_task_id_blocks_1024::1 235 |
| system.cpu.icache.tags.occ_task_id_percent::1024 0.136719 |
| system.cpu.icache.tags.tag_accesses 30696 |
| system.cpu.icache.tags.data_accesses 30696 |
| system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 44698500 |
| system.cpu.icache.ReadReq_hits::cpu.inst 14928 |
| system.cpu.icache.ReadReq_hits::total 14928 |
| system.cpu.icache.demand_hits::cpu.inst 14928 |
| system.cpu.icache.demand_hits::total 14928 |
| system.cpu.icache.overall_hits::cpu.inst 14928 |
| system.cpu.icache.overall_hits::total 14928 |
| system.cpu.icache.ReadReq_misses::cpu.inst 280 |
| system.cpu.icache.ReadReq_misses::total 280 |
| system.cpu.icache.demand_misses::cpu.inst 280 |
| system.cpu.icache.demand_misses::total 280 |
| system.cpu.icache.overall_misses::cpu.inst 280 |
| system.cpu.icache.overall_misses::total 280 |
| system.cpu.icache.ReadReq_miss_latency::cpu.inst 17542500 |
| system.cpu.icache.ReadReq_miss_latency::total 17542500 |
| system.cpu.icache.demand_miss_latency::cpu.inst 17542500 |
| system.cpu.icache.demand_miss_latency::total 17542500 |
| system.cpu.icache.overall_miss_latency::cpu.inst 17542500 |
| system.cpu.icache.overall_miss_latency::total 17542500 |
| system.cpu.icache.ReadReq_accesses::cpu.inst 15208 |
| system.cpu.icache.ReadReq_accesses::total 15208 |
| system.cpu.icache.demand_accesses::cpu.inst 15208 |
| system.cpu.icache.demand_accesses::total 15208 |
| system.cpu.icache.overall_accesses::cpu.inst 15208 |
| system.cpu.icache.overall_accesses::total 15208 |
| system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.018411 |
| system.cpu.icache.ReadReq_miss_rate::total 0.018411 |
| system.cpu.icache.demand_miss_rate::cpu.inst 0.018411 |
| system.cpu.icache.demand_miss_rate::total 0.018411 |
| system.cpu.icache.overall_miss_rate::cpu.inst 0.018411 |
| system.cpu.icache.overall_miss_rate::total 0.018411 |
| system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62651.785714 |
| system.cpu.icache.ReadReq_avg_miss_latency::total 62651.785714 |
| system.cpu.icache.demand_avg_miss_latency::cpu.inst 62651.785714 |
| system.cpu.icache.demand_avg_miss_latency::total 62651.785714 |
| system.cpu.icache.overall_avg_miss_latency::cpu.inst 62651.785714 |
| system.cpu.icache.overall_avg_miss_latency::total 62651.785714 |
| system.cpu.icache.blocked_cycles::no_mshrs 0 |
| system.cpu.icache.blocked_cycles::no_targets 0 |
| system.cpu.icache.blocked::no_mshrs 0 |
| system.cpu.icache.blocked::no_targets 0 |
| system.cpu.icache.avg_blocked_cycles::no_mshrs nan |
| system.cpu.icache.avg_blocked_cycles::no_targets nan |
| system.cpu.icache.ReadReq_mshr_misses::cpu.inst 280 |
| system.cpu.icache.ReadReq_mshr_misses::total 280 |
| system.cpu.icache.demand_mshr_misses::cpu.inst 280 |
| system.cpu.icache.demand_mshr_misses::total 280 |
| system.cpu.icache.overall_mshr_misses::cpu.inst 280 |
| system.cpu.icache.overall_mshr_misses::total 280 |
| system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17262500 |
| system.cpu.icache.ReadReq_mshr_miss_latency::total 17262500 |
| system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17262500 |
| system.cpu.icache.demand_mshr_miss_latency::total 17262500 |
| system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17262500 |
| system.cpu.icache.overall_mshr_miss_latency::total 17262500 |
| system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.018411 |
| system.cpu.icache.ReadReq_mshr_miss_rate::total 0.018411 |
| system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.018411 |
| system.cpu.icache.demand_mshr_miss_rate::total 0.018411 |
| system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.018411 |
| system.cpu.icache.overall_mshr_miss_rate::total 0.018411 |
| system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61651.785714 |
| system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61651.785714 |
| system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61651.785714 |
| system.cpu.icache.demand_avg_mshr_miss_latency::total 61651.785714 |
| system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61651.785714 |
| system.cpu.icache.overall_avg_mshr_miss_latency::total 61651.785714 |
| system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 44698500 |
| system.cpu.l2cache.tags.replacements 0 |
| system.cpu.l2cache.tags.tagsinuse 247.870917 |
| system.cpu.l2cache.tags.total_refs 2 |
| system.cpu.l2cache.tags.sampled_refs 416 |
| system.cpu.l2cache.tags.avg_refs 0.004808 |
| system.cpu.l2cache.tags.warmup_cycle 0 |
| system.cpu.l2cache.tags.occ_blocks::cpu.inst 150.801148 |
| system.cpu.l2cache.tags.occ_blocks::cpu.data 97.069768 |
| system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004602 |
| system.cpu.l2cache.tags.occ_percent::cpu.data 0.002962 |
| system.cpu.l2cache.tags.occ_percent::total 0.007564 |
| system.cpu.l2cache.tags.occ_task_id_blocks::1024 416 |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::0 55 |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::1 361 |
| system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012695 |
| system.cpu.l2cache.tags.tag_accesses 3760 |
| system.cpu.l2cache.tags.data_accesses 3760 |
| system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 44698500 |
| system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 |
| system.cpu.l2cache.ReadCleanReq_hits::total 2 |
| system.cpu.l2cache.demand_hits::cpu.inst 2 |
| system.cpu.l2cache.demand_hits::total 2 |
| system.cpu.l2cache.overall_hits::cpu.inst 2 |
| system.cpu.l2cache.overall_hits::total 2 |
| system.cpu.l2cache.ReadExReq_misses::cpu.data 85 |
| system.cpu.l2cache.ReadExReq_misses::total 85 |
| system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 278 |
| system.cpu.l2cache.ReadCleanReq_misses::total 278 |
| system.cpu.l2cache.ReadSharedReq_misses::cpu.data 53 |
| system.cpu.l2cache.ReadSharedReq_misses::total 53 |
| system.cpu.l2cache.demand_misses::cpu.inst 278 |
| system.cpu.l2cache.demand_misses::cpu.data 138 |
| system.cpu.l2cache.demand_misses::total 416 |
| system.cpu.l2cache.overall_misses::cpu.inst 278 |
| system.cpu.l2cache.overall_misses::cpu.data 138 |
| system.cpu.l2cache.overall_misses::total 416 |
| system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5142500 |
| system.cpu.l2cache.ReadExReq_miss_latency::total 5142500 |
| system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 16819500 |
| system.cpu.l2cache.ReadCleanReq_miss_latency::total 16819500 |
| system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 3206500 |
| system.cpu.l2cache.ReadSharedReq_miss_latency::total 3206500 |
| system.cpu.l2cache.demand_miss_latency::cpu.inst 16819500 |
| system.cpu.l2cache.demand_miss_latency::cpu.data 8349000 |
| system.cpu.l2cache.demand_miss_latency::total 25168500 |
| system.cpu.l2cache.overall_miss_latency::cpu.inst 16819500 |
| system.cpu.l2cache.overall_miss_latency::cpu.data 8349000 |
| system.cpu.l2cache.overall_miss_latency::total 25168500 |
| system.cpu.l2cache.ReadExReq_accesses::cpu.data 85 |
| system.cpu.l2cache.ReadExReq_accesses::total 85 |
| system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 280 |
| system.cpu.l2cache.ReadCleanReq_accesses::total 280 |
| system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 53 |
| system.cpu.l2cache.ReadSharedReq_accesses::total 53 |
| system.cpu.l2cache.demand_accesses::cpu.inst 280 |
| system.cpu.l2cache.demand_accesses::cpu.data 138 |
| system.cpu.l2cache.demand_accesses::total 418 |
| system.cpu.l2cache.overall_accesses::cpu.inst 280 |
| system.cpu.l2cache.overall_accesses::cpu.data 138 |
| system.cpu.l2cache.overall_accesses::total 418 |
| system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 |
| system.cpu.l2cache.ReadExReq_miss_rate::total 1 |
| system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.992857 |
| system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.992857 |
| system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 |
| system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 |
| system.cpu.l2cache.demand_miss_rate::cpu.inst 0.992857 |
| system.cpu.l2cache.demand_miss_rate::cpu.data 1 |
| system.cpu.l2cache.demand_miss_rate::total 0.995215 |
| system.cpu.l2cache.overall_miss_rate::cpu.inst 0.992857 |
| system.cpu.l2cache.overall_miss_rate::cpu.data 1 |
| system.cpu.l2cache.overall_miss_rate::total 0.995215 |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 |
| system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.798561 |
| system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.798561 |
| system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 |
| system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.798561 |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 |
| system.cpu.l2cache.demand_avg_miss_latency::total 60501.201923 |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.798561 |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 |
| system.cpu.l2cache.overall_avg_miss_latency::total 60501.201923 |
| system.cpu.l2cache.blocked_cycles::no_mshrs 0 |
| system.cpu.l2cache.blocked_cycles::no_targets 0 |
| system.cpu.l2cache.blocked::no_mshrs 0 |
| system.cpu.l2cache.blocked::no_targets 0 |
| system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan |
| system.cpu.l2cache.avg_blocked_cycles::no_targets nan |
| system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 85 |
| system.cpu.l2cache.ReadExReq_mshr_misses::total 85 |
| system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 278 |
| system.cpu.l2cache.ReadCleanReq_mshr_misses::total 278 |
| system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 53 |
| system.cpu.l2cache.ReadSharedReq_mshr_misses::total 53 |
| system.cpu.l2cache.demand_mshr_misses::cpu.inst 278 |
| system.cpu.l2cache.demand_mshr_misses::cpu.data 138 |
| system.cpu.l2cache.demand_mshr_misses::total 416 |
| system.cpu.l2cache.overall_mshr_misses::cpu.inst 278 |
| system.cpu.l2cache.overall_mshr_misses::cpu.data 138 |
| system.cpu.l2cache.overall_mshr_misses::total 416 |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4292500 |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4292500 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14039500 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14039500 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 2676500 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 2676500 |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14039500 |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6969000 |
| system.cpu.l2cache.demand_mshr_miss_latency::total 21008500 |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14039500 |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6969000 |
| system.cpu.l2cache.overall_mshr_miss_latency::total 21008500 |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.992857 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.992857 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.992857 |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 |
| system.cpu.l2cache.demand_mshr_miss_rate::total 0.995215 |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.992857 |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 |
| system.cpu.l2cache.overall_mshr_miss_rate::total 0.995215 |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.798561 |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.798561 |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.798561 |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.201923 |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.798561 |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.201923 |
| system.cpu.toL2Bus.snoop_filter.tot_requests 418 |
| system.cpu.toL2Bus.snoop_filter.hit_single_requests 2 |
| system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 |
| system.cpu.toL2Bus.snoop_filter.tot_snoops 0 |
| system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 |
| system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 |
| system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 44698500 |
| system.cpu.toL2Bus.trans_dist::ReadResp 333 |
| system.cpu.toL2Bus.trans_dist::ReadExReq 85 |
| system.cpu.toL2Bus.trans_dist::ReadExResp 85 |
| system.cpu.toL2Bus.trans_dist::ReadCleanReq 280 |
| system.cpu.toL2Bus.trans_dist::ReadSharedReq 53 |
| system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 560 |
| system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 |
| system.cpu.toL2Bus.pkt_count::total 836 |
| system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 17920 |
| system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 |
| system.cpu.toL2Bus.pkt_size::total 26752 |
| system.cpu.toL2Bus.snoops 0 |
| system.cpu.toL2Bus.snoopTraffic 0 |
| system.cpu.toL2Bus.snoop_fanout::samples 418 |
| system.cpu.toL2Bus.snoop_fanout::mean 0.004785 |
| system.cpu.toL2Bus.snoop_fanout::stdev 0.069088 |
| system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% |
| system.cpu.toL2Bus.snoop_fanout::0 416 99.52% 99.52% |
| system.cpu.toL2Bus.snoop_fanout::1 2 0.48% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::min_value 0 |
| system.cpu.toL2Bus.snoop_fanout::max_value 1 |
| system.cpu.toL2Bus.snoop_fanout::total 418 |
| system.cpu.toL2Bus.reqLayer0.occupancy 209000 |
| system.cpu.toL2Bus.reqLayer0.utilization 0.5 |
| system.cpu.toL2Bus.respLayer0.occupancy 420000 |
| system.cpu.toL2Bus.respLayer0.utilization 0.9 |
| system.cpu.toL2Bus.respLayer1.occupancy 207000 |
| system.cpu.toL2Bus.respLayer1.utilization 0.5 |
| system.membus.snoop_filter.tot_requests 416 |
| system.membus.snoop_filter.hit_single_requests 0 |
| system.membus.snoop_filter.hit_multi_requests 0 |
| system.membus.snoop_filter.tot_snoops 0 |
| system.membus.snoop_filter.hit_single_snoops 0 |
| system.membus.snoop_filter.hit_multi_snoops 0 |
| system.membus.pwrStateResidencyTicks::UNDEFINED 44698500 |
| system.membus.trans_dist::ReadResp 331 |
| system.membus.trans_dist::ReadExReq 85 |
| system.membus.trans_dist::ReadExResp 85 |
| system.membus.trans_dist::ReadSharedReq 331 |
| system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 832 |
| system.membus.pkt_count::total 832 |
| system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 26624 |
| system.membus.pkt_size::total 26624 |
| system.membus.snoops 0 |
| system.membus.snoopTraffic 0 |
| system.membus.snoop_fanout::samples 416 |
| system.membus.snoop_fanout::mean 0 |
| system.membus.snoop_fanout::stdev 0 |
| system.membus.snoop_fanout::underflows 0 0.00% 0.00% |
| system.membus.snoop_fanout::0 416 100.00% 100.00% |
| system.membus.snoop_fanout::1 0 0.00% 100.00% |
| system.membus.snoop_fanout::overflows 0 0.00% 100.00% |
| system.membus.snoop_fanout::min_value 0 |
| system.membus.snoop_fanout::max_value 0 |
| system.membus.snoop_fanout::total 416 |
| system.membus.reqLayer0.occupancy 416500 |
| system.membus.reqLayer0.utilization 0.9 |
| system.membus.respLayer1.occupancy 2080000 |
| system.membus.respLayer1.utilization 4.7 |
| |
| ---------- End Simulation Statistics ---------- |
