| // -*- mode:c++ -*- | |
| // Copyright (c) 2010, 2012, 2017 ARM Limited | |
| // All rights reserved | |
| // | |
| // The license below extends only to copyright in the software and shall | |
| // not be construed as granting a license to any other intellectual | |
| // property including but not limited to intellectual property relating | |
| // to a hardware implementation of the functionality of the software | |
| // licensed hereunder. You may use the software subject to the license | |
| // terms below provided that you ensure that this notice is replicated | |
| // unmodified and in its entirety in all distributions of the software, | |
| // modified or unmodified, in source code or in binary form. | |
| // | |
| // Copyright (c) 2007-2008 The Florida State University | |
| // All rights reserved. | |
| // | |
| // Redistribution and use in source and binary forms, with or without | |
| // modification, are permitted provided that the following conditions are | |
| // met: redistributions of source code must retain the above copyright | |
| // notice, this list of conditions and the following disclaimer; | |
| // redistributions in binary form must reproduce the above copyright | |
| // notice, this list of conditions and the following disclaimer in the | |
| // documentation and/or other materials provided with the distribution; | |
| // neither the name of the copyright holders nor the names of its | |
| // contributors may be used to endorse or promote products derived from | |
| // this software without specific prior written permission. | |
| // | |
| // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
| // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
| // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR | |
| // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
| // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, | |
| // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT | |
| // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, | |
| // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY | |
| // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
| // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE | |
| // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
| // | |
| // Authors: Stephen Hines | |
| //////////////////////////////////////////////////////////////////// | |
| // | |
| // Output include file directives. | |
| // | |
| output header {{ | |
| #include <iostream> | |
| #include <sstream> | |
| #include "arch/arm/insts/branch.hh" | |
| #include "arch/arm/insts/branch64.hh" | |
| #include "arch/arm/insts/data64.hh" | |
| #include "arch/arm/insts/fplib.hh" | |
| #include "arch/arm/insts/macromem.hh" | |
| #include "arch/arm/insts/mem.hh" | |
| #include "arch/arm/insts/mem64.hh" | |
| #include "arch/arm/insts/misc.hh" | |
| #include "arch/arm/insts/misc64.hh" | |
| #include "arch/arm/insts/mult.hh" | |
| #include "arch/arm/insts/neon64_mem.hh" | |
| #include "arch/arm/insts/pred_inst.hh" | |
| #include "arch/arm/insts/pseudo.hh" | |
| #include "arch/arm/insts/static_inst.hh" | |
| #include "arch/arm/insts/vfp.hh" | |
| #include "arch/arm/isa_traits.hh" | |
| #include "mem/packet.hh" | |
| #include "sim/faults.hh" | |
| #include "enums/DecoderFlavour.hh" | |
| }}; | |
| output decoder {{ | |
| #include <string> | |
| #include <gem5/asm/generic/m5ops.h> | |
| #include "arch/arm/decoder.hh" | |
| #include "arch/arm/faults.hh" | |
| #include "arch/arm/intregs.hh" | |
| #include "arch/arm/isa_traits.hh" | |
| #include "arch/arm/utility.hh" | |
| #include "base/loader/symtab.hh" | |
| #include "base/cprintf.hh" | |
| #include "cpu/thread_context.hh" | |
| using namespace ArmISA; | |
| }}; | |
| output exec {{ | |
| #include <cmath> | |
| #include "arch/arm/faults.hh" | |
| #include "arch/arm/isa_traits.hh" | |
| #include "arch/arm/utility.hh" | |
| #include "arch/generic/memhelpers.hh" | |
| #include "base/condcodes.hh" | |
| #include "base/crc.hh" | |
| #include "cpu/base.hh" | |
| #include "sim/pseudo_inst.hh" | |
| #if defined(linux) | |
| #include <fenv.h> | |
| #endif | |
| #include "base/cp_annotate.hh" | |
| #include "debug/Arm.hh" | |
| #include "mem/packet.hh" | |
| #include "mem/packet_access.hh" | |
| #include "sim/sim_exit.hh" | |
| using namespace ArmISA; | |
| }}; | |